JP3531743B2 - Test pattern generator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to internal wiring connection verification in the development stage of a semiconductor chip, and more particularly to a test pattern generation device which facilitates creation of a test pattern used for internal wiring connection verification.

[0002]

2. Description of the Related Art Conventionally, connection verification of internal wiring in the development stage of a semiconductor chip is performed by a test in which all pin connections can be confirmed according to a pin assignment table that describes input pins and output pins of test waveforms for each test mode. The pattern was created manually, and the simulation was performed together with the designed circuit.

FIG. 25 is a circuit diagram showing an example of a semiconductor chip for verifying wiring connection by such a conventional method.
FIG. 26 is a diagram showing input patterns and output patterns for verifying the circuit of FIG.

In FIG. 25, a semiconductor chip 2500
Selects the input from the external input pad according to the mode value input from the external input pads 2501 and 2502, the functional blocks 2508, 2509 and 2510, and the mode control pads 2520, 2521 and 2522, and Output multiplexers 2505 and 25
06, 2507, a multiplexer 2517 for selecting the output of the functional block according to the mode value and outputting it to the external output pad 2519, and the external input IO 2503, 2
504, 2523, 2524, 2525 and an IO 2518 for external output.

The conventional connection verification method is based on the functional block 25.
A mode for inputting a test pattern from the external input pad 2501 to 08 and verifying the pattern output to the external output pad 2519 will be described as an example. First,
The input pin 2511 of the functional block is the external input pad 2
Mode control pads 2520-2 so that the mode becomes controllable from 501 and outputs from the output pin 2514 of the functional block to the external output pad 2519.
Set an appropriate mode value to 522.

The function block 2508 is operated in this mode, the input pattern 2600 shown in FIG. 26 is input to the external input pad 2501, and it is confirmed whether this is the same as the observation pattern 2601 at the input pin 2511 of the function block 2508. To do. Next, the output pattern 2602 output to the output pin 2514 of the functional block 2508 and the observation pattern 260 on the external output pad 2519.
Check if 3 is the same.

[0007]

However, in the conventional connection verification method, as shown in FIG. 26, a complicated pattern for operating the internal function block from the external input pad and the output to the external output pad are output. It is necessary to create expected value patterns, and as the number of modes and the number of pads for external input / output increase with the increase in circuit scale, the number of patterns to be created also increases in proportion to the increase in the number of patterns and the wiring inside the semiconductor chip. There was a problem that the number of man-hours for connection verification increased significantly.

The present invention has been made in view of the above circumstances, and in connection verification of internal wiring of a semiconductor chip,
Enables a connection verification method that can automatically generate test patterns used for connection verification without the need to create complicated patterns for operating functional blocks, and can significantly reduce the number of pattern creation steps. It is an object of the present invention to provide a test pattern generator that operates.

[0009]

In order to solve the above-mentioned conventional problems, a connection verification method using a test pattern generator according to the present invention performs mode value setting from a mode input pad and verifies the input side. In the case of, only the pulse signal is input from the pad for external input, it is confirmed whether the pulse signal reaches the function block input terminal, and in the verification of the output side, only the pulse signal is forcibly input to the function block output terminal. However, the creation of a complicated test pattern is omitted by confirming whether the pulse signal forcibly input to the external output pad has arrived. At that time, the mode value, the input side connection information, and the output side connection information are described in the connection table, and the test pattern is automatically generated from this table, thereby significantly reducing the test pattern creation man-hours.

A test pattern generator according to claim 1 of the present invention comprises a plurality of functional blocks (functional block 101,
102, 103) and a multiplexer (multiplexer 13, 116) for selectively outputting the output signal of the functional block according to the mode designation input to the mode control pad.
And a test pattern generator for verifying connection to a semiconductor chip (semiconductor chip 100) having an external output pad (external output pads 115, 118) for outputting the output of the multiplexer to the outside,
A connection table (connection table 200) in which the correspondence relationship between the output signal pins (function block output pins 104, 105, 106) of the functional blocks whose connection is selected to the external output pad by the mode designation is described for each mode. )in accordance with,
Output signal pins of the functional block selected by the mode designation (functional block output pins 104, 105, 10
6) Pulse waveforms (H pulse waveforms 306, 307, 310, 31) forcibly input with a time difference for each
1), 314, 315) and a check waveform (expected value waveform 308, 309, 312, 3) for verifying the matching of the signal waveforms at the external output pads.
13, 316, 317), and means for generating.

According to the test pattern generator of the first aspect, according to the connection table describing the correspondence from the output signal pin of the functional block to the external output pad for each mode,
Since the pulse waveform forcibly input to the output signal pin of the functional block and the inspection waveform to be verified at the external output pad can be obtained for each mode, it is not necessary to create complicated test patterns and expected value patterns, and connection is possible. Since the test pattern can be automatically generated from the table, the number of man-hours required to create the test pattern can be significantly reduced.

A test pattern generator according to a second aspect of the present invention is an external input pad (external input pad 41).
3 and 416) and multiplexers (multiplexers 415 and 41) for selectively inputting an input signal from the external input pad according to mode designation input to the mode control pad.
8, 427) and a plurality of functional blocks (functional blocks 401, 402, 4) for inputting the output of the multiplexer.
03) and a semiconductor chip (semiconductor chip 10
0) in the test pattern generator for verifying the connection, the input signal pins (function block input pins 404, 405, 406) of the function block whose connection is selected by the mode designation with respect to the external input pad.
Connection table (connection table 5)
00), pulse waveforms (H pulse waveforms 608, 609, 612, 613, 616, 6) input to the external input pads with a time lag for each mode.
17) and an inspection waveform (expected value waveform 6
06, 607, 610, 611, 614, 615).

According to the test pattern generator of the second aspect, according to the connection table describing the correspondence from the external input pad to the input signal pin of the functional block for each mode,
The pulse waveform input to the external input pad for each mode and the inspection waveform to be verified at the input signal pin of the functional block can be obtained, making it unnecessary to create complicated test patterns and expected value patterns. Since the test pattern can be automatically generated, it is possible to significantly reduce the number of test pattern creation steps.

A test pattern generator according to a third aspect of the present invention is an external input pad (external input pad 70).
1) and an input AND control type IO (input AND control type IO702) that receives an input signal from the external input pad.
And a first selectively outputting the output of the input AND control type IO according to the mode designation value N input to the mode control pad.
Multiplexer (multiplexer 703), a functional block (functional block 710) for inputting the output of the first multiplexer, and one of the functions depending on the mode designation value N as an input to the control pin of the input AND control type IO. In a test pattern generator for verifying connection to a semiconductor chip (semiconductor chip 700) having a second multiplexer (multiplexer 714) for selectively outputting an output signal of a block, the mode is applied to the external input pad. The correspondence relationship between the input signal pins of the functional block whose connection is selected by the designated value N and the output signal pin of the functional block whose connection is selected by the mode designated value N with respect to the control pin of the input AND control type IO. Connection table describing the correspondence (connection table 800)
According to the external input pad and the mode designation value N
Means for generating pulse waveforms (L pulse waveform 905, H pulse waveform 907) forcibly input with a time difference at the mode designating value N for each output signal pin of the functional block selected by N
Check waveforms (expected value waveform 9
06,908).

According to the test pattern generating apparatus of the third aspect, even when the semiconductor chip includes the input AND control type IO, it receives the input signal from the external input pad and the output thereof is the mode designating value N. Describes the correspondence relationship that is selected by the input signal pin of the function block and the correspondence relationship between the output signal pin of any function block that is also selected by the mode designation value N and the control pin of the input AND control type IO. According to the connection table, the pulse waveform forcibly input to the pad for external input and the output signal pin of the functional block, and the input signal pin and input AN of the functional block
Since the inspection waveform to be verified at the control pin of the D control type IO can be obtained, it is not necessary to create a complicated test pattern or expected value pattern, and the test pattern can be automatically generated from the connection table. It is possible to significantly reduce the number of preparation steps.

A test pattern generator according to a fourth aspect of the present invention is an external input pad (external input pad 100
1) and an input OR control type IO (input OR control type IO1002) that receives an input signal from the external input pad.
A first multiplexer (multiplexer 1003) that selectively outputs the output of the input OR control type IO according to the mode designation value N input to the mode control pad, and a functional block (function that inputs the output of the first multiplexer). A semiconductor chip having a block 1010) and a second multiplexer (multiplexer 1014) for selectively outputting an output signal of any functional block according to the mode designation value N as an input to a control pin of the input OR control type IO. In a test pattern generation device for verifying connection to (semiconductor chip 1000), correspondence between input signal pins of a functional block whose connection is selected by the mode designating value N with respect to the external input pad, and the input. Depending on the mode designation value N for the control pin of the OR control type IO Connection table connection is describing the corresponding relationship between the output signal pins of the functional blocks to be selected (connection table 11
00), a pulse waveform (H pulse waveform 1205, H pulse waveform 1205, forcibly input to the output signal pin of the functional block selected by the external input pad and the mode designating value N with a time difference at the mode designating value N, respectively.
1027) and an input signal pin of a functional block selected by the mode designating value N and a control pin of the input OR control type IO, a check waveform (an expected value waveform) 120
6, 1208) is generated.

According to the test pattern generating apparatus of the fourth aspect, even when the semiconductor chip includes the input OR control type IO, it receives the input signal from the external input pad,
Correspondence in which the output is selected by the mode designation value N and input to the input signal pin of the functional block, and the control of the input OR control type IO from the output signal pin of any one of the functional blocks also selected by the mode designation value N Inspection to verify the pulse waveform forcibly input to the external input pad and the output signal pin of the functional block and the input signal pin of the functional block and the control pin of the input OR control type IO according to the connection table describing the correspondence to the pins Since waveforms can be obtained, it is not necessary to create complicated test patterns or expected value patterns, and test patterns can be automatically generated from the connection table, which can significantly reduce the number of test pattern creation steps. .

A test pattern generator according to a fifth aspect of the present invention is a functional block (functional blocks 1310, 13).
11), a first multiplexer (multiplexer 1303) that selectively outputs the output signal of the functional block according to the mode designation value N input to the mode control pad, and an output tristate that receives the output of the first multiplexer. Control type IO (output tristate control type IO1
302), an external output pad (external output pad 1301) for outputting the output of the output tristate control type IO to the outside, and the mode designation value N as an input to a control pin of the output tristate control type IO. In the test pattern generator for verifying the connection to the semiconductor chip (semiconductor chip 1300) having the second multiplexer (multiplexer 1311) that selectively outputs the output signal of any one of the functional blocks by the pad for external output. With respect to the output signal pin of the functional block whose connection is selected by the mode designating value N, and the function by which the connection is selected by the mode designating value N for the control pin of the output tristate control type IO. In the connection table (connection table 1400) that describes the correspondence between the block output signal pins A pulse waveform (L pulse waveform 1505, H pulse waveform 1507) forcibly input with a time lag at the mode designation value N is generated for each output signal pin of the functional block selected by the mode designation value N. Means and means for generating inspection waveforms (expected value waveforms 1506, 1508, 1509) for verifying the matching of the signal waveforms at the external output pad and the control pin of the output tristate control type IO, respectively. Is.

According to a fifth aspect of the test pattern generator, the semiconductor chip is an output tristate control type IO.
Even when the output of the functional block is output according to the connection table describing the correspondence between the output signal pin of the functional block selected by the mode specification value N and the pad for external output or the control pin of the output tristate control type IO. Since the pulse waveform forcibly input to the signal pin and the inspection waveform to be verified at the external output pad or the control pin of the output tristate control type IO can be obtained, it is not necessary to create a complicated test pattern or expected value pattern. Since the test pattern can be automatically generated from the connection table, it is possible to significantly reduce the number of test pattern creation steps.

A test pattern generator according to a sixth aspect of the present invention is an external input / output pad (external input / output pad 1
601) and an input AND control type bidirectional IO (input AN) in which bidirectional input / output pins are connected to the external input / output pads.
A D control type bidirectional IO 1602), a first multiplexer (multiplexer 1605) for selectively outputting an output from an output pin of the input AND control type bidirectional IO according to a mode designation value N input to a mode control pad, The first functional block (functional block 1613) for inputting the output of the first multiplexer, the second functional block (functional block 1614), and the input control pin of the input AND control type bidirectional IO are input to the input control pin. A second multiplexer (multiplexer 160) that selectively outputs the output signal of the second functional block according to the mode designation value N
6) and the third functional block (functional block 1612)
A third multiplexer (multiplexer 1604) for selectively outputting the output signal of the third functional block according to the mode designation value N as an input to an input pin of the input AND control type bidirectional IO, and a fourth function. A block (functional block 1611) and a fourth multiplexer (multiplexer 160) for selectively outputting the output signal of the fourth functional block according to the mode designating value N as an input to the output control pin of the input AND control type bidirectional IO.
3) and a semiconductor chip (semiconductor chip 160
0) in the test pattern generator for verifying the connection, the correspondence relationship between the output signal pin and the input signal pin of the functional block whose connection is selected by the mode designating value N with respect to the external input / output pad, A connection table (connection table 1700) describing the output control pins of the input AND control type bidirectional IO and the correspondence relationship between the output signal pins of the functional blocks whose connection is selected by the mode designation value N with respect to the input control pins. Accordingly, a pulse waveform (L) forcibly input with a time lag at the mode designation value N to each of the external input / output pad and the output signal pin of the functional block selected by the mode designation value N
Means for generating a pulse waveform 1821) and a level waveform (H level waveform 1819, L level waveform 1824, 1825), an input signal pin of a functional block selected by the mode designation value N, the input AND control type bidirectional IO Inspection waveforms (expected value waveforms 1812, 1813, and
1814, 1816, 1817, 1818, 1820,
1822, 1823) is generated.

According to the test pattern generator of the sixth aspect, even when the semiconductor chip includes the input AND control type bidirectional IO, it receives the input signal from the external input / output pad and its output is in the mode. Correspondence which is selected by the designated value N and is input to the input signal pin of the functional block, and both the external input / output pad or the input AND control type from the output signal pin of any functional block which is also selected by the mode designated value N. According to the connection table describing the correspondence to the output control pin or input control pin of the I / O module, the pulse waveform and level waveform forcibly input to the external input pad and the output signal pin of the functional block, and the input signal pin of the functional block and Since the test waveform to be verified at the output control pin and the input control pin of the input AND control type bidirectional IO can be obtained. It eliminates the need for the creation of complex test pattern and an expected value pattern, and because it is possible to perform automatic generation of test patterns from the connection table, it is possible to achieve a significant reduction of the test pattern generating steps.

A test pattern generator according to a seventh aspect of the present invention is an external input / output pad (external input / output pad 1
901), an input OR control type bidirectional IO (input OR control type bidirectional IO 1902) whose bidirectional input / output pins are connected to the external input / output pad, and a mode designation value N input to the mode control pad. A first multiplexer (multiplexer 1905) that selectively outputs the output from the output pin of the input OR control type bidirectional IO; and a first functional block (functional block 1913) that inputs the output of the first multiplexer. A second function block (function block 1914) and a second function block for selectively outputting an output signal of the second function block according to the mode designation value N as an input to an input control pin of the input OR control type bidirectional IO.
Multiplexer (multiplexer 1906) and a third
Function block (function block 1912) and a third multiplexer (multiplexer) that selectively outputs the output signal of the third function block according to the mode designation value N as an input to the input pin of the input OR control type bidirectional IO. 1904) and a fourth functional block (functional block 19
11) and a fourth multiplexer (multiplexer 1903) that selectively outputs the output signal of the fourth functional block according to the mode designation value N as an input to the output control pin of the input OR control type bidirectional IO. In a test pattern generation device for verifying connection to a semiconductor chip (semiconductor chip 1900) included therein, an output signal pin and an input signal of a functional block whose connection is selected by the mode designating value N with respect to the external input / output pad. A connection that describes a correspondence relationship between pins and a correspondence relationship between an output control pin of the input OR control type bidirectional IO and an output signal pin of a functional block whose connection is selected by the mode designation value N with respect to the input control pin. According to the table (connection table 2000), the external input / output pad and the mode designation value N
Pulse waveforms (H pulse waveforms 2111 and 211) forcibly input with a time lag at the mode designation value N to each of the output signal pins of the functional block selected by
5, 2121) and the level waveform (H level waveform 211
9, L level waveforms 2124, 2125), an input signal pin of a functional block selected by the mode designating value N, an output control pin and an input control pin of the input OR control type bidirectional IO, and the external device. Inspection waveforms (expected value waveforms 2112, 2113, 211) for verifying the matching of the signal waveforms at the respective input / output pads.
4, 2116, 2117, 2118, 2120, 212
2, 2123) is generated.

According to the test pattern generator of the present invention, even when the semiconductor chip includes the input OR control type bidirectional IO, it receives the input signal from the external input / output pad and the output thereof is in the mode. Correspondence between the input signal pin of the functional block selected by the designated value N and the output signal pin of any functional block similarly selected by the mode designated value N from the external input / output pad or the input OR control type According to the connection table describing the correspondence to the output control pin or input control pin of the I / O module, the pulse waveform and level waveform forcibly input to the external input pad and the output signal pin of the functional block, and the input signal pin of the functional block and Since the test waveform to be verified at the output control pin and the input control pin of the input OR control type bidirectional IO is obtained, it is complicated. It eliminates the need for creating a test pattern and an expected value pattern, and because it is possible to perform automatic generation of test patterns from the connection table, it is possible to achieve a significant reduction of the test pattern generating steps.

A test pattern generator according to an eighth aspect of the present invention is an external input / output pad (external input / output pad 2
201) and a normal bidirectional IO (normal bidirectional IO 220) whose bidirectional input / output pins are connected to the external input / output pads.
2) and the mode specification value N input to the mode control pad
The first multiplexer (multiplexer 220) that selectively outputs the output from the output pin of the normal bidirectional IO by
5), a first functional block (functional block 2213) for inputting the output of the first multiplexer, a second functional block (functional block 2212), and an input to an input pin of the normal bidirectional IO. Mode specified value N
A second multiplexer (multiplexer 2204) for selectively outputting the output signal of the second functional block by
And a third functional block (functional block 2211),
A semiconductor chip (semiconductor chip 2200) having a third multiplexer (multiplexer 2203) that selectively outputs the output signal of the third functional block according to the mode designation value N as an input to the output control pin of the normal bidirectional IO. In the test pattern generator for verifying the connection with respect to FIG. A connection table (connection table 2300) describing the correspondence relationship between the output signal pins of the functional blocks whose connection is selected by the mode designation value N for the output control pins of the normal bidirectional IO.
Accordingly, pulse waveforms (H pulse waveforms 2415, 24) forcibly input to the output signal pins of the functional block selected by the external input / output pad and the mode designating value N with a time difference at the mode designating value N, respectively.
21) and a level waveform (H level waveform 2419, L level waveform 2424, 2425), an input signal pin of a functional block selected by the mode designating value N, an output control pin of the normal bidirectional IO, and Inspection waveforms (expected value waveforms 2416, 241) for verifying the agreement of the signal waveforms on each of the external input / output pads.
7, 2418, 2420, 2422, 2423).

According to the test pattern generator of the present invention, even when the semiconductor chip normally includes bidirectional IO, it receives an input signal from the external input / output pad,
The output is selected by the mode designation value N and input to the input signal pin of the functional block, and the output signal pin of one of the functional blocks also selected by the mode designation value N is used as an external input / output pad or a normal output pad. According to the connection table that describes the correspondence with the output control pins of the bidirectional IO, the pulse waveform and level waveform forcibly input to the external input pad and the output signal pin of the functional block, the input signal pin of the functional block, and both Since a test waveform to be verified at the output control pin of the I / O device can be obtained, it is not necessary to create a complicated test pattern or expected value pattern, and the test pattern can be automatically generated from the connection table. It is possible to significantly reduce man-hours.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings. (Embodiment 1) FIG. 1 is a circuit diagram of a semiconductor chip which is a target of a test pattern generator according to Embodiment 1 of the present invention, and FIG. 2 describes a correspondence relationship of connection verification target pins in the circuit of FIG. Connection table, FIG. 3 is a signal waveform diagram of a test pattern generated by the test pattern generator according to the first embodiment of the present invention.

In FIG. 1, a semiconductor chip 100 includes functional blocks 101, 102, 103 and a functional block 1.
Outputs 01, 102 and 103 are used as mode control pads 10
Multiplexers 113 and 116 selected according to the mode values input from 7, 108 and 109, and external output pads 115 and 118 that output the output of the multiplexers to the outside.
And external input IOs 110, 111, 112 and external output IOs 114, 117.

Regarding the semiconductor chip configured as shown in FIG. 1, in FIG. 2, the horizontal axis indicates the mode control pad 10.
Mode value 201 set by 7, 108, and 109,
202 and 203 are described, and the external output pad 11 is on the vertical axis.
Connection table 2 in which external pad names 125 and 126 of 5 and 118 are described in external pad name description positions 204 and 205, respectively
Create 00.

For this connection table, mode values 201, 2
In each of 02 and 203, the functional block name 11 of the functional block 101, 102, 103 connected to the external output pad 115 represented by the external pad name 125
9, 120 and 121 are functional block name description positions 206,
Function block output pin 10 described in 207 and 208
4, 105, 106 functional block output pin names 122,
123 and 124 are functional block pin name description positions 209,
210 and 211.

Next, the mode values 201, 202, 203
In each, the functional block 10 connected to the external output pad 118 represented by the external pad name 126
2, 103, 101 functional block names 120, 121,
119 is a functional block name description position 212, 213, 21
4, the functional block output pin names 123, 124, 122 of the functional block output pins 105, 106, 104 are described in the functional block pin name description positions 215, 216, 217.

Next, referring to FIG. 3, the connection table 200 of FIG.
According to the connection information of, the functional block output pin 1 connected to the external output pad 115 in the section where the mode value 300 is 0
04, the H pulse waveform 306 is forcibly input, and the H pulse waveform 307 is forcibly input as the signal waveform 302 of the functional block output pin 105 connected to the external output pad 118. An expected value waveform 308 is generated for 115 and an expected value waveform 309 is generated for the external output pad 118.

Further, in the section where the mode value 300 is 1, an H pulse waveform 310 is output as the signal waveform 302 of the functional block output pin 105 connected to the external output pad 115.
The H pulse waveform 311 is forcibly input as the signal waveform 303 of the functional block output pin 106 connected to the external output pad 118, and the expected value waveform 312 for the external output pad 115 is output to the external output pad 115 as each expected value. An expected value waveform 313 is generated for the pad 118. The test pattern generating apparatus according to the present invention is configured by the above-mentioned means for generating the waveform.

In this way, the input waveform and the expected value waveform are generated for each mode, and when the mode value 300 is N, the H pulse is output as the signal waveform 303 of the functional block output pin 106 connected to the external output pad 115. Waveform 314
The H pulse waveform 315 is forcibly input as the signal waveform 301 of the functional block output pin 104 connected to the external output pad 118, and the expected value waveform 316 is output to the external output pad 115 as the expected value of each of them. The expected value waveform 317 is generated for the pad 118.

According to this embodiment, FIGS.
Comparing with the conventional example, it is not necessary to create a complicated input pattern for operating the function block or a complicated expected value pattern for each function block, and the waveform for designating the mode value 300 and the pulse waveforms 306, 307, 308, 309, 3
10, 311, 312, 313, 314, 315, 31
The connection verification pattern can be configured only by generating 6 and 317, and by automatically generating the pattern from the connection table, the number of man-hours required to create a pattern that increases due to an increase in the number of modes and the number of external pads can be reduced. It can be reduced significantly.

(Second Embodiment) FIG. 4 is a circuit diagram of a semiconductor chip which is a target of a test pattern generator according to a second embodiment of the present invention. FIG. 6 is a signal waveform diagram of a test pattern generated by the test pattern generating device according to the second embodiment of the present invention.

In FIG. 4, the semiconductor chip 400 has external input pads 413, 416 and mode control pads 407, 408, 409 for input from the external input pads.
Multiplexer 4 selected according to the mode value input from
15, 418, 427 and multiplexers 415, 41
Functional block 40 for inputting outputs of 8 and 427, respectively
1, 402, 403 and IO 410, 41 for external input
1, 412, 414, 417.

Regarding the semiconductor chip configured as shown in FIG. 4, in FIG. 5, the horizontal axis represents the mode control pad 40.
Mode value 501 set by 7, 408 and 409,
502 and 503 are described and the vertical input pad 41 is provided on the vertical axis.
Connection table 5 in which external pad names 425 and 426 of 3, 416 are described in external pad name description positions 504 and 505, respectively.
Create 00.

For this connection table, mode values 501, 5
02, 503, the functional block name 41 of the functional blocks 401, 402, 403 connected to the external input pad 413 represented by the external pad name 425.
9, 420, 421 are functional block name description positions 506,
507 and 508, the functional block input pin 40
4, 405, 406 functional block input pin name 422,
423 and 424 are functional block pin name description positions 509,
510 and 511.

Subsequently, mode values 501, 502, 503
In each, the functional block 40 connected to the external input pad 416 represented by the external pad name 426.
2, 403, 401 functional block names 420, 421,
419 is a functional block name description position 512, 513, 51
4, the functional block input pin names 423, 424, 422 of the functional block input pins 405, 406, 404 are described in the functional block pin name description positions 515, 516, 517.

Next, referring to FIG. 6, the connection table 500 of FIG.
In accordance with the connection information of, the H pulse waveform 608 and the pulse waveform 609 are input to the external input pad 413 and the external input pad 416 in the section where the mode value 600 is 0, and the expected value of each of them is input to the function block input pin 404. To generate an expected value waveform 606 and an expected value waveform 607 to the functional block input pin 405.

Further, in the section where the mode value 600 is 1, the H pulse waveform 612 is input to the external input pad 413 and the H pulse waveform 613 is input to the external input pad 416. The expected value waveform 610 for the functional block input pin 406
, An expected value waveform 611 is generated.

In this way, the input waveform and the expected value waveform are generated for each mode. In the section where the mode value 600 is N, the H pulse waveform 616 is applied to the external input pad 413 and the H pulse waveform is applied to the external input pad 416. The waveform 617 is input, and the expected value waveform 614 is input to the functional block input pin 406 and the expected value waveform 614 is input to the functional block input pin 405 as respective expected values.
, The expected value waveform 615 is generated. The test pattern generating apparatus according to the present invention is configured by the above-mentioned means for generating the waveform.

According to this embodiment, FIGS.
In comparison with the conventional example, it is not necessary to create a complicated input pattern for operating a functional block or a complicated expected value pattern for each functional block, and a waveform for designating a mode value 600 and a pulse waveform 606.607, 608, 609, 6
10, 611, 612, 613, 614, 615, 61
The connection verification pattern can be configured only by generating 6 and 617, and by automatically generating the pattern from the connection table, the number of man-hours required to create a pattern that increases with the increase in the number of modes and the number of external pads can be reduced. It can be reduced significantly.

(Third Embodiment) FIG. 7 is a circuit diagram of a semiconductor chip which is a target of a test pattern generator according to a third embodiment of the present invention. FIG. 9 is a signal waveform diagram of a test pattern generated by the test pattern generator according to the third embodiment of the present invention.

In FIG. 7, the semiconductor chip 700 includes an external input pad 701, an input AND control type IO 702 for receiving an input from the external input pad 701, and a mode value input from the mode control pads 704, 705 and 706. A multiplexer 703 that selects the output of the input AND control type IO 702 by N, a functional block 710 that receives the output of the multiplexer 703, and a functional block 71.
1, a multiplexer 714 that selects the output of the functional block 711 according to the mode value N, and an external input IO7
07, 708, 709, the output of the multiplexer 714 is connected to the control pin 715 of the input AND control type IO 702.

With respect to the semiconductor chip configured as shown in FIG. 7, in FIG. 8, the horizontal axis represents the mode control pad 70.
4, 705 and 706 are described, the external pad name 721 of the external input pad 701 is described in the external pad name description position 802 on the vertical axis, and the input AND control is performed on the second vertical axis. Type IO output pin 716
The IO pin name 722 of the input AND control type IO control pin 715 is input to the IO pin name description position 803.
3 is created in the IO pin name description position 804, and the connection table 800 is created.

With respect to this connection table, in the mode value N, the function block name 717 of the function block 710 connected to the output pin 716 of the input AND control type IO 702 is placed in the function block name description position 805 and the function block 710.
Of the functional block input pin name 719 to the functional block pin name description position 807, the functional block name 718 of the functional block 711 connected to the control pin 715 of the input AND control type IO 702 to the functional block name description position 806, and the functional block 711. The functional block output pin name 720 of the above is described in the functional block pin name description position 808, respectively.

Next, referring to FIG. 9, the connection table 800 of FIG.
According to the information of the
The L pulse waveform 905 is forcibly input to the function block output pin 713 connected to the control pin 715 of the D control type IO 702, and the expected value waveform 906 is generated for the control pin 715 of the input AND control type IO 702. Subsequently, with a time difference, the H pulse waveform 907 is input to the external pad 701, and the expected value waveform 908 is generated for the functional block input pin 712 connected to the output pin 716 of the input AND control type IO 702. The test pattern generating apparatus according to the present invention is configured by the above-mentioned means for generating the waveform.

According to this embodiment, even when the semiconductor chip includes the input AND control type IO, a complicated input pattern for operating the plurality of functional blocks and a complicated expected value pattern for each of the plurality of functional blocks are created. There is no need, the connection verification pattern can be configured only by generating a simplified pulse waveform, and the number of modes and the number of external pads can be increased by automatically generating the pattern from the connection table. The number of man-hours required for pattern formation can be significantly reduced.

(Fourth Embodiment) FIG. 10 is a circuit diagram of a semiconductor chip which is a target of a test pattern generator according to a fourth embodiment of the present invention, and FIG. 11 is a correspondence relation of connection verification target pins in the circuit of FIG. 12 is a signal waveform diagram of a test pattern generated by the test pattern generator according to the fourth embodiment of the present invention.

In FIG. 10, a semiconductor chip 1000 is shown.
Is an external input pad 1001 and an external input pad 1
Input OR control type IO1002 that receives input from 001
And mode control pads 1004, 1005, 1006
Input OR control type IO10 according to the mode value N input from
Multiplexer 1003 for selecting the output of 02, and functional block 101 for receiving the output of multiplexer 1003
0, the functional block 1011 and the functional block 1011
1014 for selecting the output of the above according to the mode value N, and external input IOs 1007, 1008, 10
09, and the output of the multiplexer 1014 is connected to the control pin 1015 of the input OR control type IO1002.

Regarding the semiconductor chip configured as shown in FIG. 10, in FIG. 11, the horizontal axis indicates the mode control pad 1
The mode value 1101 set by 004, 1005, and 1006 is described, and the external pad name 1021 of the external input pad 1001 is plotted on the vertical axis as the external pad name description position 1102.
In the second vertical axis, the IO pin name 1022 of the output pin 1016 of the input OR control type IO is set in the IO pin name description position 1103, and the control pin 10 of the input OR control type IO is described.
15 IO pin names 1023 are IO pin name description positions 110
4, the connection table 1100 described above is created.

For this connection table, in the mode value N, the function block name 10 of the function block 1010 connected to the output pin 1016 of the input OR control type IO1002
17 in the function block name description position 1105, the function block input pin name 1019 of the function block 1010 in the function block pin name description position 1107, and the input OR control type IO.
The function block name 1018 of the function block 1011 connected to the control pin 1015 of 1002 is set to the function block name description position 1106, and the function block output pin name 1020 of the function block 1011 is set to the function block pin name description position 1
108, respectively.

Next, referring to FIG. 12, the connection table 1 of FIG.
According to the information of 100, in the section where the mode value 1200 is N,
The H pulse waveform 1 is output to the functional block output pin 1013 connected to the control pin 1015 of the input OR control type IO1002.
205 is compulsorily input to generate an expected value waveform 1206 to the control pin 1015 of the input OR control type IO1002. Continue to set a time lag and set H on the external pad 1001.
Input the pulse waveform 1207 and input OR control type IO10
The expected value waveform 1208 is generated for the function block input pin 1012 connected to the output pin 1016 of 02. The test pattern generating apparatus according to the present invention is configured by the above-mentioned means for generating the waveform.

According to this embodiment, even when the semiconductor chip includes the input OR control type IO, a complicated input pattern for operating the plurality of functional blocks and a complicated expected value pattern for each of the plurality of functional blocks are created. There is no need, the connection verification pattern can be configured only by generating a simplified pulse waveform, and the number of modes and the number of external pads can be increased by automatically generating the pattern from the connection table. The number of man-hours required for pattern formation can be significantly reduced.

(Fifth Embodiment) FIG. 13 is a circuit diagram of a semiconductor chip which is a target of a test pattern generator according to a fifth embodiment of the present invention, and FIG. 14 is a correspondence relation of connection verification target pins in the circuit of FIG. FIG. 15 is a signal waveform diagram of a test pattern generated by the test pattern generator according to the fifth embodiment of the present invention.

In FIG. 13, a semiconductor chip 1300
Is a functional block 1310 and outputs the output of the functional block 1310 to mode control pads 1304, 1305, 130.
6, a multiplexer 1303 selected by a mode value N input from 6, an output tristate control type IO 1302 inputting the output of the multiplexer 1303, and an external output pad 1301 outputting the output of the output tristate control IO 1302 to the outside. Block 1311
And the output of the function block output 1311 is the mode value N
It is composed of a multiplexer 1314 that is selected by and an external input IO 1307, 1308, 1309. The output of the multiplexer 1314 is connected to the control pin 1315 of the output tristate control type IO 1302.

Regarding the semiconductor chip configured as shown in FIG. 13, in FIG. 14, the horizontal axis indicates the mode control pad 1
The mode value 1401 set by 304, 1305, and 1306 is described, and the vertical pad indicates the external pad name 1321 of the external output pad 1301 on the external pad name description position 1402.
And the second vertical axis indicates the IO pin name 13 of the input pin 1316 of the output tristate control type IO 1302.
22 to the IO pin name description position 1403, and the IO pin name 1323 of the control pin 1315 of the output tristate control type IO 1302 to the IO pin name description position 1404 to create a connection table 1400.

With respect to this connection table, in the mode value N, the function block name 1317 of the function block 1310 connected to the input pin 1316 of the output tristate control type IO1302 is set to the function block name description position 1405.
Function block output pin name 131 of function block 1310
9 in the functional block pin name description position 1407 and the functional block name 131 of the functional block 1311 connected to the control pin 1315 of the output tristate control type IO 1302.
8 in the functional block name description position 1406, and the functional block output pin name 1320 of the functional block 1311 in the functional block pin name description position 1408.

Next, referring to FIG. 15, the connection table 1 of FIG.
According to the information of 400, in the section where the mode value 1500 is N,
Control pin 13 of output tristate control type IO1302
The L pulse waveform 1505 is forcibly input to the output pin 1313 of the functional block connected to 15, and the expected value waveform 1506 is output to the control pin 1315 of the output tristate control type IO 1302 and the high impedance expected value is output to the external output pad 1301. Waveform 1509 is generated. After that, set a time difference and set H to the function block output pin 1312.
Forced input of pulse waveform 1507, pad 1 for external output
An expected value waveform 1508 is generated for 301. The test pattern generating apparatus according to the present invention is configured by the above-mentioned means for generating the waveform.

According to this embodiment, even when the semiconductor chip includes the output tristate control type IO, a complicated input pattern for operating a plurality of functional blocks and a complicated expected value pattern for each of a plurality of functional blocks can be created. There is no need to perform it, the connection verification pattern can be configured only by generating a simplified pulse waveform, and by automatically generating the pattern from the connection table, the number of modes and the number of external pads can be reduced. The number of man-hours required for pattern formation, which increases due to the increase, can be significantly reduced.

(Sixth Embodiment) FIG. 16 is a circuit diagram of a semiconductor chip targeted by a test pattern generator according to a sixth embodiment of the present invention. FIG. 18 is a signal waveform diagram of a test pattern generated by the test pattern generator according to the sixth embodiment of the present invention.

In FIG. 16, a semiconductor chip 1600
Is an external input / output pad 1601 and an input AND in which the external input / output pad 1601 and the bidirectional input / output pin are connected.
Control type bidirectional IO 1602 and mode control pad 16
According to the mode value N input from 15, 1616, 1617, the output pin 16 of the input AND-controlled bidirectional IO 1602
A multiplexer 1605 that selects the output from 21;
A function block 1613 that receives the output of the multiplexer 1605, a function block 1614, a multiplexer 1606 that selects the output of the function block 1614 by the mode value N, a function block 1612, and the output of the function block 1612 that is the mode value N. A multiplexer 1604 selected by, a functional block 1611,
A multiplexer 1603 that selects the output of the functional block 1611 according to the mode value N, and an external input IO 16
18, 1619, 1620, and the output of the multiplexer 1606 is an input AND control type bidirectional IO16.
02 input control pin 1624 to multiplexer 160
The output of 4 is to the input pin 1622 of the input AND control type bidirectional IO 1602, and the output of the multiplexer 1603 is the output control pin 162 of the input AND control type bidirectional IO 1602.
3 are connected respectively.

Further, in FIG. 16, the output tristate inversion control type buffer 1637 is connected to the outside of the semiconductor chip 1600 as a verification external driver.
The output of the output tristate inversion control buffer 1637 is connected to the external input / output pad 1601 and the output control pin 1 of the output tristate inversion control buffer 1637 is connected.
639 is connected to the output control pin 1623 of the input AND control type bidirectional IO 1602.

Regarding the semiconductor chip configured as shown in FIG. 16, in FIG. 17, the horizontal axis represents the mode control pad 1
The mode value 1701 set by 615, 1616, and 1617 is described, and the vertical input / output pad 1601 is shown on the vertical axis.
External pad name 1636 of external pad name description position 170
2 and the second vertical axis indicates the input pin name 16 of the input pin 1622 of the input AND control type bidirectional IO 1602.
33 to the IO pin name description position 1703, the output pin name 1634 of the output pin 1621 of the input AND control type bidirectional IO 1602 to the IO pin name description position 1704, and the input AND
The output control pin name 1632 of the output control pin 1623 of the control type bidirectional IO 1602 is set to the IO pin name description position 1705.
Then, the connection table 1700 in which the input control pin name 1635 of the input control pin 1624 of the input AND control type bidirectional IO 1602 is described in the IO pin name description position 1706 is created.

For this connection table, at mode value N, input pin 1 of input AND control type bidirectional IO 1602
The function block name 1626 of the function block 1612 connected to 622 is set to the function block name description position 1707, the function block output pin name 1640 of the function block output pin 1608 is set to the function block pin name description position 1711, and the input AND control type bidirectional Output pin 1621 of IO1602
Function block name 1 of the function block 1613 connected to
627 in the functional block name description position 1708, and the functional block input pin name 163 of the functional block input pin 1609.
Input 0 to the function block pin name description position 1712
Function block name 16 of the function block 1611 connected to the output control pin 1623 of the D control type bidirectional IO 1602
25 in the functional block name description position 1709, and the functional block output pin name 1629 of the functional block output pin 1607.
To the functional block pin name description position 1713 and input AND
Function block name 162 of function block 1614 connected to input control pin 1624 of control type bidirectional IO 1602
8 is described in the functional block name description position 1710, and the functional block output pin name 1631 of the functional block output pin 1610 is described in the functional block pin name description position 1714.

Next, referring to FIG. 18, the connection table 1 of FIG.
According to the information of 700, in the section where the mode value 1800 is N,
Output control pin 1 of input AND control type bidirectional IO 1602
623 to the functional block output pin 1607 connected to 623
The level waveform 1824 is forcibly input to set the input AND control type bidirectional IO 1602 to the input mode, and the L pulse waveform 181 is output to the functional block output pin 1610 connected to the input control pin 1624 of the input AND control type bidirectional IO 1602.
1 is forcibly input, and the expected value waveform 1813 is input to the input control pin 1624 of the input AND control type bidirectional IO and input A
The expected value waveform 1814 is input to the output pin 1621 of the ND control type bidirectional IO 1602 and input AND control type bidirectional I
The expected value waveform 1812 is generated for the function block input pin 1609 connected to the output pin 1621 of the O1602.

Continuing to provide a time difference, the L pulse waveform 1815 is input to the input 1638 of the verification driver 1637 and the expected value waveform 18 is input to the external input / output pad 1601.
18 and the expected value waveform 1817 to the output pin 1621 of the input AND control type bidirectional IO 1602
An expected value waveform 1816 is generated for each of the functional block input pins 1609 connected to the output pin 1621 of the control type bidirectional IO 1602.

Next, the input AND control type bidirectional IO 160.
H-level waveform 1819 is forcibly input to the functional block output pin 1607 connected to the second output control pin 1623,
Input AND control type bidirectional IO 1602 with a time difference
The L pulse waveform 1821 is forcibly input to the functional block output pin 1608 connected to the input pin 1622 of
An expected value 1822 is generated for the input pin 1622 of the ND control type bidirectional IO 1602, and an expected value waveform 1823 is generated for the external input / output pad 1601.

Finally, the input AND control type bidirectional IO16
The L level waveform 1825 is forcibly input to the functional block output pin 1607 connected to the output control pin 1623 of No. 02, and the expected value waveform 1820 is generated for the output control pin 1623 of the input AND control type bidirectional IO 1602.
The test pattern generating apparatus according to the present invention is configured by the above-mentioned means for generating the waveform.

According to this embodiment, even when the semiconductor chip includes the input AND control type bidirectional IO, a complicated input pattern for operating a plurality of functional blocks and a complicated expected value pattern for each plurality of functional blocks are created. The connection verification pattern can be configured only by generating a simplified pulse waveform, and the number of modes and the number of external pads can be automatically generated from the connection table. The number of man-hours required to create a pattern can be significantly reduced by increasing

(Embodiment 7) FIG. 19 is a circuit diagram of a semiconductor chip which is a target of a test pattern generator according to Embodiment 7 of the present invention. FIG. 21 is a signal waveform diagram of a test pattern generated by the test pattern generator according to the seventh embodiment of the present invention.

In FIG. 19, a semiconductor chip 1900
Is an external input / output pad 1901, an input OR control type bidirectional IO 1902 in which the external input / output pad 1901 and bidirectional input / output pins are connected, and a mode control pad 191.
The output pin 1921 of the input OR control type bidirectional IO 1902 depending on the mode value N input from 5, 1916 and 1917.
1905 for selecting the output from the multiplexer 1 and the functional block 1 having the output of the multiplexer 1905 as the input
913, a function block 1914, and a function block 19
A multiplexer 1906 that selects the output of 14 according to the mode value N, a function block 1912, a multiplexer 1904 that selects the output of the function block 1912 according to the mode value N, a function block 1911, and the output of the function block 1911. Multiplexer 1903 selected by value N and IO 191 for external input
8, 1919, 1920, and the output of the multiplexer 1906 is an input OR control type bidirectional IO 1902.
To the input control pin 1924 of the input 1 of the input OR control type bidirectional IO 1902.
The output of the multiplexer 1903 is connected to the output control pin 1923 of the input OR control type bidirectional IO 1902.

Further, in FIG. 19, the output tristate inversion control type buffer 1937 is connected to the outside of the semiconductor chip 1900 as a verification external driver.
The output of the output tristate inversion control buffer 1937 is connected to the external input / output pad 1901, and the output control pin 1 of the output tristate inversion control buffer 1937 is connected.
Reference numeral 939 is connected to the output control pin 1923 of the input OR control type bidirectional IO 1902.

Regarding the semiconductor chip configured as shown in FIG. 19, in FIG. 20, the horizontal axis represents the mode control pad 1
The mode value 2001 set by 915, 1916, and 1917 is described, and the vertical axis represents the external input / output pad 1901.
The external pad name 1936 of the external pad name description position 200
2 and the second vertical axis indicates the input pin name 193 of the input pin 1922 of the input OR control type bidirectional IO 1902.
3 in the IO pin name description position 2003, and the output pin name 19 of the output pin 1921 of the input OR control type bidirectional IO 1902.
34 to the IO pin name description position 2004, the output control pin name 1932 of the output control pin 1923 of the input OR control type bidirectional IO 1902 to the IO pin name description position 2005, and the input control pin 1924 of the input OR control type bidirectional IO 1902.
Input control pin name 1935 of IO pin name description position 200
The connection table 2000 described in 6 is created.

With respect to this connection table, at the mode value N, the input pin 19 of the input OR control type bidirectional IO 1902.
22 to the functional block name 1926 of the functional block 1912 connected to the functional block 1912 in the functional block name description position 2007 and the functional block output pin name 1 of the functional block output pin 1908.
940 in the function block output pin name position 2011, and the function block name 192 of the function block 1913 connected to the output pin 1921 of the input OR control type bidirectional IO 1902.
7 to the functional block name description position 2008, the functional block input pin name 1930 of the functional block input pin 1909 to the functional block pin name description position 2012, and the functional block connected to the output control pin 1923 of the input OR control type bidirectional IO 1902. The function block name 1925 of 1911 is set to the function block name description position 2009, the function block output pin name 1929 of the function block output pin 1907 is set to the function block pin name description position 2013, and the input control pin 1924 of the input OR control type bidirectional IO 1902 is set. The functional block name 1928 of the connected functional block 1914 is described in the functional block name description position 2010, and the functional block output pin name 1931 of the functional block output pin 1910 is described in the functional block pin name description position 2014.

Next, referring to FIG. 21, the connection table 2 of FIG.
According to the information of 000, in the section where the mode value 2100 is N,
Output control pin 19 of input OR control type bidirectional IO 1902
A functional block connected to the input control pin 1924 of the input OR control type bidirectional IO 1902 by forcibly inputting the L level waveform 2124 to the output pin 1907 connected to the input OR control type bidirectional IO 1902. The H pulse waveform 2111 is forcibly input to the output pin 1910, and the input control pin 1 of the input OR control type bidirectional IO
A functional block output pin 1 connected to the expected value waveform 2113 for 924, the expected value waveform 2114 for the output pin 1921 of the input OR control type bidirectional IO 1902, and the output pin 1921 of the input OR control type bidirectional IO 1902.
The expected value waveform 2112 is generated for 909.

Subsequently, with a time difference, the H pulse waveform 2115 is input to the input 1938 of the verification driver 1937, and the expected value waveform 21 is input to the external input / output pad 1901.
18 is the expected value waveform 2117 for the output pin 1921 of the input OR control type bidirectional IO 1902, and the expected value waveform 21 is for the functional block input pin 1909 connected to the output pin 1921 of the input OR control type bidirectional IO 1902.
16 are generated respectively.

Next, the input OR control type bidirectional IO 1902
H level waveform 2119 is forcibly input to the function block output pin 1907 connected to the output control pin 1923 of
Functional block output pin 1 connected to input pin 1922 of input OR control type bidirectional IO 1902 with a time difference
Forcibly input the H pulse waveform 2121 to 908, and input OR
An expected value 2122 is generated for the input pin 1922 of the control type bidirectional IO 1902, and an expected value waveform 2123 is generated for the external input / output pad 1901.

Finally, the input OR control type bidirectional IO 190
2 forcibly inputs the L level waveform 2125 to the functional block output pin 1907 connected to the output control pin 1923.
Output control pin 19 of input OR control type bidirectional IO 1902
An expected value waveform 2120 is generated for 23. The test pattern generating apparatus according to the present invention is configured by the above-mentioned means for generating the waveform.

According to this embodiment, even when the semiconductor chip includes the input OR control type bidirectional IO, a complicated input pattern for operating a plurality of functional blocks and a complicated expected value pattern for each plurality of functional blocks are created. The connection verification pattern can be configured only by generating a simplified pulse waveform, and the number of modes and the number of external pads can be automatically generated from the connection table. The number of man-hours required to create a pattern can be significantly reduced by increasing the number of times.

(Embodiment 8) FIG. 22 is a circuit diagram of a semiconductor chip targeted by a test pattern generator according to Embodiment 8 of the present invention, and FIG. 23 is a correspondence relation of connection verification target pins in the circuit of FIG. 24 is a signal waveform diagram of a test pattern generated by the test pattern generating apparatus according to the eighth embodiment of the present invention.

In FIG. 22, the semiconductor chip 2200
Is an external input / output pad 2201, a normal bidirectional IO 2202 in which bidirectional input / output pins are connected to the external input / output pad 2201, and mode control pads 2215, 221.
6 and 2217, the multiplexer 2205 that selects the output from the output pin 2221 of the normal bidirectional IO 2202, the functional block 2213 that receives the output of the multiplexer 2205, the functional block 2212, and the functional block 2212. A multiplexer 2204 for selecting an output according to the mode value N, a function block 2211, and a multiplexer 2203 for selecting an output of the function block 2211 according to the mode value N.
And an external input IO 2218, 2219, 2220. The output of the multiplexer 2204 is connected to the input pin 2222 of the normal bidirectional IO 2202, and the output of the multiplexer 2203 is connected to the output control pin 2223 of the normal bidirectional IO 2202. There is.

Further, in FIG. 22, the output tri-state inversion control type buffer 2237 is connected to the outside of the semiconductor chip 2200 as a verification external driver.
The output of the output tristate inversion control type buffer 2237 is connected to the external input / output pad 2201 and the output control pin 2 of the output tristate inversion control type buffer 2237 is connected.
239 is the output control pin 222 of the normal bidirectional IO 2202
It is connected with 3.

Regarding the semiconductor chip configured as shown in FIG. 22, in FIG. 23, the horizontal axis indicates the mode control pad 2
The mode value 2301 set by 215, 2216, and 2217 is described, and the vertical axis represents the external input / output pad 2201.
External pad name 2236 of external pad name description position 230
2, and the second vertical axis indicates normal bidirectional IO 22.
The input pin name 2233 of the input pin 2222 of 02 is the IO pin name description position 2303, the output pin name 2234 of the output pin 2221 of the normal bidirectional IO 2202 is the IO pin name description position 2304, and the output control pin 2223 of the normal bidirectional IO 2202 is A connection table 2300 in which the output control pin name 2232 of each item is described in the IO pin name description position 2305 is created.

With respect to this connection table, in the mode value N, the function block name 2226 of the function block 2212 which is normally connected to the input pin 2222 of the bidirectional IO 2202.
To the functional block name description position 2307, the functional block output pin name 2240 of the functional block output pin 2208 to the functional block pin name description position 2311, and the normal bidirectional IO
The function block name 2227 of the function block 2213 connected to the output pin 2221 of the 2202 is set to the function block name description position 2308, and the function block input pin name 2230 of the function block input pin 2209 is set to the function block pin name description position 2312. The function block name 2225 of the function block 2211 connected to the output control pin 2223 of the destination IO 2202 is set as the function block name description position 2309.
In addition, the function block output pin name 2229 of the function block output pin 2207 is set to the function block pin name description position 2313.
, Respectively.

Next, referring to FIG. 24, the connection table 2 of FIG.
According to the information of 300, in the section where the mode value 2400 is N,
Normally, the L level waveform 2 is output to the functional block output pin 2207 which is connected to the output control pin 2223 of the bidirectional IO 2202.
Forcibly input 424 to set the normal bidirectional IO 2202 to the input mode, provide a time difference, input the H pulse waveform 2415 to the input 2238 of the verification driver 2237, and input the expected value waveform 2418 to the external input / output pad 2201. An expected value waveform 2417 is generated for the output pin 2221 of the normal bidirectional IO 2202, and an expected value waveform 2416 is generated for the functional block input pin 2209 connected to the output pin 2221 of the normal bidirectional IO 2202.

Next, the functional block output pin 220 which is normally connected to the output control pin 2223 of the bidirectional IO 2202.
7 is forcibly input with the H level waveform 2419, a time difference is provided, and the H pulse waveform 2 is output to the functional block output pin 2208 that is normally connected to the input pin 2222 of the bidirectional IO 2202.
421 is forcibly input to generate an expected value 2422 for the input pin 2222 of the normal bidirectional IO 2202 and an expected value waveform 2423 for the external input / output pad 2201.

Finally, the functional block output pin 22 normally connected to the output control pin 2223 of the bidirectional IO 2202.
The L level waveform 2425 is forcibly input to 07, and the expected value waveform 2420 is normally generated for the output control pin 2223 of the bidirectional IO 2202. The test pattern generating apparatus according to the present invention is configured by the above-mentioned means for generating the waveform.

According to this embodiment, it is necessary to create a complicated input pattern for operating a plurality of functional blocks and a complicated expected value pattern for each of a plurality of functional blocks even when the semiconductor chip normally includes bidirectional IO. Connection verification pattern can be configured only by the generation of a simplified pulse waveform, and by automatically generating the pattern from the connection table, the number of modes and the number of external pads can be increased. The number of man-hours required to create patterns can be significantly reduced.

[0091]

As described above, according to the present invention,
Set the mode value from the mode input pad, and in the verification of the input side, input only the pulse signal from the external input pad, confirm that the pulse signal has reached the functional block input terminal, and check the output side. In the verification, by forcibly inputting only the pulse signal to the functional block output terminal and confirming whether the pulse signal forcibly input to the external output pad has arrived, by performing the wiring connection verification inside the semiconductor chip, The creation of complicated test patterns can be omitted. In addition, by describing the mode value, input side connection information, and output side connection information in the connection table and automatically generating a test pattern from this connection table, a test pattern that increases according to an increase in the number of pads and the number of modes. The number of production steps can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor chip targeted by a test pattern generator according to a first embodiment of the present invention.

FIG. 2 is a connection table describing a correspondence relationship of connection verification target pins in the circuit of FIG.

FIG. 3 is a signal waveform diagram of a test pattern generated by the test pattern generator according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram of a semiconductor chip targeted by a test pattern generator according to a second embodiment of the present invention.

5 is a connection table describing a correspondence relationship of connection verification target pins in the circuit of FIG. 4;

FIG. 6 is a signal waveform diagram of a test pattern generated by the test pattern generator according to the second embodiment of the present invention.

FIG. 7 is a circuit diagram of a semiconductor chip targeted by a test pattern generation device according to a third embodiment of the present invention.

8 is a connection table describing a correspondence relationship of connection verification target pins in the circuit of FIG.

FIG. 9 is a signal waveform diagram of a test pattern generated by the test pattern generator according to the third embodiment of the present invention.

FIG. 10 is a circuit diagram of a semiconductor chip targeted by a test pattern generation device according to a fourth embodiment of the present invention.

11 is a connection table describing a correspondence relationship of connection verification target pins in the circuit of FIG.

FIG. 12 is a signal waveform diagram of a test pattern generated by the test pattern generator according to the fourth embodiment of the present invention.

FIG. 13 is a circuit diagram of a semiconductor chip targeted by a test pattern generation device according to a fifth embodiment of the present invention.

FIG. 14 is a connection table describing a correspondence relationship of connection verification target pins in the circuit of FIG.

FIG. 15 is a signal waveform diagram of a test pattern generated by the test pattern generator according to the fifth embodiment of the present invention.

FIG. 16 is a circuit diagram of a semiconductor chip targeted by a test pattern generation device according to a sixth embodiment of the present invention.

FIG. 17 is a connection table describing a correspondence relationship between connection verification target pins in the circuit of FIG. 16;

FIG. 18 is a signal waveform diagram of a test pattern generated by the test pattern generator according to the sixth embodiment of the present invention.

FIG. 19 is a circuit diagram of a semiconductor chip targeted by a test pattern generation device according to a seventh embodiment of the present invention.

20 is a connection table describing a correspondence relationship of connection verification target pins in the circuit of FIG. 19;

FIG. 21 is a signal waveform diagram of a test pattern generated by the test pattern generator according to the seventh embodiment of the present invention.

FIG. 22 is a circuit diagram of a semiconductor chip targeted by a test pattern generator according to an eighth embodiment of the present invention.

23 is a connection table describing the correspondence relationship of connection verification target pins for the circuit of FIG. 22. FIG.

FIG. 24 is a signal waveform diagram of a test pattern generated by the test pattern generator according to the eighth embodiment of the present invention.

FIG. 25 is a circuit diagram example of a semiconductor chip which is a target of wiring connection verification by a conventional method.

FIG. 26 is a diagram showing input patterns and output patterns for verifying the circuit of FIG. 25.

[Explanation of symbols]

100 semiconductor chips 101, 102, 103 functional blocks 104, 105, 106 functional block output pins 107, 108, 109 mode control pads 110, 111, 112 external input IO 113, 116 multiplexer 114, 117 external output IO 115, 118 external output pads 119, 120, 121 functional block names 122, 123, 124 functional block output pin names 125, 126 external pad names 200 connection tables 201, 202, 203 mode values 204, 205 external pad name description positions 206, 207 , 208, 212, 213, 214 Function block name description position 209, 210, 211, 215, 216, 217 Function block pin name description position 300 Mode value input waveform 301, 302, 303 Forced input to function block output pin Expected waveform at the pad waveform 304, 305 external output 306,307,310,311,314,315 H
Pulse waveforms 308, 309, 312, 313, 316, 317 Expected value waveform 400 Semiconductor chips 401, 402, 403 Functional blocks 404, 405, 406 Functional block input pins 407, 408, 409 Mode control pads 410, 411, 412, 414, 417 External input IO 413, 416 External input pad 415, 418, 427 Multiplexer 419, 420, 421 Functional block name 422, 423, 424 Functional block input pin name 425, 426 External pad name 500 Connection table 501, 502 , 503 Mode value 504, 505 External pad name description position 506, 507, 508, 512, 513, 514 Function block name description position 509, 510, 511, 515, 516, 517 Function block pin name description position 600 Mode value Force waveforms 601, 602 Input waveforms 603, 604, 605 of external input pads Expected value waveforms 606, 607, 610, 611, 614, 615 at functional block input pins Expected value waveforms 608, 609, 612, 613, 616, 617 H
Pulse waveform 700 Semiconductor chip 701 External input pad 702 Input AND control type IO 703, 714 Multiplexer 704, 705, 706 Mode control pad 707, 708, 709 External input IO 710, 711 Function block 712 Function block input pin 713 Function Block output pin 715 Input AND control type IO control pin 716 Input AND control type IO output pin 717, 718 Function block name 719 Function block input pin name 720 Function block output pin name 721 External pad name 722 Input AND control type IO Output pin name 723 Input AND control type IO control pin name 800 Connection table 801 Mode value 802 External pad name description position 803, 804 IO pin name description position 805, 806 Function block name description position 807, 808 Function block Check pin name Description position 900 Mode value input waveform 901 Forced input waveform to functional block output pin 902 Input waveform of external input pad 903 Expected value waveform at functional block input pin 904 Expected value waveform at control pin of input AND control type IO 905 L pulse waveform 906, 908 Expected value waveform 907 H pulse waveform 1000 Semiconductor chip 1001 External input pad 1002 Input OR control type IO 1003, 1014
Multiplexers 1004, 1005, 1006 Mode control pads 1007, 1008, 1009 External input IO 1010, 1011 Function block 1012 Function block input pin 1013 Function block output pin 1015 Input OR control type IO control pin 1016 Input OR control type IO Output pins 1017, 1018 Function block name 1019 Function block input pin name 1020 Function block output pin name 1021 External pad name 1022 Output pin name 1023 of input OR control type IO Control pin name 1100 of input OR control type IO Connection table 1101 Mode value 1102 External pad name description position 1103, 1104 IO pin name description position 1105, 1106 Functional block name description position 1107, 1108 Functional block pin name description position 1200 Mode value input waveform 1 01 Forced input waveform 120 to the functional block output pin Input waveform 1203 of the pad for external input 1203 Expected value waveform 1204 at the functional block input pin Expected value waveform 1205 at the control pin of the input OR control type IO 1207 H pulse waveform 1206, 1208 Expected Value waveform 1300 Semiconductor chip 1301 External output pad 1302 Output tristate control type IO 1303, 1314 Multiplexer 1304, 1305, 1306 Mode control pad 1307, 1308, 1309 External input IO 1310, 1311 Functional block 1312, 1313 Functional block output Pin 1315 Output tristate control IO control pin 1316 Output tristate control IO input pin 1317, 1318 Function block name 1319, 1320 Function block Output pin name 1321 External pad name 1322 Output tristate control IO input pin name 1323 Output tristate control IO control pin name 1400 Connection table 1401 Mode value 1402 External pad name description position 1403, 1404 IO pin name description position 1405, 1406 Function block name description position 1407, 1408 Function block pin name description position 1500 Mode value input waveform 1501, 1502 Forced input waveform to function block output pin 1503 Expected value waveform at external output pad 1504 Output 3-state control type IO Expected value waveform 1505 L pulse waveforms 1506, 1508, 1509 Expected value waveform 1507 H pulse waveform 1600 Semiconductor chip 1601 External input / output pad 1602 Input AND control type bidirectional IO 16 3, 1604, 1605, 1606 Multiplexer 1607, 1608, 1610 Function block output pin 1609 Function block input pin 1611, 1612, 1613, 1614 Function block 1615, 1616, 1617 Mode control pad 1618, 1619, 1620 External input IO 1621 Input AND control type bidirectional IO output pin 1622 Input AND control type bidirectional IO input pin 1623 Input AND control type bidirectional IO output control pin 1624 Input AND control type bidirectional IO input control pin 1625, 1626, 1627 , 1628 Function block name 1629, 1631, 1640 Function block output pin name 1630 Function block input pin name 1632 Input AND control type bidirectional IO output control pin name 1633 Input AND control type both IO input pin name 1634 Input AND control type bidirectional IO output pin name 1635 Input AND control type bidirectional IO input control pin name 1636 External pad name 1637 Verification driver 1638 Verification driver input 1639 Verification driver output Control pin 1700 Connection table 1701 Mode value 1702 External pad name description position 1703, 1704, 1705, 1706 IO pin name description position 1707, 1708, 1709, 1710 Functional block name description position 1711, 1712, 1713, 1714 Functional block pin name description Position 1800 Mode value input waveforms 1801, 1802, 1804 Forced input waveforms to function block output pins 1803 Expected value waveforms at function block input pins 1805 Verification driver input waveform 1806 Input AND control type bidirectional IO Expected value waveform at input control pin 1807 Expected value waveform at output pin of input AND control type bidirectional IO 1808 Expected value waveform at output control pin of input AND control type bidirectional IO 1809 Input pin of input AND control type bidirectional IO Expected value waveform 1810 in the external input / output pad 1811, 1815, 1821 L pulse waveform 1812, 1813, 1814, 1816, 1817,
1818, 1820, 1822, 1823 Expected value waveform 1819 H level waveform 1824, 1825 L level waveform 1900 Semiconductor chip 1901 External input / output pad 1902 Input OR control type bidirectional IO 1903, 1904, 1905, 1906 Multiplexer 1907, 1908, 1910 Function block output pin 1909 Function block input pin 1911, 1912, 1913, 1914 Function block 1915, 1916, 1917 Mode control pad 1918, 1919, 1920 External input IO 1921 Input OR Controlled bidirectional IO output pin 1922 Input OR Input pin 1923 of control type bidirectional IO Output control pin 1924 of input OR control type bidirectional IO Input control pin 1925, 1926, 1927, 192 of input OR control type bidirectional IO Function block name 1929, 1931, 1940 Function block output pin name 1930 Function block input pin name 1932 Input OR control type bidirectional IO output control pin name 1933 Input OR control type bidirectional IO input pin name 1934 Input OR control type both Output pin name 1935 for input I / O control type bidirectional IO input control pin name 1936 External pad name 1937 Verification driver 1938 Verification driver input 1939 Verification driver output control pin 2000 Connection table 2001 Mode value 2002 External pad Name description position 2003, 2004, 2005, 2006 IO pin name description position 2007, 2008, 2009, 2010 Functional block name description position 2011, 2012, 2013, 2014 Functional block pin name description position 2100 Mode value input waveform 210 2102, 2104 Forced input waveform to output pin of functional block 2103 Expected value waveform at input pin of functional block 2105 Input waveform of verification driver 2106 Input OR control type Expected value waveform at input control pin of bidirectional IO 2107 Input OR control type both Expected value waveform 2108 at the output pin of the input / output control IO 2102 Expected value waveform at the output control pin of the input OR control type bidirectional IO 2109 Expected value waveform at the input pin of the input OR control type bidirectional IO 2110 Expected value waveform at the external input / output pad 2111, 2115, 2121 H pulse waveforms 2112, 2113, 2114, 2116, 2117,
2118, 2120, 2122, 2123 Expected value waveform 2119 H level waveform 2124, 2125 L level waveform 2200 Semiconductor chip 2201 External input / output pad 2202 Normal bidirectional IO 2203, 2204, 2205 Multiplexer 2207, 2208 Functional block Output pin 2209 Functional block Input pins 2211, 2212, 2213 Functional blocks 2215, 2216, 2217 Mode control pads 2218, 2219, 2220 External input IO 2221 Normal bidirectional IO output pin 2222 Normal bidirectional IO input pin 2223 Normal bidirectional IO output Control pin 2225, 2226, 2227 Function block name 2229, 2240 Function block output pin name 2230 Function block input pin name 2232 Normal bidirectional IO output control pin name 2233 Normal bidirectional IO input pin name 2234 Normal bidirectional IO output pin name 2236 External pad name 2237 Verification driver 2238 Verification driver input 2239 Verification driver output control pin 2300 Connection table 2301 Mode value 2302 External pad name Description position 2303, 230
4, 2305 IO pin name description position 2307, 2308, 2309 Function block name description position 2311, 2312, 2313 Function block pin name description position 2400 Mode value input waveform 2401, 2402 Forced input waveform to function block output pin 2403 Function block input Expected value waveform at pin 2405 Verification driver input waveform 2407 Expected value waveform at output pin of normal bidirectional IO 2408 Expected value waveform at output control pin of normal bidirectional IO 2409 Expected value waveform at input pin of normal bidirectional IO 2410 External Expected value waveforms 2415, 2421 H pulse waveforms 2416, 2417, 2418, 2420, 2422 in input / output pads,
2423 Expected value waveform 2419 H level waveform 2424, 2425 L level waveform 2500 Semiconductor chips 2501, 2502, 2518 External input pads 2503, 2504, 2523, 2524, 2525
External input IO 2505, 2506, 2507, 2517 Multiplexer 2508, 2509, 2510 Functional block 2511, 2512, 2513 Functional block input pin 2514, 2515, 2516 Functional block output pin 2518 External output IO 2519 External output pad 2520, 2521 , 2522 Mode control pad 2600 Input pattern 2601 from external input pad Observation pattern at functional block input pin 2602 Output pattern from functional block output pin 2603 Observation pattern at external output pad

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Claims (8)

(57) [Claims] 1. A plurality of functional blocks, a multiplexer that selectively outputs an output signal of the functional block according to a mode designation input to a mode control pad, and an external output pad that outputs the output of the multiplexer to the outside. In a test pattern generator for verifying a connection to a semiconductor chip, a connection in which output signal pins of a functional block whose connection is selected by the mode designation with respect to the external output pad is described for each mode. According to the table, means for generating a pulse waveform forcibly input with a time difference to each output signal pin of the functional block selected by the mode designation, Means for generating an inspection waveform, and a test comprising: Turn generating device. 2. An external input pad, a multiplexer for selectively inputting an input signal from the external input pad according to mode designation input to a mode control pad, and a plurality of functional blocks for inputting an output of the multiplexer.
In a test pattern generation device for verifying connection to a semiconductor chip having, a correspondence relationship between input signal pins of a functional block whose connection is selected by the mode designation with respect to the external input pad is described for each mode. According to the connection table, a means for generating a pulse waveform to be input to each of the external input pads with a time lag for each mode, and a matching of the signal waveform at each of the input signal pins of the functional block selected by the mode designation. A test pattern generation device comprising: a means for generating an inspection waveform for verification. 3. An external input pad, and an input AND control type IO that receives an input signal from the external input pad,
A first multiplexer that selectively outputs the output of the input AND control type IO according to a mode designation value N input to a mode control pad, a functional block that inputs the output of the first multiplexer, and the input AND control type IO A second multiplexer that selectively outputs an output signal of any one of the functional blocks according to the mode designation value N as an input to the control pin of the test pattern generation device for verifying connection to the semiconductor chip, Correspondence between input signal pins of a functional block whose connection is selected by the mode designating value N with respect to the input pad and connection by the mode designating value N with respect to the control pin of the input AND control type IO. According to the connection table that describes the correspondence between the output signal pins of the And means for generating a pulse waveform forcibly input with a time lag at the mode designating value N to each output signal pin of the functional block selected by the mode designating value N, and selected by the mode designating value N. A test pattern generation device, comprising: a means for generating a check waveform for verifying the matching of the signal waveforms at the input signal pin of the functional block and the control pin of the input AND control type IO. 4. An external input pad, an input OR control type IO that receives an input signal from the external input pad, and an output of the input OR control type IO according to a mode designating value N input to the mode control pad. A first multiplexer for selective output, a functional block for inputting the output of the first multiplexer, and an output signal of one of the functional blocks depending on the mode designation value N as an input to a control pin of the input OR control type IO. In a test pattern generation device for verifying connection to a semiconductor chip having a second multiplexer for selectively outputting, the input of a functional block whose connection is selected by the mode designation value N with respect to the external input pad. The correspondence between the signal pins and the control pin of the input OR control type IO is connected by the mode designation value N. According connection table that describes the correspondence between the output signal pins of-option is the functional block,
Means for generating a pulse waveform forcibly input with a time lag at the mode designation value N to each of the output signal pins of the functional blocks selected by the external input pad and the mode designation value N; And a means for generating an inspection waveform for verifying the coincidence of the signal waveforms at the input signal pin of the functional block selected by the above and the control pin of the input OR control type IO, respectively. . 5. A functional block, a first multiplexer for selectively outputting an output signal of the functional block according to a mode designation value N input to a mode control pad, and the first multiplexer.
As an input to the output tri-state control type IO that receives the output of the multiplexer, the external output pad that outputs the output of the output tri-state control type IO to the outside, and the control pin of the output tri-state control type IO. A test pattern generation device for verifying connection to a semiconductor chip, comprising: a second multiplexer that selectively outputs an output signal of one of the functional blocks according to the mode designation value N; Correspondence between the output signal pins of the functional block whose connection is selected by the mode designation value N and the output signal of the functional block whose connection is selected by the mode designation value N for the control pin of the output tristate control type IO. A device selected by the mode designation value N according to the connection table describing the pin correspondence. Means for generating a pulse waveform forcibly input with a time lag at the mode designation value N to each of the output signal pins of the functional block; And a means for generating an inspection waveform for verifying the coincidence of the test pattern generation device. 6. An external input / output pad, an input AND control type bidirectional IO whose bidirectional input / output pins are connected to the external input / output pad, and a mode designation value N input to a mode control pad. A first multiplexer that selectively outputs the output from the output pin of the input AND control type bidirectional IO, a first functional block that inputs the output of the first multiplexer, a second functional block, and the input AN.
A second multiplexer that selectively outputs the output signal of the second functional block according to the mode designation value N as an input to the input control pin of the D control type bidirectional IO, a third functional block, and the input AND control. Type bidirectional IO, a third multiplexer that selectively outputs the output signal of the third functional block according to the mode designation value N as an input to the input pin, a fourth functional block, and the input AND control type bidirectional A test pattern generation device for verifying connection to a semiconductor chip, comprising: a fourth multiplexer that selectively outputs an output signal of the fourth functional block according to the mode designation value N as an input to an IO output control pin. An output signal pin of a functional block whose connection is selected by the mode designation value N with respect to the external input / output pad, and The correspondence relationship between the input signal pins and the output control pin of the input AND control type bidirectional IO and the correspondence relationship between the output signal pin of the functional block whose connection is selected by the mode designating value N with respect to the input control pin are described. According to the connection table
A means for generating a pulse waveform and a level waveform forcibly input with a time difference at the mode designation value N to the output signal pin of the function block selected by the external input / output pad and the mode designation value N, respectively. A check waveform for verifying signal waveform matching at the input signal pin of the functional block selected by the mode designation value N, the output control pin and input control pin of the input AND control type bidirectional IO, and the external input / output pad. And a means for generating a test pattern generating apparatus. 7. An external input / output pad, an input OR control type bidirectional IO whose bidirectional input / output pins are connected to the external input / output pad, and a mode designation value N input to the mode control pad. A first multiplexer for selectively outputting the output from the output pin of the input OR control type bidirectional IO;
A first functional block for inputting the output of the first multiplexer, a second functional block, and the second functional block N as the input to the input control pin of the input OR control type bidirectional IO. A second multiplexer for selectively outputting the output signal of the functional block, a third functional block, and a third functional block of the third functional block according to the mode designation value N as an input to an input pin of the input OR control type bidirectional IO. A third multiplexer that selectively outputs an output signal, a fourth functional block, and the mode specifying value N as an input to an output control pin of the input OR control type bidirectional IO.
A test pattern generator for verifying connection to a semiconductor chip having a fourth multiplexer for selectively outputting an output signal of the fourth functional block according to: The correspondence between the output signal pin and the input signal pin of the functional block whose connection is selected by N, and the connection is selected by the mode designating value N for the output control pin and the input control pin of the input OR control type bidirectional IO. According to the connection table describing the correspondence relationship between the output signal pins of the functional block to be generated, the mode designating value N is set for each of the output signal pins of the functional block selected by the external input / output pad and the mode designating value N. Means for generating a pulse waveform and a level waveform forcibly input with a time difference; Generating a test waveform for verifying signal waveform matching at the input signal pin of the functional block selected by the constant value N, the output control pin and input control pin of the input OR control type bidirectional IO, and the external input / output pad. A test pattern generation device comprising: 8. An external input / output pad and a normal bidirectional I having a bidirectional input / output pin connected to the external input / output pad.
O, a first multiplexer for selectively outputting the output from the output pin of the normal bidirectional IO according to the mode designation value N input to the mode control pad, and a first function for inputting the output of the first multiplexer. A block, a second functional block, and a second multiplexer that selectively outputs the output signal of the second functional block according to the mode designation value N as an input to the input pin of the normal bidirectional IO,
The third functional block and the third bidirectional IO are controlled by the mode specifying value N as an input to the output control pin of the bidirectional IO.
In a test pattern generator for verifying connection to a semiconductor chip having a third multiplexer that selectively outputs the output signal of the function block of, the connection to the external input / output pad by the mode designation value N is performed. Correspondence between output signal pins and input signal pins of the selected functional block, and correspondence between output signal pins of the functional block whose connection is selected by the mode designation value N with respect to the output control pin of the normal bidirectional IO. And a pulse waveform and level forcibly input to the output signal pin of the functional block selected by the mode designating value N with a time difference at the mode designating value N according to the connection table describing Means for generating a waveform and input of a functional block selected by the mode designation value N No. pin, the normal test pattern generating apparatus characterized by comprising, means for generating a test waveform to verify the coincidence of the signal waveform in the bidirectional IO output control pins and the external output pad, respectively.