JPH0746123B2 - Integrated circuit test method - Google Patents

Description

The present invention relates to a test method of an integrated circuit in which flip-flops inside the integrated circuit are connected in series to perform a test, and a bus collision during a test is reduced to improve a test efficiency. For the purpose of the above, in a test method of an integrated circuit using a shift operation of flip-flops connected in series inside the integrated circuit, a driver control means for controlling the operation of the bidirectional bus driver,
A driver control signal output from the driver control means is introduced, and a limiting means for limiting the supply of the driver control signal to the bidirectional bus driver under test is provided, and the control of the bidirectional bus driver by the driver control means is limited. To configure.

[Industrial application field]

The present invention relates to an integrated circuit test method, and more particularly to an integrated circuit test method in which flip-flops inside the integrated circuit are connected in series to perform a test.

[Conventional technology]

In the current integrated circuit (eg, LSI) test, it is assumed that one location inside the LSI to be tested is faulty, test data is input, and output data for the input is verified.

However, this test method has a drawback that it is necessary to increase the number of patterns of test data to be input in proportion to the scale of the LSI, and it is not possible to verify a failure in a deep logic part.

A scan method is a test method for solving this drawback. FIG. 4 shows an explanation of the scanning method. In the scan method, all flip-flops 31 in the LSI 301 are previously set.
1,313, ..., 315,317 are provided with a scan circuit (scan-in terminal (hereinafter referred to as SI terminal), scan clock terminal (hereinafter referred to as ST terminal)) for LSI test, and an output terminal (Q Terminal) and the SI terminal of the next flip-flop are connected in series.

In such connection, the LSI test consists of the following steps.

Input scan-in data (setting of each flip-flop).

A scan clock signal (different from the system clock signal for performing normal operation) is input to the ST terminal of each flip-flop, and scan-in data is input from the SI terminal of the flip-flop 311 in synchronization with the scan clock signal. , Sequentially shift the data to each flip-flop. By this shift operation, scan-in data is set in each flip-flop.

Enter test data.

Input test data to the input pin of LSI301.

The operation is advanced by one cycle.

The system clock signal is input to the clock input terminal (T terminal) of each flip-flop to advance the operation for one cycle.

Continue scanning out data.

Input the scan clock signal to each flip-flop,
The data held in each flip-flop is taken out from the flip-flop 317 as scan-out data in synchronization with the scan clock signal.

Based on the scan-in data input in the above procedure, the test data input in the procedure, and the scan-out data and the output data of the output pin obtained in the procedure,
Verify the failure.

According to the present method, a contingency at a certain location does not need to be reflected to the outside of the LSI 301, but only the nearest flip-flop may be reflected. In addition, when setting a desired logic near the location to test a failure at a location, the LSI3
Instead of inputting data from the 01 input pin, data can be set using the shift operation of the scan circuit.

[Problems to be solved by the invention]

By the way, in the above-mentioned conventional method, when a signal is input from the output side of the bidirectional bus driver, the output side of the bidirectional bus driver must be in a high impedance state. At this time, since the output terminal in the high impedance state is opened, it can be used as an input terminal.

However, after inputting the test data from the output pin of the LSI (including the output side of the bidirectional bus driver), the operation was advanced for one cycle in synchronization with the system clock signal, and as a result, it was set in the driver control flip-flop. There was a problem that bus collision occurred depending on the value. When a bus collision occurs, the test pattern at that time becomes invalid, so that the efficiency of the test decreases.

The present invention was created in view of the above points, and an object thereof is to provide a test method for an integrated circuit that reduces bus collision during a test and improves test efficiency.

[Means for solving problems]

FIG. 1 is a block diagram showing the principle of an integrated circuit test system according to the present invention.

In the figure, flip-flops 141 and 143 are provided inside the integrated circuit.
Are connected in series.

The terminal 151 of the flip-flop 141 is a scan-in signal terminal, and the terminal 153 is a scan clock signal terminal. The terminal 161 of the flip-flop 143 is a scan-out signal terminal.

The driver control means 111 is used in combination with a certain stage of the flip-flops connected in series.

The bidirectional bus driver 131 includes an input terminal 155, a test signal output terminal / bus terminal 163, and a control signal input terminal from the control means 121.

The control means 121 receives the driver control signal output from the driver control means 111 and receives the bidirectional bus driver 131.
To limit the supply of bus driver control signals to control the state of.

[Action]

Flip-flops 141 and 143 connected in series and terminals 151 and 1
When testing the entire integrated circuit shown in the figure using the test data clock input from 53,
At the output terminal of the bidirectional bus driver 131, the test output data and the input test data for another test may coincide in time, causing a so-called bus collision.

In the present invention, the operation state is detected by the driver control means 111, and a control signal from the driver control means for controlling the operation of the bidirectional bus driver 131 to a required state is prevented from causing a bus collision. Means of restriction
Limited by 121. That is, a signal is sent from the control means 121 so that a signal for putting the bidirectional bus driver 131 into a high impedance state is input.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

2 and 3 show the configuration of an embodiment to which the test method of the integrated circuit of the present invention is applied.

I. Correspondence between the embodiment and FIG. 1 Here, the correspondence between the embodiment of the present invention and FIG. 1 will be shown.

The driver control means 111 corresponds to the flip-flop 211.

The limiting means 121 includes a NAND gate 221 and a flip-flop 22.
3, which corresponds to the flip-flop 225 and the flip-flop 227.

The bidirectional bus driver 131 corresponds to the bidirectional bus driver 231.

An embodiment of the present invention will be described below on the basis of the above correspondence.

II. Configuration of Embodiment In FIG. 2, each flip-flop (D
The flip-flop) has a data input terminal (D terminal), a clock input terminal (T terminal), for performing a normal operation,
In addition to the output terminal (Q terminal), a scan-in terminal (SI terminal) and a scan clock terminal (ST terminal) for performing an integrated circuit test by the scan method are provided.

The Q terminal of the flip-flop 241 is connected to the SI terminal of the next-stage flip-flop 243, and the Q terminal of the flip-flop 243 is connected to the SI terminal of the flip-flop 245. Similarly,
The Q terminal of the flip-flop 245 is connected to the SI terminal of the flip-flop 211 via another flip-flop, and the Q terminal of the flip-flop 211 is connected to the SI terminal of the flip-flop 247.

Scan-in data is externally input to the SI terminal of the flip-flop 241 and scan-out data is externally output from the Q terminal of the flip-flop 247.

The Q terminal of the flip-flop 241 is connected to the SI terminal of the test flip-flop 223 which does not have the input terminals (D terminal, T terminal) for normal operation.

The output from the Q terminal of the flip-flop 211 is input to the first input terminal of the two input terminals of the NAND gate 221, and the signal from the Q terminal of the flip-flop 223 is input to the second input terminal.

The output of the NAND gate 221 is input to the control terminal (C terminal) of the bidirectional bus driver 231 in negative logic. The output terminal of the bidirectional bus driver 231 is connected to the external bus via the input / output pin of the LSI 201, and at the same time, the input / output pin is connected to the input terminal of the receiver 233.

In response to the signal “1” output from the NAND gate 221, the signal input from the input / output pin is received by the receiver 233 when the output end of the bidirectional bus driver 231 is in the high impedance state.
You can receive it at. Further, when the signal “0” is input from the NAND gate 221 to the C terminal of the bidirectional bus driver 231, the bidirectional bus driver 231 causes the output terminal to have a low level (“0”) or a high level (“1”) according to the input signal. Signal can be output to the input / output pin of the LSI 201.

Further, the scan clock signal is input to the ST terminal of each flip-flop, and the system clock signal is input to the T terminal.

The LSI 201 includes a bidirectional bus driver 231 and a receiver 233.
In addition to the input pin connected to, the input pin for inputting data during normal operation is provided, and test data is input from the input pin and the input / output pin.

III. Operation of Embodiment Next, the operation of the test method of the integrated circuit according to the embodiment of the present invention will be described. Hereinafter, FIG. 2 will be referred to.

First, scan-in data is input from the outside of the LSI 201 to the SI terminal of the flip-flop 241 in synchronization with the scan clock signal.

For example, the scan-in data latched in the flip-flop 241 in synchronization with the rising edge of the scan clock signal is latched in the flip-flop 243 in synchronization with the rising edge of the next scan clock signal. Similarly, the scan-in data is sequentially synchronized with the rising edge of the scan clock signal and flip-flops 245, 211, ..., 247.
Is sequentially shifted to.

Next, the test data is input to the input pin of the LSI 201, and the operation is advanced for one cycle in synchronization with the system clock signal.

When the operation is advanced by one cycle in synchronization with the system clock signal, the driver control signal input to the D terminal of the flip-flop 211 is latched and input to the first input terminal of the NAND gate 221. Since the output of the flip-flop 223 is input to the second input terminal of the NAND gate 221, when the value latched by the flip-flop 223 is “1”,
An output signal corresponding to the signal input to the first input terminal of the NAND gate 221 is output from the NAND gate 221 to the bidirectional bus driver 2
Entered in 31.

Since the flip-flop 223 latches the scan-in data latched in the flip-flop 243 in synchronization with the next scan clock signal, “0” or “1” is input to the second input terminal of the NAND gate 221. Therefore, when “0” is input to the NAND gate 221, the flip-flop 2
The driver control signal input from 11 to the NAND gate 221 becomes invalid.

FIG. 3 shows the configuration of another embodiment. A flip-flop 225 and a flip-flop 227 for testing (having neither D terminal nor T terminal) are connected in series to the Q terminal of the flip-flop 223 of the embodiment shown in FIG. Nand Gate 221 4
The flip-flop 211 is provided at the first input terminal out of the two input terminals.
The output signal from the Q terminal of the flip-flop 223 to the second input terminal, the output signal from the Q terminal of the flip-flop 225 to the third input terminal,
The output signal from the Q terminal of the flip-flop 227 is input to the input terminal.

The driver control signal from the flip-flop 211 input to the first input terminal of the NAND gate 221 is valid when the values latched by the flip-flops 223 to 227 are all "1".

IV. Summary of Embodiments As described above, the output terminal (Q terminal) of the flip-flop 211 is connected to the C terminal of the bidirectional bus driver 231 via the NAND gate 221. "0" or "1" is input to the other input terminal of the NAND gate 221, and the driver control signal output from the flip-flop 211 is input to the bidirectional bus driver 231 only when "1" is input.

Therefore, it is possible to reduce the collision of the bus during the test of the LSI 201 and improve the test efficiency.

V. Modification of the Invention In the above-described embodiment of the present invention, the signal output from the flip-flop 243 is input to the NAND gate 221 after being latched in the test flip-flop 223 (and the flip-flops 225 and 227). The Q terminal of each flip-flop of the LSI 201 configured to perform normal operation may be directly connected to the input terminal of the NAND gate 221.

Further, in the embodiment, one of the flip-flops connected in series is used.
Although one (flip-flop 211) outputs the driver control signal, the same can be considered when the driver control signal is output from another constituent circuit (eg, gate). In this case, the output of the circuit is NAND gate
It may be introduced into the first input terminal of 221.

Furthermore, in “I. Correspondence between FIG. 1 and the embodiment,”
Although the correspondence between FIG. 1 and the present invention has been described, the present invention is not limited to this, and those skilled in the art can easily contemplate that there are various modifications.

〔The invention's effect〕

As described above, according to the present invention, the collision of the bus during the test can be reduced by limiting the supply of the driver control signal output from the driver control means to the bidirectional bus driver. Is extremely useful for

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of an integrated circuit test method of the present invention, FIG. 2 is a block diagram of an embodiment to which the integrated circuit test method of the present invention is applied, and FIG. 3 is an integrated circuit test of the present invention. FIG. 4 is a configuration diagram of another embodiment to which the method is applied, and FIG. 4 is an explanatory diagram of the scanning method. In the figure, 111 is a driver control means, 121 is a limiting means, 131 is a bidirectional bus driver, 201 is an LSI, 211,223,225,227,241,243,24.
5, 247 is a flip-flop, 221 is a NAND gate, 231 is a bidirectional bus driver, and 233 is a receiver.

Claims (1)

[Claims] 1. A bidirectional bus driver to which an input signal from an input terminal is applied in a test method of an integrated circuit utilizing a shift operation of a flip-flop connected in series inside the integrated circuit, and the bidirectional bus. In order to control the output state of the driver, driver control means for using a certain stage of the flip-flops connected in series and driver control signals output from the driver control means are introduced, and the bidirectional bus is introduced. A test method for an integrated circuit, comprising: a limiting unit that limits the supply of the driver control signal for controlling the state of the driver.