JPS61155874A - Method and device for detecting fault of large-scale integrated circuit - Google Patents

Abstract

PURPOSE:To improve the efficiency of a test by dividing shift registers which form a scan path corresponding to plural functional modules and detecting a fault of each functional module. CONSTITUTION:Scan paths 2a-2c are set in functional modules 1a-1c and control circuits 3a-3c which control them are provided. Different addresses are assigned to the circuits 3a-3c. Then, a circuit (e.g. 3a) whose assigned address coincides with its input address outputs clock pulses from a scan clock line 7a in synchronism with a clock from a clock input line 5 and places a scan-out control line 9a in an output enabled state while the state of a scan address/data selecting line 6 indicates data. Consequently, a shift register constituting a scan path 2a sends out scan-out data from a shared scan output line 8 to perform data processing and fault detection.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a method and apparatus for detecting failures in large-scale integrated circuits, and in particular to test II (evaluation) of the scan canvas method.
It is used for.

[Technical background and problems of the invention]

BACKGROUND ART Conventionally, a method called a scan canvas method has been known as a method for easily testing (evaluating) large-scale integrated circuits. In this test, the latch part (so-called system latch) included in the integrated circuit is configured with a shift register, and the test (
At the time of evaluation), scan input data is set in this system latch, the contents of the system latch are taken out after a predetermined operation is performed, and a failure of the integrated circuit is detected based on this scan output data.

In this way, in the scan canvas method, the system latch is configured as one shift register, so as the scale of the integrated circuit increases, the shift register tends to become longer in proportion. Therefore, if one of the plurality of system latches making up the shift register is out of order, failures in other system latches making up the shift register cannot be detected. Furthermore, when developing integrated circuits, it is necessary to detect failures in detail for all system latches, but as mentioned above, if there is a failure in one system latch, this does not mean that failures in other system latches cannot be detected. , unable to meet the demands during development.

Components (functional modules) that make up large-scale integrated circuits
There is also a method of performing a divided test for each test, but if this method is applied directly to the scan canvas method, the system latch is configured as one long shift register, which has the disadvantage of reducing test efficiency. Furthermore, if a normal test is to be performed on each functional module constituting a large-scale integrated circuit, a large number of input/output pins for testing must be arranged on the integrated circuit chip, which is undesirable.

[Purpose of the invention]

The present invention has been made to overcome the drawbacks of the prior art described above, and includes a fault detection method for large-scale integrated circuits that can detect faults on a functional module basis and improve testing (evaluation) efficiency. The purpose is to provide a device for

[Summary of the invention]

In order to achieve the above object, the present invention sets a scan path for each of a plurality of functional modules that constitute a large-scale integrated circuit, selects one of the plurality of functional modules based on address data, and selects one of the plurality of functional modules based on address data. The present invention provides a fault detection method for a large-scale integrated circuit, which inputs scan data into the scan path of a functional module, and detects a fault in the functional module based on the output of the scan path of a selected functional module, and a device therefor. be.

(Embodiments of the Invention) The present invention will now be described in detail with reference to FIGS. 1 and 2 of the accompanying drawings.

FIG. 1 is a block diagram of the same embodiment. Scanvases 2a, 2b, and 2c are set in the functional modules 1a, 1b, and IC constituting the large-scale integrated circuit, respectively, and a control circuit 3a for controlling them.

3b and 3cffi are provided. A shared scan input line 4 for transmitting scan input data and address data is connected to the scan canvases 2a to 2C of each functional module 1a to 1C, and is also connected to control circuits 3a to 3C. Further, a clock input line 5 for sending a scan clock for driving each circuit synchronously is connected to the control circuits 3a to 3C.
connected to.

Scan address/instruction to select/instruct whether to send address data or scan data using shared scan input line 4
A scan address/data selection line (hereinafter referred to as "selection line") 6 for sending a data selection signal (hereinafter referred to as "selection signal J") is connected to control circuits 3a to 3C.

Scan clock lines 7a, 7b, and 7c for sending scan clocks from control circuits 3a to 3C are connected to scan canvases 2a to 2C, respectively. Further, the scan output data from the scan canvases 2a to 2C is outputted via the shared scan output 1118, and this output operation is controlled by the scan output control lines 9a, 9b, 9c.
It is controlled by a signal output via the

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to the waveform diagram in FIG. 2.

When the state (selection signal) of the scan address/data selection/selection line 6 becomes a state indicating an address (high potential in FIG. 2), the control circuits 3a to 3C in each module receive data transmitted through the shared scan input line 4. The data is taken in as address information in synchronization with the scan clock. Here, different addresses are assigned in advance to each of the control circuits 3a, 3b, and 3c, and the control circuit (for example, 3a) whose input address and assigned address match
performs the following operations.

In other words, the control circuit 3a is in a state where the state of the scan address/data selection line 6 indicates data (low potential in FIG. 2).
While , a clock pulse (
At the same time, the scan output control 1111i19a is set to an output enabled state. As a result, the shift register constituting the scan bus 2a takes in scan input data from the shared scan input line 4 in synchronization with the scan clock, and sends out scan output data from the shared scan output line 8. This scan output data is taken into a check device (not shown) connected to the outside of the integrated circuit for data processing and fault detection.

On the other hand, in the control circuits (3b and 3C in this example) where the address given from the shared scan input line 4 and the pre-allocated address do not match, the gap 1! The operation is stopped until the state of the address/data selection line 6 again indicates an address.

After the failure of the functional module 1a is detected as described above, when the state of the scan address/data selection line 6 returns to the state indicating an address (high potential), the signal assigned to the control circuit 3b is detected. If the address and the input address match, only failure detection of the functional module 1b is performed and the sub-111 circuits 3a and 3b of other modules do not operate. In this way, by sending data with address information added to the shared scan input line 4, it is possible to select one module from a plurality of functional modules and perform scan input/output. In the above embodiment, it is only necessary to add one scan address/data selection line, so
Very efficient.

The present invention is not limited to the above embodiments, but the second embodiment
The shared scan input line 4 shown in the figure may be used to send only test data, and the scan address/data selection line may be used to send address data serially. However, if this is done, it becomes necessary to determine the start and end of the address data within each functional module (particularly within the control circuit).

Further, the clock for inputting test data (data clock) and the clock for inputting address data (address clock) may not be shared as scan clocks, but may be input from separate signal lines. moreover,
It is also possible to select 2° scan canvases with 0 address lines (n is a natural number), but if this is done, the number of signal lines increases.

(Effects of the Invention) As described above, in the present invention, the shift registers forming the scan canvas are divided for each of a plurality of functional modules constituting a large-scale integrated circuit, these shift registers are connected to a common line, and the functional modules are A means for inputting address information for selection was added, and this controlled the input and output of information to each functional module.
It is possible to obtain a fault detection method and apparatus for large-scale integrated circuits that can improve the efficiency of evaluation). Furthermore, since the present invention can be realized by adding a minimum number of signal lines, the effective area of the chip is not reduced and the number of external input/output pins is not increased unnecessarily.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a waveform diagram illustrating the operation of the embodiment. 1 a, 1 b, 1 c...function module, 2
a. 2b, 2c...Sukishinpass, 4...Shared Suki 1r
5... Clock input line, 6... Scan address/data selection line, 7a, 7b, 7c... Sink clock line, 8... Shared scan output line, 9a. 9b, 9c...Scan output control lines.

Claims (1)

[Claims] 1. Setting a scan path for each of a plurality of functional modules constituting a large-scale integrated circuit, selecting one of the plurality of functional modules based on address data, and scanning the selected functional module. A failure detection method for a large-scale integrated circuit, wherein scan data is input to a scan path of the selected functional module, and a failure of the selected functional module is detected based on the output of the scan path of the selected functional module. 2. A scan path set for each of the plurality of functional modules constituting a large-scale integrated circuit, a shared scan input line for inputting scan input data and address data to the plurality of functional modules, and a shared scan input line that inputs scan input data and address data to the plurality of functional modules; a scan address/data selection line for sending a selection signal for selecting whether the scan input data or the address data is sent; a shared scan output line for sending scan output data. 3. The functional module has control means for determining whether or not the own module is selected based on the address data, and inputting the scan input data from the shared scan input line to the scan path when the module is selected. A failure detection device for a large-scale integrated circuit according to claim 2. 4. The input of the address data, the input of the scan input data, and the output of the scan output data are performed according to a common scan clock.
3. A failure detection device for a large-scale integrated circuit according to item 1 or 3. 5. The large-scale integrated circuit according to claim 2 or 3, wherein the address data is input in accordance with an address clock, and the scan input data is input and the scan output data is output in accordance with a data clock. Fault detection device. 6. A scan path set for each of the plurality of functional modules constituting a large-scale integrated circuit, a shared scan data input line for inputting scan input data to the plurality of functional modules, and a shared scan data input line for inputting scan input data to the plurality of functional modules; A common address data input line to be input, and a shared address data input line provided for each of the plurality of functional modules, and determining whether or not the own module is selected based on the address data;
a control means for inputting scan input data from the shared scan data input line to the scan path of the own module when selected; and a control means for inputting scan output data output from the scan path of the functional module selected by the address data. A failure detection device for a large-scale integrated circuit, comprising a shared scan data output line for sending out. 7. The input of the address data, the input of the scan input data, and the output of the scan output data are performed according to a common scan clock.
A failure detection device for a large-scale integrated circuit as described in 2. 8. Failure detection in a large-scale integrated circuit according to claim 6, wherein the input of the address data is performed according to an address clock, and the input of the scan input data and the output of the scan output data are performed according to a data clock. Device.