JP2000338188A - Testing circuit for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of test patterns and the test time to reduce the cost for testing by mounting a serial-to-parallel converting circuit, etc., for converting the input data for scan pass test into parallel data. SOLUTION: The input data for scan pass test input from a data input terminal 7 for scan pass test is input to a serial-to-parallel converting circuit 9 to simultaneously determine two kinds of test pattern data. On the other hand, a semiconductor IC having a data input terminal 1 and an output terminal 4 is divided into functional modules 15, 16 respectively including combinational circuits 2, 3. The test pattern data output from the serial-parallel converting circuit 9 are respectively input to the functional modules 15, 16 for simultaneously testing them in parallel. Further the results of the scan pass test of the functional modules 15, 16 tested in parallel are input to an output selection circuit 11, and output from an output terminal for scan pass test. Whereby the fault of the functional modules 15, 16 is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit in a semiconductor integrated circuit, and more particularly to a test circuit of a scan path test system.

[0002]

2. Description of the Related Art Conventionally, a scan path test method has been used for detecting a failure in a semiconductor integrated circuit with a view to obtaining a high failure detection rate with a simple circuit configuration. FIG. 8 is a block diagram showing an example of a circuit of a conventional scan path test method. The scan path test method is
As shown in FIG. 9, all flip-flop circuits 2 of the circuit
The selector circuit 20 is added to the input portion of the switch 1 and the test is performed by switching the selector circuit 20 between a shift mode for taking in and outputting scan data and a normal mode for testing a combinational circuit.

[0005] By repeatedly performing the shift mode and the scan mode, the failure detection rate of the semiconductor integrated circuit is increased. More specifically, in the shift mode, scan data is serially input from the scan path test data input terminal 7 and is taken into the scan path test flip-flop X1 to the next scan path test flip-flops X2 to Xn. By shifting, data can be set in the combinational circuit 2. Next, the mode is switched to the normal mode, and the output data of the combinational circuit 2 is switched to the scan path test flip-flop Y1.
To Yn. Then, the mode is again switched to the shift mode, and the scan path test flip-flops Y1 to Yn
Is shifted and output from the scan data dedicated output terminal 12. By checking the data output from the output terminal 12, a failure inside the semiconductor integrated circuit can be detected. By repeating these operations, the accuracy of the failure detection of the semiconductor integrated circuit is improved.

Since one test requires at least (number of flip-flops + 1) clocks,
When n tests are performed to obtain a high failure detection rate, {(number of flip-flops + 1) × 2} × n patterns are required.

[0005]

However, the prior art has the following problems. A first problem is that when a scan path test is performed on a large-scale semiconductor integrated circuit, the cost required for the test increases. This is because the test pattern dedicated to the scan path test has a longer pattern length, so that the test time is longer. Further, since a large amount of the pattern memory of the tester is used, it is difficult to simultaneously test another semiconductor integrated circuit.

The second problem is that the test efficiency becomes worse as the semiconductor integrated circuit becomes larger. Because, in order to test one combinational circuit inside the semiconductor integrated circuit, it is necessary to repeat clocks by the number of flip-flops existing inside the semiconductor integrated circuit. This is because there is more time to go. This results in an increase in test time, which is the first problem.

An object of the present invention is to provide a test circuit for a semiconductor integrated circuit which solves the above problems.

[0008]

A test circuit for a semiconductor integrated circuit according to the present invention comprises a flip-flop for scan path test and a serial-parallel converter for converting scan data input from a data input terminal for scan path test into parallel. A circuit and an output selection circuit for serially outputting scan path test result output data to a scan path test output terminal in the semiconductor integrated circuit, and dividing the semiconductor integrated circuit into functional modules, A scan path shift register is provided for each scan path.

The test circuit for a semiconductor integrated circuit according to the present invention comprises a scan path test flip-flop and a serial-parallel conversion circuit for converting scan data input from a scan path test data input terminal into parallel. The circuit is divided into circuits for each functional module, and a semiconductor integrated circuit is divided for each functional module, a scan path shift register is formed for each functional module, and a scan path test output terminal connected to each functional module is provided. It is characterized by observing each output.

A test circuit for a semiconductor integrated circuit according to the present invention comprises: a scan path test flip-flop; a serial-parallel conversion circuit for converting scan data input from a scan path test data input terminal into parallel; The semiconductor integrated circuit includes an output selection circuit that serially outputs campus test result output data to a scan path test output terminal, and the semiconductor integrated circuit is divided into functional modules, and a scan path is provided for each of the functional modules. All the outputs of the combinational circuits existing in each of the functional modules.
It is characterized by taking -OR.

A test circuit for a semiconductor integrated circuit according to the present invention includes a scan path test flip-flop provided with an EX-OR circuit and a serial circuit for converting scan data input from a scan path test data input terminal into parallel. Having a parallel conversion circuit and an output selection circuit for serially outputting scan path test result output data to a scan path test output terminal in the semiconductor integrated circuit, and dividing the semiconductor integrated circuit into functional modules,
A scan path shift register is configured for each of the function modules, and an output of a combinational circuit existing in each of the function modules is output through an EX-OR circuit included in the scan path test flip-flop.

The test circuit for a semiconductor integrated circuit according to the present invention comprises a scan path test flip-flop and a serial-parallel conversion circuit for converting scan data input from a scan path test data input terminal into parallel. The circuit is divided into circuits for each functional module, and a semiconductor integrated circuit is divided for each functional module, a scan path shift register is formed for each functional module, and a scan path test output terminal connected to each functional module is provided. It is characterized in that outputs are observed, and EX-OR of all outputs of the combinational circuits existing in the respective function modules is obtained.

Further, a test circuit for a semiconductor integrated circuit according to the present invention comprises a scan path test flip-flop having an EX-OR circuit and a serial path for converting scan data input from a scan path test data input terminal into parallel. -Having a parallel conversion circuit in the semiconductor integrated circuit;
And, the semiconductor integrated circuit is divided into circuits for each function module, a scan path shift register is formed for each of the function modules, and the output of the scan path test output terminal connected to each of the function modules is observed. The output of a combinational circuit present in each of the functional modules is output through an EX-OR circuit included in the scan path test flip-flop.

[0014]

Embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a test circuit of a semiconductor integrated circuit according to a first embodiment of the present invention, which has scan path test flip-flops X1 to Z
n, and a serial converter for converting scan data input from the scan path test data input terminal 7 into parallel data.
The semiconductor integrated circuit includes a parallel conversion circuit 9 and an output selection circuit 11 that serially outputs scan path test result output data to a scan path test output terminal 12, and the semiconductor integrated circuit includes functional modules 15 and 16.
And a scan path shift register is configured for each functional module.

In FIG. 1, scan path test input data input from a scan path test data input terminal 7 is input to a serial-parallel conversion circuit 9, and a plurality of test pattern data (two types in FIG. 1) are simultaneously output. Set. On the other hand, a semiconductor integrated circuit having a data input terminal 1 and an output terminal
The functional module circuit 1 divides the test pattern data output from the serial-parallel conversion circuit 9 into two functional modules each including
5 and 16 are input to each, and the test is performed simultaneously and in parallel. Furthermore, the functional module circuit 1 tested in parallel
The scan path test results of Nos. 5 and 16 are input to the output selection circuit 11, and a failure is serially detected at the scan path test output terminal 12. As a result, by dividing the semiconductor integrated circuit into functional modules and performing scan path tests in parallel, the number of test patterns and test time can be significantly reduced, and the test cost of the semiconductor integrated circuit can be reduced. The effect is obtained.

The operation of this embodiment will be described below with reference to FIG.

First, the scan path test flip-flop X1 existing in the functional modules 15 and 16
9 is set to the shift mode by the input from the scan path test mode switching control terminals 5 and 6, input from the scan path test data input terminal 7, and output from the serial-parallel conversion circuit 9. The two types of scan data, which have been converted into parallel data, are connected to scan path test flip-flops X1 and Y
n scan data input terminals. At this time, the two types of scan data converted in parallel by the serial-parallel conversion circuit 9 are transferred to the function module 15.
The scan data selector circuit 10 determines which of the signals is input to the scan data selector 16 or the scan data selector 16 based on the scan data selector circuit control signal 13. Subsequently, the data input to the scan path test flip-flops X1 and Yn are shifted to X1 to Yn-m and Yn to Zn, respectively, and the outputs of the scan path test flip-flops Yn-m and Zn are output. Data selection circuit 11
, And selectively output based on the output data selection circuit control signal 14, so that the scan path test output terminal 1
From 2, the failure of the functional modules 15 and 16 is detected. That is, the scan data converted in parallel by the serial-parallel conversion circuit 9 is transmitted to the functional module 1.
5 and 16 are set. Then, the scan data output from each of the functional modules 15 and 16 is serially converted through the output selection circuit 11 and output from the scan path test output terminal 12. Thereby, the failure of the functional modules 15 and 16 can be detected. The clock signal is supplied from a clock input terminal 8.

For example, if there are 100 flip-flops in a semiconductor integrated circuit and 100 patterns are input, the conventional method uses (100 + 1) × 100 × 2
= 20200 patterns are required, but in the embodiment of FIG. 1, assuming that each of the functional modules 15 and 16 has 50 flip-flops, ((5
With 0 + 1) × 100 + 2)) × 2 = 10204 patterns, a fault equivalent to the conventional one can be detected.

Next, a test circuit for a semiconductor integrated circuit according to a second embodiment of the present invention will be described with reference to FIG. In the second embodiment of FIG. 2, the output selection circuit 11 is deleted from the circuit configuration of the first embodiment of FIG. 1, and scan path test output terminals 12 and 17 are provided for each functional module.

The operation is as follows. The two types of scan data converted in parallel by the serial-parallel conversion circuit 9 are respectively input to the scan data input terminals of the scan path test flip-flops X1 and Yn. At this time, the selector circuit 10 determines which of the two types of scan data converted in parallel by the serial-parallel conversion circuit 9 is input to the functional module 15 or 16. Subsequently, the data input to the scan path test flip-flops X1 and Yn are shifted to X1 to Yn-m and Yn to Zn, respectively, so that the outputs of the scan path test flip-flops Yn-m and Zn are shifted. From the scan path test output terminals 12 and 17 connected to the
5 and 16 faults are detected. That is, the scan data converted in parallel by the serial-parallel conversion circuit 9 is set in the function modules 15 and 16.
The scan data output from the functional modules 15 and 16 is output from the scan path test output terminals 12 and 17. As a result, the failure of the functional modules 15 and 16 can be detected earlier than in the embodiment of FIG.

Next, a test circuit for a semiconductor integrated circuit according to a third embodiment of the present invention will be described with reference to FIG. In the third embodiment shown in FIG. 3, EX-OR circuits 18 and 19 are provided which take exclusive ORs of all the outputs of the combination circuits 2 and 3 in the first embodiment shown in FIG.

The operation is as follows. The two types of scan data converted in parallel by the serial-parallel conversion circuit 9 are respectively input to the scan data input terminals of the scan path test flip-flops X1 and Yn. At this time, the selector circuit 10 determines which of the two types of scan data converted in parallel by the serial-parallel conversion circuit 9 is input to the functional module 15 or 16. Subsequently, the data input to the scan path test flip-flops X1 and Yn are shifted to X1 to Yn-m and Yn to Zn, respectively.
The outputs of nm and Zn are input to the output selection circuit 11 and selected and output, so that the output terminal 12
Of the functional modules 15 and 16 are detected.
Here, when the scan data is shifted, the outputs of the combination circuits 2 and 3 change, so that the outputs of the EX-OR circuits 18 and 19 connected thereto also change.
That is, the scan data converted in parallel by the serial-parallel conversion circuit 9 is set in the function modules 15 and 16. Then, the scan data output from each of the functional modules 15 and 16 is serially converted through the output selection circuit 11 and output from the scan path test output terminal 12. At the same time, changes in the outputs of the combinational circuits 2 and 3 are output from the EX-OR circuits 18 and 19 respectively connected thereto. As a result, the failure of the functional modules 15 and 16 can be detected earlier than in the embodiment of FIG. It is 1
This is because the outputs of the combinational circuits that are not tested and are discarded at the time of the test are used effectively by providing the EX-OR circuits 18 and 19.

Next, a test circuit for a semiconductor integrated circuit according to a fourth embodiment of the present invention will be described with reference to FIG. In the fourth embodiment of FIG. 4, circuits 18 and 19 are provided which take exclusive ORs (EX-OR circuits) of all the outputs of the combination circuits 2 and 3 in the second embodiment of FIG. ing. Therefore, the operation is as follows.

The two types of scan data converted in parallel by the serial-parallel conversion circuit 9 are input to scan data input terminals of scan path test flip-flops X1 and Yn, respectively. At this time, the selector circuit 10 determines which of the two types of scan data converted in parallel by the serial-parallel conversion circuit 9 is input to the functional module 15 or 16. Subsequently, the data input to the scan path test flip-flops X1 and Yn are shifted to X1 to Yn-m and Yn to Zn, respectively, so that the outputs of the scan path test flip-flops Yn-m and Zn are shifted. The failure of the functional modules 15 and 16 is detected from the scan path test output terminals 12 and 17 connected to. Here, when shifting the scan data,
Since the outputs of the combination circuits 2 and 3 change, the outputs of the EX-OR circuits 18 and 19 connected thereto also change. That is, the scan data converted in parallel by the serial-parallel conversion circuit 9 is set in the function modules 15 and 16. The scan data output from the functional modules 15 and 16 is output from the scan path test output terminals 12 and 17. At the same time, changes in the outputs of the combinational circuits 2 and 3 are output from the EX-OR circuits 18 and 19 respectively connected thereto. As a result, the failure of the function modules 15 and 16 can be detected earlier than in the embodiment of FIG. That is, the output of a combinational circuit that is discarded during one test and that is not a test target is EX-ORed.
This is because the circuits 18 and 19 are provided for effective use.

Next, a test circuit for a semiconductor integrated circuit according to a fifth embodiment of the present invention will be described with reference to FIG. In the fifth embodiment of FIG. 5, the scan path test flip-flops X1 to Zn in the first embodiment of FIG. 1 are replaced with the scan path test flip-flops XX1 to ZZn configured as shown in FIG. Things. Therefore, the operation is as follows.

The two types of scan data converted in parallel by the serial-parallel conversion circuit 9 are input to the scan data input terminals of the scan path test flip-flops XX1 and YYn, respectively. At this time, the serial-parallel conversion circuit 9 converts
The type of scan data is transferred to the function module 15 or 1
6 is determined by the selector circuit 10. Subsequently, the data input to the scan path test flip-flops XX1 and YYn is
Yn-m and YYn to ZZn are respectively shifted and flip-flops for scan path test YYn-m
And the output of ZZn are input to the output selection circuit 11 and selected and output, whereby the failure of the functional modules 15 and 16 is detected from the output terminal 12 for scan path test. Since the outputs of the combinational circuits 2 and 3 change when the scan data is shifted, the scan path test flip-flops XX1 to YY shown in FIG.
EX-OR circuit 2 existing in nm and YYn to ZZn
2 changes. Since the EX-OR circuit 22 is serially connected in each of the functional modules 15 and 16, the data output from the scan path test flip-flops YYn-m and ZZn, which are the final stage, also changes. Then, the output of the output terminal 4 connected to each also changes. That is, the scan data converted in parallel by the serial-parallel conversion circuit 9 is set in the function modules 15 and 16. Then, the scan data output from each of the functional modules 15 and 16 is serially converted through the output selection circuit 11 and output from the scan path test output terminal 12. At the same time, the changes in the outputs of the combinational circuits 2 and 3 are detected by the scan path test flip-flops XX1 to XX1.
The signal is output from the external terminal 4 through the EX-OR circuits 22 existing in YYn-m and YYn to ZZn. This allows
The failure of the functional modules 15 and 16 can be detected earlier than in the first embodiment of FIG. This is because the output of a combinational circuit that is discarded during one test and is not a test target is effectively used by providing the EX-OR circuit 22.

Next, a test circuit for a semiconductor integrated circuit according to a sixth embodiment of the present invention will be described with reference to FIG. In the sixth embodiment of FIG. 6, the scan path test flip-flops XX1 to Zn in the second embodiment of FIG. 2 are replaced with scan path test flip-flops XX1 to ZZn configured as shown in FIG. Things. Therefore, the operation is as follows.

The two types of scan data converted in parallel by the serial-parallel conversion circuit 9 are input to scan data input terminals of flip-flops XX1 and YYn for scan path tests. At this time, the serial-parallel conversion circuit 9 converts
The type of scan data is transferred to the function module 15 or 1
6 is determined by the selector circuit 10. Subsequently, the data input to the scan path test flip-flops XX1 and YYn is
The scan path test flip-flop YY is shifted by Yn-m and YYn to ZZn, respectively.
The failure of the functional modules 15 and 16 is detected from the scan path test output terminals 12 and 17 connected to the outputs of nm and ZZn. Here, when the scan data is shifted, the outputs of the combinational circuits 2 and 3 change. Therefore, the scan path test flip-flops XX1 to YYn-m and YYn to Z configured in FIG.
The output of the EX-OR circuit 22 existing in Zn changes.
Since this EX-OR circuit 22 is serially connected in each of the functional modules 15 and 16,
Scan path flip-flop YYn corresponding to the last stage
The data output from -m and ZZn also changes. Then, the output of the output terminal 4 connected to each also changes. That is, the scan data converted in parallel by the serial-parallel conversion circuit 9 is transmitted to the functional module 1.
5 and 16 are set. The scan data output from the functional modules 15 and 16 is output from the scan path test output terminals 12 and 17. At the same time, the changes in the outputs of the combinational circuits 2 and 3 are
Scan path test flip-flops XX1 to YYn
EX-OR circuit 22 existing in -m and YYn to ZZn
And output from the external terminal 4. As a result, the failure of the functional modules 15 and 16 can be detected earlier than in the second embodiment of FIG. This is because the output of a combinational circuit that is discarded during one test and is not a test target is effectively used by providing the EX-OR circuit 22.

[0029]

According to the present invention, the first effect is that a fault equivalent to the conventional one can be detected with a short test pattern. The reason is that, as described in the embodiment, a serial-parallel conversion circuit and an output selection circuit are incorporated in the semiconductor integrated circuit, and a scan path test circuit is configured for each functional module, so that the scan path test is performed in parallel Can be executed.

The second effect is that the cost required for testing the semiconductor integrated circuit is reduced. The reason is,
This is because the number of test patterns required for the test can be reduced, and as a result, the test time is reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing a third embodiment of the present invention.

FIG. 4 is a diagram showing a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a fifth embodiment of the present invention.

FIG. 6 is a diagram showing a sixth embodiment of the present invention.

FIG. 7 is a diagram showing one embodiment of a scan path flip-flop circuit of the present invention.

FIG. 8 is a block diagram showing an example of a conventional test circuit of a scan path test method.

FIG. 9 shows a configuration conventionally used in a scan path test circuit in which a selector is added to an input portion of a flip-flop.

[Explanation of symbols]

 Reference Signs List 1 data input terminal 2 combination circuit 3 combination circuit 4 output terminal 5 scan path test mode switching control terminal 6 scan path test mode switching control terminal 7 scan path test data input terminal 8 clock input terminal 9 serial-parallel conversion circuit 10 Scan data selector circuit 11 Output data selection circuit 12 Scan path test output terminal 13 Scan data selector circuit control signal 14 Output data selection circuit control signal 15 Function module 16 Function module 17 Scan path test output terminal 18 EX-OR circuit 19 EX-OR circuit 20 selector circuit 21 flip-flop circuit 22 EX-OR circuit

Claims (6)

[Claims] 1. A scan path test flip-flop, a serial-parallel conversion circuit for converting scan data input from a scan path test data input terminal into parallel, and output of scan path test result output data for scan path test The semiconductor integrated circuit has an output selection circuit for serially outputting to a terminal in the semiconductor integrated circuit, and the semiconductor integrated circuit is divided into circuits for each function module, and a scan path shift register is formed for each of the function modules Test circuit for semiconductor integrated circuits. 2. A semiconductor integrated circuit comprising: a scan path test flip-flop; and a serial-parallel conversion circuit for converting scan data input from a scan path test data input terminal into parallel. Divide the circuit for each functional module, configure a scan path shift register for each functional module,
A test circuit for a semiconductor integrated circuit, wherein an output of a scan path test output terminal connected to each of the functional modules is observed. 3. The EX-controller according to claim 1, wherein all of the outputs of the combinational circuits existing in each of the functional modules are EX-
2. The test circuit for a semiconductor integrated circuit according to claim 1, wherein an OR operation is performed. 4. The scan path test flip-flop according to claim 1, wherein the scan path test flip-flop comprises an EX-OR circuit,
2. The test circuit for a semiconductor integrated circuit according to claim 1, wherein an output of a combinational circuit present in each of the functional modules is output through an EX-OR circuit included in the scan path test flip-flop. 5. The apparatus according to claim 2, wherein all of the outputs of the combinational circuits in each of the functional modules are EX-
3. The test circuit for a semiconductor integrated circuit according to claim 2, wherein an OR operation is performed. 6. The scan path test flip-flop according to claim 2, further comprising: an EX-OR circuit;
3. The test circuit for a semiconductor integrated circuit according to claim 2, wherein an output of a combinational circuit present in each of the functional modules is output through an EX-OR circuit included in the scan path test flip-flop.