JP5453981B2 - LSI and test data setting method thereof - Google Patents

Description

  The present invention relates to an LSI and a test data setting method thereof.

  When the scale of LSI internal circuits becomes enormous due to miniaturization, multi-core, etc., the number of registers per scan chain increases due to the limitation of the number of external terminals. For this reason, the test time tends to increase due to the complexity of the test pattern during the LSI test.

  In addition, non-scanned portions that cannot be scanned due to physical restrictions such as delay and capacity may be included in the LSI. In such a case, full scanning cannot be performed during LSI testing. In such a case, in order to improve the failure detection rate (test coverage) of the LSI test, a function test for testing by operating a non-scan block may be performed.

JP 2008-226186 A Special table 2009-512872 gazette

  The function test described above has a problem that the test pattern length becomes very long. This is very long if the register group is set using the scan path even though only a part of the register group needs to set the initial value and expected value. This is because a large number of registers that do not need to be set are included in the functional test in the scan chain, and a test pattern in which values are set must be supplied to the registers that do not need to be set.

  As a technique related to the present invention, Patent Document 1 discloses an integrated circuit intended for testing on a device incorporating an ASIC. The integrated circuit disclosed in Patent Document 1 is not intended for LSI testing, nor is it related to a method of setting an initial value as a test condition. The integrated circuit disclosed in Patent Document 1 is only related to test control and does not disclose a method for setting an initial value for a desired register. Furthermore, the integrated circuit of Patent Document 1 includes a test condition storage unit called a register setting unit. Depending on the conditions to be held, the register setting unit can select a register for switching whether to test the arithmetic module, This is to set the setting register for module testing. For this reason, in the integrated circuit of Patent Document 1, it is impossible to directly set a value from the external pin to a register group that is uniquely determined based on an address given from the external pin.

  In addition, as another technique related to the present invention, Patent Document 2 discloses an IC test method. The IC test method of Patent Document 2 relates to a WIR (instruction register) that holds a test instruction for a test target (core). In the IC test method of Patent Document 2, data is set in the instruction register in two modes. Here, with respect to these data setting modes, the input to the serial shift register is merely the difference between using a scan chain or using one port of a parallel input. A value is input while performing a serial shift operation. For this reason, even in the IC test method of Patent Document 2, a value cannot be directly set from an external pin for a register group that is uniquely determined based on an address given from the external pin.

  Therefore, the object of the present invention is to make it possible to set data directly from an external pin only to a register that needs to be set at the time of an LSI test test without using a long scan path, thereby greatly increasing the test pattern length. An LSI capable of being reduced and a test data setting method thereof are provided.

  The LSI according to the present invention is connected to a logic circuit, and is connected in series to a plurality of setting register units constituting a scan chain, and based on a setting address signal input from the outside during the LSI test, A set strobe generation unit for generating a set strobe signal for designating a setting register unit to be set of setting data among the plurality of setting register units, and using the set strobe signal during LSI testing A setting data signal is inputted from the outside to the designated setting register section.

  According to the present invention, it is possible to provide an LSI that can greatly reduce the test pattern length and a test data setting method thereof.

1 is a block diagram showing a configuration of an LSI according to a first embodiment of the present invention. It is a block diagram which shows the structure of the setting register | resistor part which concerns on Embodiment 1 of this invention.

Embodiment 1 FIG.
Embodiment 1 of the present invention will be described below with reference to the drawings. First, the configuration of the LSI according to the first embodiment will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of an LSI according to the first embodiment. According to the LSI of the first embodiment, the test pattern can be set directly from an external pin only to a register that needs to be set during the LSI test test without using a long scan path. The length can be greatly reduced.

  As shown in FIG. 1, an LSI (semiconductor integrated circuit) 10 includes an external pin 20, an external pin 21, an external pin 22, an external pin 23, a set strobe generation unit 30, and a plurality of setting register units 40_1 to 40_1. 40 </ b> _n (hereinafter sometimes simply referred to as a setting register unit 40), a non-scan block 60, and a comparator 70.

  The setting register unit 40 is configured by collecting a group of registers that require setting of initial values, expected values, and the like in a function test in units of several bits. For example, the setting register unit 40_1 includes a register group 41_1 in which registers are grouped in units of several bits. Register groups 41 </ b> _ <b> 1 to 41 </ b> _n (hereinafter sometimes simply referred to as register group 41) included in the setting register unit 40 constitute a part of the scan chain 501. That is, the entire setting register unit 40 is serially connected to form a scan chain. The detailed configuration of the setting register unit 40 will be described later.

  The setting register unit 40 also includes a scan mode signal 203 from the external pin 22, a function test setting mode signal 204 from the external pin 23, a set strobe signal 301 from the set strobe generation unit 30, and an external pin 21. The setting data signal 202 is input. Based on these input signals, the setting register unit 40 holds setting data and supplies it as an expected value or an initial value of the non-scan block 60 during a function test.

  In the example shown in FIG. 1, an input signal to the non-scan block 60 is set in the setting register unit 40_1. Further, a signal used for comparison with the output signal from the non-scan block 60 is set in the setting register unit 40_2. The comparator 70 compares the output signal from the non-scan block 60 with the signal set in the setting register unit 40_2, and outputs the comparison result. Here, at the time of the LSI function test performed by operating the non-scan block 60, the initial value of the input signal to the non-scan block 60 is set in the setting register unit 40_1, and the output of the non-scan block 60 is set in the setting register unit 40_2. The expected value of the signal can be set.

  The set strobe generator 30 receives a setting address signal 201 for identifying the register group 41 to be set from the external pin 20. The set strobe generation unit 30 transmits a set strobe signal 301 generated based on the setting address signal 201 only to the setting register unit 40 to be set.

  The setting address signal 201, the setting data signal 202, the scan mode signal 203, and the function test setting mode signal 204 are input from a tester as an external device.

  FIG. 2 is a block diagram illustrating a detailed configuration of the setting register unit 40. The setting register unit 40 includes a plurality of setting registers 400_1 to 400_n (hereinafter sometimes simply referred to as setting register 400) and a plurality of setting value selection circuits 410_1 to 410_n (hereinafter simply referred to as setting value selection circuit 410). And a logical sum circuit 420. The example illustrated in FIG. 2 includes setting registers 400_1 to 400_n for a plurality of bits (here, 8 bits are illustrated).

  The setting value selection circuit 410 is one of the setting data signal 202, the scan input signal from the previous stage input according to the shift operation, and the output signal from the setting register 400 at the subsequent stage, depending on the mode during the LSI test. One signal is selected and output. More specifically, the set value selection circuit 410 is based on the scan mode signal 203, the function test setting mode signal 204, and the set strobe signal 301, and the previous stage scan output signal, the setting data signal 202, Any one of the output values from the setting register 400 is selected and output. When the scan mode signal 203 is High and the function test setting mode signal 204 is Low, the setting value selection circuit 410 selects the previous scan output signal, the function test setting mode signal 204 is High, and When the set strobe signal 301 is High, the setting data signal 202 is selected. In other cases, the value of the setting register 400 is selected and the selected signal is output. The output signal of the set value selection circuit 410 becomes the scan input signal SIN of the setting register 400.

  The setting register 400 is connected to normal logic as a combinational logic circuit and holds a signal input from the setting value selection circuit 410 at the previous stage. More specifically, the setting register 400 performs a shift operation based on the scan mode signal 203 or the function test setting mode signal 204 and holds the output value of the setting value selection circuit 410.

  The setting register 400 receives the output from the OR circuit 420 as SMC. When at least one of the scan mode signal 203 and the function test setting mode signal 204 is High, the output of the OR circuit 420 is High. As a result, the setting register 400 holds a value input as SIN from the setting value selection circuit 410 in the scan mode or the function test setting mode.

  Next, the test data setting operation of the LSI according to the first embodiment will be described. In the data setting mode at the time of the LSI function test, a function test setting mode signal 204 meaning a data setting mode is input from the external pin 23. The input function test setting mode signal 204 is supplied to the plurality of setting register units 40.

  A setting data signal 202 is input from the external pin 21 and supplied to each setting register unit 40. Further, a setting address signal 201 for identifying a register group to be set is input from the external pin 20, and the input setting address signal 201 is supplied to the set strobe generation unit 30.

  When the set address signal 201 is input, the set strobe generation unit 30 supplies the set strobe signal 301 only to the setting register unit 40 indicated by the address.

  The setting register unit 40 divides the supplied setting data signal 202 into one bit and sends it to a setting value selection circuit 410 that selects a scan input signal to each setting register 400. Further, the set strobe signal 301 and the function test setting mode signal 204 are also sent to each set value selection circuit 410.

  Upon receiving the set strobe signal 301 and the function test setting mode signal 204, the setting value selection circuit 410 outputs the setting data signal 202 as a scan input signal to the setting register 400.

  Accordingly, in the present invention, it is possible to directly set a value from the external pin to the setting register 400 without using the long scan chain 501.

As described above, the present invention has the following effects.
The first effect is that the set strobe generator 30 and the set value selection circuit 410 have a long scan chain by directly setting values from an external pin to a register that needs to be set in the LSI test. Compared to the data setting method using, the test pattern length can be greatly reduced.

  The second effect is that the operation range in the test is limited by using the function test setting mode signal, so that the power consumption during the LSI test can be reduced. Specifically, if there is a block that is completely unrelated in the functional test setting mode, that is, there is a block that does not need to operate, the power supply of the block that does not need to operate in the functional test setting mode By separating these, it becomes possible to stop the power supply of blocks that do not require operation in accordance with the function test setting mode signal. Thereby, it is possible to reduce the power consumption during the LSI test. Alternatively, in the function test setting mode, power supply during the LSI test can be reduced by stopping the supply of the clock to the blocks that do not require operation with the function test setting mode signal.

Other embodiments.
In the above-described embodiment, the external pin 22 of the scan mode signal 203 and the external pin 23 of the function test setting mode signal 204 are described as being configured, but the present invention is not limited to this. That is, since the scan mode and the function test setting mode do not operate simultaneously, the scan mode signal 203 and the function test setting mode signal 204 can be used as selection signals so that the external pins of the scan input signal can also be used. . As a result, since the external terminals need only be the setting address signal 201, the setting data signal 202, and the external pins of the scan input signal that are also used, the same effect can be obtained without increasing the number of external terminals.

  Note that the present invention is not limited to the above-described embodiment, and can be modified as appropriate without departing from the spirit of the present invention.

10 LSI,
20, 21, 22, 23 External pin,
30 set strobe generator,
40_1 to 40_n setting register section,
60 non-scan blocks,
501 scan chain,
400_1 to 400_n setting register,
410_1-410_n set value selection circuit,
420 logical sum circuit,

Claims (4)

A plurality of setting register units connected to the logic circuit and serially connected to form a scan chain, and
A set strobe generation unit for generating a set strobe signal for designating a setting register unit to be set with setting data among the plurality of setting register units based on a setting address signal input from the outside during an LSI test And comprising
The setting register section is
A setting value selection circuit, and a setting register to which an output signal from the setting value selection circuit is input according to a shift operation,
The set value selection circuit includes:
Depending on the mode at the time of the LSI test, the setting data signal input from the outside for the setting register unit specified using the set strobe signal, the scan input signal input according to the shift operation, and the setting register at the subsequent stage Select and output one of the output signals
The setting register is
An LSI, which is connected to a logic circuit and holds a signal input from the preceding set value selection circuit . A first setting register unit that is connected to a logic circuit and is connected serially as a whole to form a scan chain and sets an input signal to a non-scan block, and a comparison with an output signal from the non-scan block a plurality of setting registers unit at least chromatic and second setting register for setting a signal, the use in,
A set strobe generation unit for generating a set strobe signal for designating a setting register unit to be set with setting data among the plurality of setting register units based on a setting address signal input from the outside during an LSI test When,
A comparator that compares an output signal from the non-scan block and a signal set in the second setting register unit ;
During the LSI test, a setting data signal is input from the outside for the setting register unit specified using the set strobe signal .
During an LSI function test performed by operating the non-scan block, an initial value of an input signal to the non-scan block is set in the first setting register unit as the external setting data signal. 2. An LSI according to claim 2, wherein an expected value of an output signal when the initial value is input to the non-scan block is set in the setting register unit . A test data setting method for an LSI including a plurality of setting register units that are connected to a logic circuit and serially connected to form a scan chain, and a non-scan block,
The previous period setting register unit includes a setting value selection circuit and a setting register to which an output signal from the setting value selection circuit is input according to a shift operation.
For designating a setting register unit for setting data among the plurality of setting register units based on a setting address signal input from the outside during an LSI function test performed by operating the non-scan block A setting data signal is input from the outside for a setting register unit that generates a set strobe signal and is specified using the generated set strobe signal .
The set value selection circuit includes any of a setting data signal input from the outside, a scan input signal input according to a shift operation, and an output signal from the setting register in the subsequent stage, depending on a mode at the time of LSI test. Select one signal and output it,
The LSI test data setting method , wherein the setting register is connected to a logic circuit and holds a signal input from the setting value selection circuit in the previous stage . A test data setting method for an LSI including a plurality of setting register units that are connected to a logic circuit and serially connected to form a scan chain, a non-scan block, and a comparator ,
The plurality of setting register units include a first setting register unit that sets an input signal to the non-scan block, and a second setting register unit that sets a signal used for comparison with an output signal from the non-scan block. Have
For designating a setting register unit for setting data among the plurality of setting register units based on a setting address signal input from the outside during an LSI function test performed by operating the non-scan block A setting data signal is input from the outside for a setting register unit that generates a set strobe signal and is specified using the generated set strobe signal .
During an LSI function test performed by operating the non-scan block, an initial value of an input signal to the non-scan block is set in the first setting register unit as the external setting data signal. Set the expected value of the output signal when the initial value is input to the non-scan block in the setting register unit of 2,
The LSI test data setting method , wherein the comparator compares an output signal from the non-scan block with a signal set in the second setting register unit .

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