JP2017199445A - Memory test system and semiconductor device, and memory test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to test a path itself to latch output data from a memory, while suppressing an increase in scale of a circuit.SOLUTION: There is provided a memory test system including a built in self test (BIST) circuit built in a chip, the BIST circuit including a comparator circuit that compares output data from a memory on the chip with expectation value data from a test controller in order to test the memory, and thereby outputting a test result signal, wherein the flip-flop of the comparator circuit is also used as the flip-flop of a system logic circuit that latches the output data from the memory.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a memory test system, a semiconductor device, and a memory test method.

  Today's deep submicron technology makes it possible to mount enormous amounts of memory on a single chip. Memory BIST (Built In Self Test) technology is already known for performing post-manufacturing tests on a large number of memories arranged on these chips. Hereinafter, the built-in self-test circuit is referred to as “BIST circuit”. A memory test system provided with a BIST circuit is referred to as a BIST system.

  In the conventional BIST system, when the memory test is executed, the memory access is switched by the selector at the preceding stage, and the test access signal from the controller accesses the memory. The memory data output for this access is compared with an expected value obtained from the controller by a comparator, and the comparison result is output to the outside of the chip as a test output.

  However, in the conventional BIST system, as the number of memories increases, the number and size of BIST controllers increase accordingly. In addition, there is a problem that a portion for latching output data from the memory cannot be tested.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a memory test system capable of solving the above problems and testing a path itself for latching output data from a memory while suppressing an increase in circuit.

A memory test system according to an aspect of the present invention is a BIST (Built In Self Test) circuit built in a chip, and outputs data from the memory to a test controller in order to test the memory on the chip. A memory test system comprising a BIST circuit having a comparator circuit that outputs a test result signal by comparing with expected value data from
The flip-flop of the comparator circuit is shared with the flip-flop of the system logic circuit that latches output data from the memory.

  Therefore, according to the present invention, the path itself for latching the output data from the memory can be tested while suppressing an increase in circuit.

It is a schematic block diagram which shows the structural example of the BIST system which concerns on a comparative example. 1 is a schematic block diagram illustrating a configuration example of a BIST system according to a first embodiment. It is a schematic block diagram which shows the structural example of the BIST system which concerns on Embodiment 2. FIG. It is a schematic block diagram which shows the structural example of the BIST system which concerns on Embodiment 3. FIG. It is a schematic block diagram which shows the structural example of the BIST system which concerns on Embodiment 4. FIG. 10 is a schematic block diagram illustrating a configuration example of a BIST system according to a fifth embodiment. It is a schematic block diagram which shows the structural example of the BIST system which concerns on Embodiment 6. FIG.

  Hereinafter, a comparative example and an embodiment according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

Comparative example.
FIG. 1 is a schematic block diagram showing a configuration example of a BIST system according to a comparative example. 1, the BIST system includes a BIST circuit 10 built in a chip, a memory 20, a system logic circuit 21, a selector 22, and a system logic circuit 23. Here, the BIST circuit 10 includes a test pattern generator 11 of a test controller and a comparator circuit 12. The comparator circuit 12 includes a flip-flop (hereinafter referred to as FF) 51 that temporarily stores and outputs input data in synchronization with a clock, and an exclusive OR gate XOR1. The system logic circuit 23 includes an FF 52. The BIST clock is input to the test pattern generator 11 and the FFs 51 and 52.

  In FIG. 1, at the time of a memory test, a mode switching signal indicating a memory test mode is input from the test device to the selector 22 and the test pattern generator 11. At this time, the selector 22 is switched to the input B side, and the test pattern generator 11 generates a test access signal based on the BIST clock and outputs it to the memory 20 via the selector 22. The test pattern generator 11 generates expected value data and outputs it to the second input terminal of the XOR 1 of the comparator circuit 12. The output data read from the memory 20 is output via the first stage FF 52 of the system logic circuit 23 and also output as a test result signal via the FF 51 and XOR1.

  On the other hand, in response to a mode switching signal indicating the memory execution mode of the normal operation, the selector 22 is switched to the input A side, and the system access signal from the system logic circuit 21 is input to the memory 20 via the selector 22. At this time, the memory 20 performs operations such as normal data reading.

  In the BIST system configured as described above, in the memory test mode, the memory 20 is accessed by switching the selector 22 and the test access signal from the test pattern generator 11 in the controller accesses the memory 20. The output data of the memory 20 for this access is compared with the expected value data obtained from the test pattern generator 11 by the comparator circuit 12, and the comparison result signal is output as a test result signal to a tester device outside the chip.

  However, in the BIST system of FIG. 1, when the number of memories 20 increases, the number and size of controllers in the BIST circuit 10 increase accordingly, and there is a problem that a portion that latches output data from the memory 20 cannot be tested. there were. In order to solve this problem, the present inventors devised a BIST system according to the following embodiment.

Embodiment 1. FIG.
FIG. 2 is a schematic block diagram illustrating a configuration example of the BIST system (memory test system) according to the first embodiment. The BIST system according to the first embodiment in FIG. 2 is characterized in that the FF 51 in the comparator circuit 12 is shared with the FF 52 in the system logic circuit 23 as compared with the BIST system according to the comparative example in FIG. Specifically, it is as follows.
(1) Instead of the BIST circuit 10, a BIST circuit 10A is provided. The BIST circuit 10A includes a comparator circuit 12A in which the FF 51 is deleted instead of the comparator circuit 12.
(2) The output data from the FF 52 of the system logic circuit 23 is input to the first input terminal of the exclusive OR gate XOR1.
Hereinafter, the difference will be described in detail.

  In the BIST system according to the comparative example of FIG. 1, the output data from the memory 20 is latched by the FF 51 in the comparator circuit 12, and the expected value data from the test pattern generator 11 is separately compared with the output data. It was.

  On the other hand, in the first embodiment of FIG. 2, the circuit portion is changed, and the FF 52 in the system logic circuit 23 shares the FF that receives the output data from the memory 20. By receiving and inputting the output data from the shared FF 52 by the comparator circuit 12A of the BIST circuit 10A, the data passing through the path from the memory 20 to the shared FF 52 can be compared with the expected value data even in the memory test mode. It will be possible.

  Therefore, according to the first embodiment, even if any failure occurs in the path from the output of the memory 20 to the shared FF 52, the circuit failure can be detected by the memory test. In other words, a circuit failure between the memory 20 and the system logic circuit 23 can be found, and as a result, a defective chip can be found.

Embodiment 2. FIG.
FIG. 3 is a schematic block diagram illustrating a configuration example of the BIST system according to the second embodiment. The BIST system according to the second embodiment in FIG. 3 differs from the BIST system according to the first embodiment in FIG. 1 in the following points.
(1) A system logic circuit 23A is provided instead of the system logic circuit 23. The system logic circuit 23 </ b> A further includes a selector 24 before the clock input terminal of the shared FF 52.
Hereinafter, the difference will be described in detail.

  In FIG. 3, the selector 24 supplies the BIST clock to the shared FF 52 in response to the mode switching signal indicating the memory test mode, while the selector 24 shares the system clock in response to the mode switching signal indicating the memory execution mode. Supply to FF52.

  In the BIST system configured as described above, the clock supplied to the shared FF 52 can be switched to an arbitrary clock. For example, if a test by BIST is performed while supplying clocks of actual operating frequencies of the memory 20 and the system logic circuits 21 and 23A, a so-called At-Speed test is obtained.

  On the other hand, if there is any mismatch information of expected value data in the BIST test result at the actual operating frequency, the BIST test is performed with a clock slower than the actual operating frequency in order to analyze this in detail. As a result, it can be used to determine whether the mismatch is due to a delay fault or a stuck-at fault. Therefore, the overhead of the circuit can be suppressed.

Embodiment 3. FIG.
FIG. 4 is a schematic block diagram illustrating a configuration example of the BIST system according to the third embodiment. The BIST system according to Embodiment 3 in FIG. 4 differs from the BIST system according to Embodiment 1 in FIG. 1 in the following points.
(1) A system logic circuit 21A is provided instead of the system logic circuit 21. The system logic circuit 21A further includes the selector 22 shown in FIG. Hereinafter, the difference will be described in detail.

  4, the input side to the memory 20 is also provided in common with the FF 54 of the system logic circuit 21A, and the selector 22 is arranged in the preceding stage. That is, not only the output side of the memory 20 but also the path on the input side can be tested, and the circuit increase by the BIST circuit 10A (BIST controller) can be further suppressed. The effect of this increases as the number of BIST target memories provided on the circuit increases.

Embodiment 4 FIG.
FIG. 5 is a schematic block diagram illustrating a configuration example of a BIST system according to the fourth embodiment. The BIST system according to Embodiment 4 in FIG. 5 differs from the BIST system according to Embodiment 1 in FIG. 2 in the following points.
(1) A BIST circuit 10B is provided instead of the BIST circuit 10A. The BIST circuit 10B further includes a MOS switch 13.
Hereinafter, the difference will be described in detail.

  In FIG. 5, the MOS switch 13 is inserted between the output terminal of the FF 52 and the first input terminal of the exclusive OR gate XOR1. The MOS switch 13 is turned on in response to the mode switching signal indicating the memory test mode, and turned off in response to the mode switching signal indicating the memory execution mode.

  According to the fourth embodiment configured as described above, the power consumption of the BIST circuit 10B (BIST controller) can be suppressed by setting the MOS switch 13 to be off except during the BIST test. Further, since the output load capacity of the shared FF 52 is also reduced, more stable operation can be expected in the system logic circuit 23.

Embodiment 5. FIG.
FIG. 6 is a schematic block diagram illustrating a configuration example of a BIST system according to the fifth embodiment. The BIST system according to Embodiment 5 in FIG. 6 differs from the BIST system according to Embodiment 1 in FIG. 2 in the following points.
(1) A plurality of memories 20 and 20A to be tested are provided.
(2) A selector 22A that performs the same operation as the selector 22 is provided in the previous stage of the memory 20A.
(3) A system logic circuit 23B is provided instead of the system logic circuit 23A. Here, a FF 52A that operates in the same manner as the FF 52 is further provided in the subsequent stage of the memory 20A.
(4) A BIST circuit 10C is provided instead of the BIST circuit 10A. Here, a comparator circuit 12B is provided instead of the comparator circuit 12A. An XOR2 that performs the same operation as that of the exclusive OR gate XOR1 is further provided at the subsequent stage of the FF 52A.
Hereinafter, the difference will be described in detail.

  In FIG. 6, in the memory test mode, the test access signal is input to the memory 20A via the selector 22A, and in response to this, the output data from the memory 20A is input to the exclusive OR gate XOR2 via the FF 52A. Is done. The exclusive OR gate XOR2 outputs a test result signal which is a comparison result between the input output data and the expected value data.

  According to the fifth embodiment configured as described above, even when the BIST is realized for the plurality of memories 20 and 20A on the circuit, the FF of the system logic is set as the BIST controller for each of the memories 20 and 20A. Sharing. This makes it possible to test a path between the output from each of the memories 20 and 20A and the system logic circuit 23B while suppressing an increase in circuit due to the BIST.

  In the configuration example of FIG. 6 described above, the case of two memories 20 and 20A is illustrated. However, the present invention is not limited to this, and a plurality of memories 20 and 20A may be provided, and accordingly, the selectors 22 and 22A and the exclusive OR gates XOR1 and XOR2 are each provided with a plurality. . The configuration of the fifth embodiment may be similarly applied to the second to fourth embodiments.

Embodiment 6. FIG.
FIG. 7 is a schematic block diagram illustrating a configuration example of a BIST system according to the sixth embodiment. The BIST system according to Embodiment 6 in FIG. 7 differs from the BIST system according to Embodiment 1 in FIG. 2 in the following points.
(1) A BIST circuit 10D is provided instead of the BIST circuit 10A. Here, in place of the comparator circuit 12A, a MISR (Multiple Input Signature Register) 14 is provided.
Hereinafter, the difference will be described in detail.

  In FIG. 7, the MISR 14 compresses a plurality of input data from the memory 20 using a shift register with feedback of several tens of bits, and extracts and outputs the several tens of bits as a signature at the end of the test. If the output data from the memory 20 is the same, this signature takes the same signature value every time. Therefore, by comparing the signature of the normal operation with no circuit failure and the signature of the test result, the presence or absence of failure in the test is determined. It becomes possible to do.

  The configuration of the sixth embodiment may be similarly applied to the second to fifth embodiments.

  In the above embodiment, the BIST system including the BIST circuit has been described. However, the present invention can be applied to a semiconductor memory device or a semiconductor device including the BIST system.

Differences from Patent Document 1.
Patent Document 1 discloses a configuration in which an FF that accesses a memory in a normal operation and an FF that accesses a memory from a memory BIST controller are shared for the purpose of preventing memory access timing deterioration due to the memory BIST. However, as described above, the problem that the portion that latches the output data from the memory cannot be tested has not been solved.

  As described in detail above, unlike the circuit configuration of the conventional memory BIST, the path itself to the FF that first latches the output from the memory in the normal operation is used as a part of the comparator circuit of the memory BIST. Therefore, it is possible to test a path itself for latching output data from the memory while suppressing an increase in the circuit of the memory BIST.

10, 10A-10D ... BIST circuit,
11 ... Test pattern generator,
12, 12A, 12B... Comparator circuit,
13 ... MOS switch,
14 ... MISR,
20, 20A ... memory,
21 ... System logic circuit,
22, 22A ... selector,
23, 23A-23D ... system logic circuit,
24, 25 ... selector,
51-54, 53A ... flip-flop (FF),
XOR1, XOR2 ... exclusive OR gates.

Japanese Patent No. 4676967

Claims (9)

BIST (Built In Self Test) circuit built in the chip, in order to test the memory on the chip, the test result is obtained by comparing the output data from the memory with the expected value data from the test controller A memory test system comprising a BIST circuit having a comparator circuit for outputting a signal,
A memory test system, wherein a flip-flop of the comparator circuit is shared with a flip-flop of a system logic circuit that latches output data from the memory.   2. The memory test system according to claim 1, further comprising a selector which is provided in a preceding stage of a clock input terminal of the flip-flop of the shared system logic circuit and selects one clock from a plurality of clocks.   2. The memory test system according to claim 1, wherein a flip-flop that temporarily stores an access signal input to the memory is shared with a normal-operation flip-flop of a system logic circuit.   The switch connected between the output of the shared flip-flop and the input of the comparator circuit, further comprising a switch that is turned on during a test and turned off during a normal operation. The memory test system according to 1. With multiple memories,
5. The memory test system according to claim 1, wherein the memory test system is provided at an output of each of the memories and includes the shared flip-flop.   6. The MISR (Multiple Input Signature Register) that outputs a signature in response to output data from the shared flip-flop, instead of the comparator circuit. Memory test system described in 1.   A semiconductor device comprising the memory test system according to claim 1. A memory test method using the memory test system according to any one of claims 1 to 5,
The memory test method includes:
Receiving output data from the memory via the shared flip-flop;
A memory test method comprising: a comparator circuit outputting a test result signal by comparing the received output data with expected value data from a test controller. A memory test method using the memory test system according to claim 6,
The memory test method includes:
Receiving output data from the memory via the shared flip-flop;
A memory test method, wherein the MISR includes outputting a signature based on the received output data.

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