JP2012003792A - Semiconductor integrated circuit and method for inspecting the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of implementing a test between a memory and memory peripheral logic in a scan test.SOLUTION: A semiconductor integrated circuit comprises: a memory 10 having memory cells 22 to 25, redundant cells 26 and 27, and a selector 28 for selecting a redundant cell if a failed memory cell is found; a repair control circuit 13 for generating a first control signal used to make the selector select a redundant cell on the basis of external information; and a repair information retention latch 14 for latching the first control signal of a repair control circuit 13. The repair information retention latch 14 latches the first control signal generated by the repair control circuit 13 according to a second control signal.

Description

  The present invention relates to a semiconductor integrated circuit and a semiconductor integrated circuit inspection method, and more particularly to a semiconductor integrated circuit having a memory circuit having a redundant cell for defect relief and a semiconductor integrated circuit inspection method.

  The number of memory circuits mounted on a chip is increasing year by year. In general, a memory BIST (Built In Self-Test) is applied to the test of the memory itself, and a scan path test is used to test the peripheral part of the memory.

  However, due to the recent increase in the number of mounted memories, failures between the memory circuit and peripheral random logic cannot be ignored. In order to detect a failure between a memory and a random logic, a RAM (Random Access Memory) sequential test, which can expand a scan path test and include a memory circuit, is generally performed.

  On the other hand, as one of the measures for improving the manufacturing yield, there is a memory defect remedy method by replacing a defective memory cell with a redundant cell having redundancy. Defect relief is realized by setting relief information corresponding to the defect in a peripheral register of the memory circuit and using the memory under the set condition. The state of the defect relief circuit is determined by the presence or absence of a defect in the memory circuit mounted on each device and the position where the defect has occurred, and a different state setting is required for each device.

  A technique related to an integrated circuit system equipped with a memory relief circuit is described in Patent Document 1. FIG. 4 is a diagram showing the semiconductor integrated circuit 201. The semiconductor integrated circuit 201 includes a plurality of memory devices 211, a plurality of repair information analysis circuits 212, one storage device 213, and one repair information transfer circuit 114. The memory device 211 is a memory capable of performing redundant repair of a defective portion by inputting device repair information.

  The relief information D written in advance in the storage device 213 such as eFuse is serially transferred to the relief information analysis circuit 212 via the relief information transfer circuit 214.

  The repair information analysis circuit 212 receives the reset signal Sa, the registration signal Sb, the clock signal Sc, and the shift enable signal Sd, is controlled by these signals, analyzes the repair information, and inputs it to the memory device.

  FIG. 5 is a diagram showing the repair information analysis circuit 212. The repair information analysis circuit 212 includes an identification information storage unit 301, an identification information comparison unit 302, a device repair information registration unit 303, and a repair upper transfer unit 304.

  In the repair information analysis unit 212, based on the repair information transferred from the repair information transfer unit 304, arithmetic processing is performed by various arithmetic circuits including the identification information storage unit 301, the identification information comparison unit 302, and the device repair information registration unit 303. The device repair information DX for replacing the defective cell and the substitute cell is calculated. The calculated device repair information DX is output to the memory circuit 111.

  The defective cell existing in the memory circuit 111 is replaced with a normal cell by the replacement information, and normal operation can be performed.

  By the way, generally, in an LSI mounting a memory circuit such as an SRAM, the memory circuit is tested using a BIST circuit, and the memory peripheral circuit is tested using a scan path test. Conventionally, at a boundary portion between a memory and its peripheral circuit, it has been possible to perform a test without fail by using both a test using a BIST circuit and a test using a scan path test. However, lately, with the miniaturization and speeding up of processes, delay faults cannot be ignored. For this reason, the combined use of the scan path test and the test using the BIST circuit as described above has a problem that the path delay test actually used during normal operation cannot be correctly performed.

  Patent Document 2 describes a technique for testing a boundary portion between a memory circuit and its peripheral circuit, that is, a technique related to a RAM sequential test. FIG. 6 is a diagram showing an outline of the semiconductor integrated circuit described in Patent Document 2. In FIG.

  The semiconductor integrated circuit described in Patent Document 2 includes an SRAM 401, a BIST 402 for testing the SRAM, flip-flop circuits (hereinafter referred to as FF) 403 and 407 connected to a scan chain, combinational circuits 404 and 406, A selection circuit 405 that selects a signal from the BIST 402 and a signal from the combinational circuit 404 is provided.

  In the technique described in Patent Document 2, the test control signal is controlled so that access to the memory circuit is valid in the scan mode, and the data set in the scan FF 403 of the scan chain is written into the memory circuit 401.

  Next, the data written in the memory circuit 401 is read and captured by the scan FF 407 in the output stage of the memory circuit 401. The data fetched into the scan FF 407 is output to the outside of the LSI through the scan chain, and the expected value is determined by the tester. As a result, a RAM sequential test can be performed.

  In the technique described in Patent Document 2, the boundary between the memory circuit and the random logic circuit is tested by accessing the memory circuit during the scan path test.

  By the way, Patent Document 3 describes a technique related to a semiconductor integrated device manufacturing method and a semiconductor integrated device. The technique described in Patent Document 3 is a method of manufacturing a semiconductor device having a memory unit having a plurality of memory cells and a logic unit. When a memory unit is tested and the memory unit is defective, Keep information in registers. Then, based on the defect information held in the register, the defective cell is replaced with a redundant cell, and the logic unit is tested. Thereafter, the Fuse circuit is set based on the defect information held in the register.

JP 2008-226285 A JP 2004-012374 A International Publication No. 2002/059902

  However, when the technique described in Patent Document 2 is applied to a semiconductor integrated circuit having a defect relief circuit, the defect relief circuit is also a test target. Therefore, there is a possibility that the state of the defect relief circuit is not guaranteed, and therefore, a defective cell that should have been saved by the relief circuit is accessed, and a place that should be judged as a normal device can be judged as a defective device. There is a problem.

  Further, it is possible to exclude the defect relief circuit from the target of the scan test and completely separate it from the scan test and perform the RAM sequential test, but there is a problem that failure detection of the defect relief circuit cannot be performed.

  A semiconductor integrated circuit according to the present invention has a memory cell and a redundant cell, a memory having a selector for selecting a redundant cell when the memory cell is defective, and allows the selector to select a redundant cell based on information from the outside. A relief control circuit that generates a first control signal for the purpose, and a relief information holding latch that latches the first control signal of the relief control circuit. The relief information holding latch latches the first control signal generated by the relief control circuit in response to the second control signal.

  A method for testing a semiconductor integrated circuit according to the present invention includes: a first control signal for controlling a selector of a memory having a memory cell and a redundant cell; and a selector for selecting a redundant cell when the memory cell is defective. The relief information holding latch generated by the relief control circuit latches the first control signal generated by the relief control circuit according to the input second control signal, and the combinational circuit and the relief arranged around the memory The control circuit is tested by a scan chain that scan-tests the relief control circuit and the combinational circuit and a memory test circuit that tests the memory.

  In the present invention, in the memory circuit having the defect relief circuit, the relief information can be held during the scan test, so that the RAM sequential test in a state where the defect is relieved is possible.

  According to the present invention, a test between a RAM and a RAM peripheral logic can be realized by a scan test.

1 is a diagram showing an outline of a semiconductor integrated circuit 1 according to a first embodiment; 2 is a diagram showing a relief control circuit 13 and a relief information holding latch 14 according to the first embodiment. FIG. FIG. 4 is a diagram showing a portion of a semiconductor integrated circuit 2 according to a second embodiment. 1 is a diagram showing a conventional semiconductor integrated circuit 201. FIG. FIG. 11 is a diagram showing a conventional relief information transfer circuit 212. It is a figure which shows the outline | summary of the conventional semiconductor integrated circuit.

  For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. In addition, each element described in the drawings as a functional block for performing various processes can be configured by a CPU (Central Processing Unit), a memory, and other circuits in terms of hardware. This is realized by a program loaded on the computer. Therefore, it is understood by those skilled in the art that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof, and is not limited to any one. The configuration of each device shown in the following drawings is realized by executing a program read into a storage device on a computer (PC (personal computer), portable terminal device, etc.), for example.

  The program may be stored using various types of non-transitory computer readable media and supplied to a computer. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / W, semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (Random Access Memory)) are included. The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

Embodiment 1
FIG. 1 is a diagram showing an outline of a semiconductor integrated circuit 1 according to the present embodiment. The semiconductor integrated circuit 1 according to the present embodiment includes an SRAM (Static Random Access Memory) 10 as a memory, a BIST (Built In Self-Test) circuit 11, a Fuse circuit 12, a repair control circuit 13, and repair information. Holding latch 14. Further, the semiconductor integrated circuit 1 includes a combinational circuit 16, a selection circuit 17, a combinational circuit 18, and a scan FF 19.

  The SRAM 10 has normal cells 22 to 25 and redundant cells 26 and 27 therein, and has select circuits 21 and 28 for switching the normal cells to the redundant cells 26 or 27 when the normal cells 22 to 25 are defective. This is an SRAM with a defect relief mechanism.

  The BIST circuit 11 is a circuit for testing the SRAM 10.

  The fuse circuit 12 has information for defect repair of the SRAM 10 provided from the outside, and outputs the defect repair information to the repair control circuit 13. The Fuse circuit 12 is connected to the repair control circuit 13.

  The repair control circuit 13 receives defect repair information of the SRAM 10 from the fuse circuit 12. Then, a select signal which is a first control signal for causing the select circuit 21 or the select circuit 28 to select a redundant cell is generated and output to the repair information holding latch 14.

  The relief information holding latch 14 is a through latch, and performs a holding operation when the scan mode signal 33 which is a second control signal input from the outside is enabled, and becomes through logic when disabled. The relief information holding latch 14 outputs the select signal output from the relief control circuit 13 to the select circuits 21 and 28 when the scan mode signal 33 is enabled.

  The relief control circuit 13 and the relief information holding latch 14 will be described in more detail. FIG. 2 is a diagram showing the relief control circuit 13 and the relief information holding latch 14. The relief control circuit 13 includes relief control registers 131 to 133 and a relief information calculation circuit 134.

  The relief control registers 131 to 134 temporarily store defect relief information received from the Fuse circuit 12. The relief control registers 131 to 133 are configured by scan FFs and are connected to a scan chain (not shown). Therefore, the relief control registers 131 to 134 can be targeted for the scan test without being particularly distinguished from the scan test of the semiconductor integrated circuit 1.

  The repair information calculation circuit 134 generates a select signal based on the defect repair information received from the repair control registers 131 to 134.

  The relief information holding latch 14 includes an inverter 141 and latch circuits 142 to 144.

  The inverter 141 inverts the scan mode signal 33 input from the outside and inputs the inverted signal to the latch circuits 142 to 144.

  The latch circuits 142 to 144 perform a holding operation only when the scan mode signal 33 is enabled, and become a through logic in the disabled state.

  The select circuit 21 and the select circuit 28 replace the defective one of the normal cells 22 to 25 with the redundant cell 26 or 27 based on the select signal.

  Returning to FIG. 1, the semiconductor integrated circuit 1 will be further described. The semiconductor integrated circuit 1 includes a scan FF 15 as a logic circuit connected to the SRAM 10, a combination circuit 16, a select circuit 17, a combination circuit 18, and a scan FF 19.

  The scan FF 15 and the scan FF 19 are connected to a scan chain (not shown).

  The select circuit 17 switches between the signal from the BIST circuit 11 and the signal from the combinational circuit 16 based on the test control signal 30. Here, the test control signal 30 may be connected to the scan mode signal 33 of the LSI chip.

  The semiconductor integrated circuit 1 according to the present embodiment has a relief information holding latch 14, and the relief information holding latch 14 holds a select signal output from the relief control circuit 13 when the scan mode signal 33 is enabled. To do. While the select signal is held in the repair information holding latch 14, the defect repair of the SRAM 10 can be performed regardless of the operation of the repair control circuit 13.

  Next, the operation of the semiconductor integrated circuit 1 according to the present embodiment will be described. First, the fuse circuit 12 outputs defect repair information to the repair control circuit 13. The read defect repair information is transferred to the repair control registers 131 to 133 of the repair control circuit 13 via the fuse data transfer path 31.

The transferred defect repair information is calculated by the repair information calculation circuit 134 and is output as the select signal 32 to the SRAM circuit 10 via the latch circuits 142 to 144 of the repair information holding latch 14 in the output stage. At this time, the scan mode signal 33 is disabled.
It is “Low level” and is inverted by the inverter 141. Thereby, the latch circuits 142 to 144 become through logic.

  Next, after the select signal 32 reaches the select circuit 21 or 28 of the SRAM 10, the scan mode signal 32 is switched to "High" (enabled state). Here, the scan mode signal 32 may be a scan mode signal (not shown) of the semiconductor integrated circuit 1. As a result, the select signal 34 is held in the relief information holding latch 14.

  Next, a RAM sequential test including SRAM peripheral logic is performed. The test control signal 30 is fixed so that the combinational circuit 16 is always selected. Thereby, an access test to the SRAM 10 becomes possible.

  Next, the test data set in the scan FF 15 is written into the SRAM 10 via the combination circuit 16 through a scan chain (not shown). Data written in the SRAM 10 is read, captured by the scan FF 19 via the combinational circuit 18 at the subsequent stage of the SRAM 10, and output through the scan chain.

  At this time, the select signal 34 is held in the latch circuits 142 to 144, and the test can be performed without accessing the defective cell of the SRAM 10.

  In the semiconductor integrated circuit 1 according to the present embodiment, the retention of the select signal 34 can be controlled by the relief information holding latch 14 by the scan mode signal 33. When the scan mode signal 33 is disabled, desired defect repair information is transferred from the fuse circuit 12 to the repair control registers 131 to 133 and the repair information calculation circuit 134 via the fuse data transfer path 31. Is possible. Then, the select signal 34 as the calculation result can be output to the relief information holding latch 14.

  The select signal 34 output in the procedure is information necessary for replacing a defective cell of the SRAM 10 with a normal cell. After the steps are taken, the select signal 34 is held in the relief information holding latch 14 by enabling the scan mode signal 33. Once held, the select signal 34 for the SRAM 10 is not lost even if an arbitrary value is overwritten in the relief control registers 131 to 133 and 134 of the relief control circuit 13. As a result, the defective cell is not accessed in the RAM sequential test, and the relief control register can be simultaneously subjected to the scan test.

Embodiment 2
Next, the semiconductor integrated circuit 2 according to the present embodiment will be described. In the first embodiment and the present embodiment, the NAND circuit 36 as the first logic circuit that controls the latch circuits 142 to 144, and the observation unit 39 connected to the output stage of the latch circuits 142 to 144, Is different. FIG. 3 is a diagram showing a portion of the semiconductor integrated circuit 2 according to the present embodiment.

  The NAND circuit 36 receives the scan mode signal 33 and the RAM sequential mode signal 35 and generates a holding control signal 37.

  The sequential signal 35 is a mode signal for determining whether or not to execute the RAM sequential test, and is provided separately from the scan mode signal. The latch circuits 142 to 144 are through logic when the holding control signal 37 generated by the NAND circuit 36 is High, and perform a holding operation when the holding control signal 37 is Low. Therefore, the latch circuits 142 to 144 perform the holding operation only when the scan mode signal 33 is High and the sequential mode signal 35 is High.

  The AND circuit 38 receives the holding control signal 37 and the select signal 34, takes an AND logic of the two signals, and outputs it to the observation unit 39.

  The observation unit 39 includes a scan FF and observes a signal input via the AND circuit 38.

  Next, the operation of the semiconductor integrated circuit 2 according to the present embodiment will be described. Since the operation from the output of defect repair information of the Fuse circuit 12 to the output of the select signal 34 to the SRAM 10 via the latch circuits 142 to 144 is the same as that of the first embodiment, it is omitted here.

  After the select signal 34 reaches the SRAM 10, the scan mode signal 33 and the scan mode signal 33 are enabled, and the holding control signal 37 is switched to “High”. Then, the holding control signal 37 is held in the latch circuits 142 to 144.

  In this case, the observation unit 39 is fixed to the “Low” state by the AND circuit 38. By this fixed control, it is possible to prevent the observation unit 39 from capturing different defect relief information for each semiconductor integrated circuit. In other words, the defect relief information differs for each chip, and it is difficult to create an expected value corresponding to the information on the test vector, but this fixed control serves as a mask means for preventing it.

  In this case, the operation is the same as that of the first embodiment, and the scan test of the repair information calculation circuit 134 and the repair control registers 131 to 133 can be performed. At this time, a RAM sequential test for the SRAM circuit 10 can be used together.

  Next, an operation when the failure detection of the repair control circuit 13 and the repair information holding latch 14 is performed using the observation unit 39 will be described.

  Also in this case, the description will be made from the time when the select signal 34 reaches the SRAM 10. First, only the scan mode signal 33 is enabled “High”, and the sequential mode signal 35 is disabled “Low”. As a result, the holding control signal 37 becomes High, and the latch circuits 142 to 144 maintain the through logic. At the same time, the relief control register 13 also performs an arbitrary operation, so that the RAM sequential test cannot be executed.

  On the other hand, the fixed control of the AND circuit 38 arranged at the subsequent stage of the latch circuits 142 to 144 is removed. As a result, the output signals of the latch circuits 142 to 144 are taken into the observation unit 39.

  As a result, the select signal 34 is not held, and the repair information calculation circuit 134 and the latch circuits 142 to 144 can be tested using a desired value shifted into the repair control register 132.

  The semiconductor integrated circuit 2 according to the present embodiment can detect a failure of the latch circuits 142 to 144 that cannot be detected in the first embodiment. Further, in the first embodiment, it is possible to detect a failure of the repair information calculation circuit, in which a portion where failure detection is impossible is left. Further, by controlling the scan mode signal 33 and the sequential signal 35, a RAM sequential test can be realized as shown in the first embodiment.

  In the semiconductor integrated circuit 1 according to the present embodiment, in a memory circuit having a defect relief circuit, the relief information can be held during a scan test, so that a RAM sequential test in a state where the defect is relieved is possible. . Thereby, the test between the RAM and the RAM peripheral logic can be realized by the scan test.

  Also, by enabling the holding mechanism only during the RAM sequential operation, it becomes possible to realize a test of the defect relief circuit itself including the holding circuit by a scan test.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 2 Semiconductor integrated circuit 10 SRAM
11 BIST circuit 12 Fuse circuit 13 Relief control circuit 14 Relief information holding latch 15 Scan FF
16 Combination circuit 17 Select circuit 18 Combination circuit 19 Scan FF
DESCRIPTION OF SYMBOLS 21 Select circuit 22 Normal cell 23 Normal cell 24 Normal cell 25 Normal cell 26 Redundant cell 27 Redundant cell 28 Select circuit 30 Test control signal 31 Fuse data transfer path 32 Select signal 33 Scan mode signal 34 Select signal 35 Sequential signal 36 NAND circuit 37 Holding control signal 38 AND circuit 39 Observation unit 131 Relief control register 132 Relief control register 133 Relief control register 134 Relief information calculation circuit 141 Inverter 142 Latch circuit 143 Latch circuit 144 Latch circuit

Claims (7)

A memory having a memory cell and a redundant cell, and a selector for selecting the redundant cell when the memory cell is defective;
A relief control circuit for generating a first control signal for causing the selector to select the redundant cell based on information from outside;
A relief information holding latch for latching the first control signal of the relief control circuit, wherein the relief information holding latch is the first control generated by the relief control circuit in response to a second control signal. A semiconductor integrated circuit that latches signals.   The semiconductor integrated circuit according to claim 1, wherein the second control signal is a scan mode signal. A memory test circuit for testing the memory;
A combinational circuit disposed around the memory;
A scan chain that scan-tests the combinational circuit,
The relief control circuit is connected to the scan chain,
2. The repair control circuit and the combinational circuit are tested using the scan chain and the memory after the repair information holding latch latches the first control signal in response to the second control signal. Or the semiconductor integrated circuit of 2. A first logic circuit for generating a latch signal of the relief information holding latch based on the second control signal and the third control signal;
An observation unit for observing data latched by the relief information holding latch;
A second logic circuit for generating a fourth control signal for determining whether to take data into the observation unit based on the latch signal and the first control signal;
4. The semiconductor according to claim 1, wherein the latch signal is deactivated by the first logic circuit, and data is taken into the observation unit by the fourth control signal of the second logic circuit. 5. Integrated circuit. Generating a first control signal for controlling the selector of a memory having a memory cell and a redundant cell, and a selector for selecting the redundant cell when the memory cell is defective;
The relief information holding latch latches the first control signal generated by the relief control circuit in response to the input second control signal,
A test method for a semiconductor integrated circuit, wherein the combinational circuit and the relief control circuit arranged around the memory are tested by a scan chain for performing a scan test on the relief control circuit and the combinational circuit and a memory test circuit for testing the memory.   6. The method of testing a semiconductor integrated circuit according to claim 5, wherein the second control signal is a scan mode signal. Generating a latch signal of the relief information holding latch based on the second control signal and the third control signal by a first logic circuit;
A second logic circuit for generating a fourth control signal for deciding whether to take data into the observation unit based on the latch signal and the first control signal;
The latch signal is deactivated by the first logic circuit, and data is taken into an observation unit for observing the data latched by the relief information holding latch by the fourth control signal of the second logic circuit. A method for testing a semiconductor integrated circuit according to claim 5 or 6.

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