JP2006349548A - Built-in self-checking circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means which easily tests a fault of a scan path itself in an LSI test using a built-in self-checking circuit, and furthermore to provide a means which easily determines a fault location in the scan path in its fault diagnosis process. <P>SOLUTION: A comparator circuit 304 for comparing output responses both of which are output by the scan path 303 is disposed in the built-in self-checking circuit, and an output response of the comparator circuit 304 is used as a test termination signal of the built-in self-checking circuit. Furthermore, the comparator circuit 304 of the scan path 303 is arranged for a flip-flop 302 in each stage on the scan path 303, in order to enable output responses of each flip-flop 302 to be compared, in addition to comparing outputs of the final stage of the scan path 303. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a built-in self-test circuit, and more particularly to a built-in self-test circuit having a circuit configuration for testing and diagnosing a scan path failure for testing a semiconductor integrated circuit such as an LSI.

  In LSI inspection, test patterns are applied and output responses are observed using a tester. However, along with the recent increase in scale and speed of LSIs, there are problems such as the tester operating frequency not being able to keep up with the LSI operating frequency, and the test pattern data being too large to store in the tester memory. It is happening. Therefore, a built-in self test (BIST) method has been proposed as one of the testability design methods for avoiding these problems.

  Built-in self-inspection is a test circuit built into the LSI, and the test itself is generated without externally providing a test pattern by generating a test pattern and comparing the output response with the expected value inside the LSI. (See Non-Patent Document 1).

  When testing LSIs with built-in self-test circuits, test patterns are generated and output responses are observed inside the circuit, so the test can be performed at the circuit's original operating frequency. There is an advantage that inspection can be performed if only the signal is observed.

  However, the pass / fail judgment signal is output by comparing the expected value with the value stored in the output response compressor after all of the predetermined test patterns are applied, so that the test pattern is applied to the circuit to be inspected. Even if the scan path provided in the test fails itself and the test pattern application itself cannot be performed normally, the inspection is continued to the end, resulting in a waste of inspection time.

  Also, just by checking the value of the output response compressor after all patterns are applied, it is distinguished whether the cause of the failure is in the circuit to be inspected or in the scan path during the failure diagnosis process for identifying the cause of the failure. There is a problem that it is difficult.

On the other hand, in Patent Document 1, when a writable memory is mounted on the circuit to be inspected, output data from the scan path is temporarily stored in the memory, and the stored data is compared with a normal value. By doing so, it is possible to inspect failures on the scan path. However, this method requires special settings that are not used during normal testing in order to store the scan path in the memory inside the circuit, and compares the expected value after all the scan path output has been stored in the memory. Therefore, it is impossible to immediately detect a failure of the scan path itself.
JP 2003-234409 A “Digital Systems Testing and Testable DESIGN”, Chapter 11, published by Built-In Self-Test Computer Science Press 1990

  As described above, in the built-in self-test circuit of the conventional LSI, even if the scan path itself provided for the test pattern application fails and the test pattern application itself cannot be performed normally, all the test patterns are applied. There is a problem that the inspection is continued until is applied. Moreover, it is difficult to distinguish whether the scan path is faulty or the circuit to be inspected is faulty at the time of fault diagnosis processing only by inspecting the value stored in the output response compressor after applying all test patterns. There was a problem.

  An object of the present invention is to provide a built-in self-inspection circuit having means for easily inspecting a failure of a scan path itself for these problems.

  It is another object of the present invention to provide a built-in self-inspection circuit having means for easily determining which part of the scan path is faulty during failure diagnosis processing.

  In order to solve the above problems, the present invention takes the following measures.

  The built-in self-test circuit according to the present invention includes a plurality of scan paths for performing a test, a pattern generator for supplying a test pattern to the scan path, and an output response compressor for storing an output response from the scan path. A built-in self-test circuit comprising scan path comparison means for comparing output responses between the plurality of scan paths.

  In the above configuration, the scan path comparison unit uses the comparison result as a test end signal.

  In the above configuration, the plurality of scan paths have a plurality of stages of flip-flops, and the scan path comparison means compares the output responses of the flip-flops of each stage existing on the scan path.

  In the above configuration, the scan path comparison unit stores the comparison result output value in a plurality of flip-flops configured in a chain.

  According to the present invention, by comparing output responses between scan paths at the start of a test, if the scan path fails and the application of the test pattern itself cannot be performed normally, the test is immediately terminated, which is useless. It is possible to prevent the test from continuing.

  Further, by comparing output responses between scan paths for flip-flops at each stage on the scan path, it is possible to identify which flip-flop on the scan path is faulty.

  Further, at this time, the comparison result output value of the output response of each stage flip-flop is stored in the flip-flop, and is configured in a chain shape, thereby preventing an increase in external output pins for observing the comparison result output value. .

(Embodiment 1)
FIG. 1 is a diagram showing a basic configuration of a built-in self-test circuit in a first embodiment (corresponding to claim 1) of the present invention. In FIG. 1, 100 is a pattern generator which is a generator for generating a random pattern, 101 is an output response compressor, 102 is a scan flip-flop in the circuit under test, 103 is a scan flip-flop 102 configured on a chain. A campus 104 is a scan path output response comparison circuit that compares output responses of a plurality of scan paths 103.

  The test is performed by inputting the pattern generated by the pattern generator 100 to the scan path 103, storing the output response in the output response compressor 101, and comparing the expected value with a pass / fail judgment signal.

  The operation for detecting a scan path failure according to this embodiment will be described below. First, before performing the above-described normal inspection using the pattern generated by the pattern generator 100, 0 is applied to all the scan paths 103 in the circuit. At this time, the output value from each scan path 103 is zero. In this embodiment, the scan path output response comparison circuit 104 is configured by an exclusive-OR gate, and the two scan paths 103 are connected. Therefore, the input value to the scan path output response comparison circuit 104 is ( 0,0). At this time, the output value is 0 due to the logical characteristics of the exclusive-OR gate, but if one scan path 103 is faulty and the output value from the scan path 103 is 1, the input to the exclusive-OR gate The value is (0,1) or (1,0), and the output value is 1. Similarly, if 1 is applied to all of the scan paths 103, the scan path response comparison circuit 104 outputs 0 if the scan path 103 is normal, but when the scan path outputs 0 due to a failure, The campus output response comparison circuit 104 outputs 1.

  As described above, according to the present embodiment, by inputting 0 or 1 to all the scan paths 103 at the start of the test, if any scan path 103 has a failure, the scan path output response comparison circuit 104 1 is output, and the failure of the scan path 103 is immediately identified.

  In this embodiment, an exclusive-OR gate is used as the scan path output response comparison circuit 104. However, other logic elements may be used in practice. The scan path output response comparison circuit 104 receives the outputs of a plurality of scan paths 103, but the output responses of the scan paths 103 may be compared several by one, or all the scan paths 103 may be compared with one scan path. The output response comparator 104 may perform comparison.

(Embodiment 2)
FIG. 2 is a diagram showing a configuration of a built-in self-test circuit according to the second embodiment (corresponding to claim 2) of the present invention. Reference numeral 200 denotes a pattern generator, 201 denotes an output response compressor, 202 denotes a scan flip-flop in the circuit to be tested, 203 denotes a scan path in which the scan flip-flop 202 is configured on a chain, and 204 denotes an output response between a plurality of scan paths 203 A scan path output response comparison circuit 205 for comparing the two is a test end signal generator. The test by the built-in self-test circuit is the same as that of the first embodiment.

  In the present embodiment, the output of each scan path output response comparison circuit 204 corresponding to the scan path output response comparison circuit 104 in the first embodiment is input to the test end signal generator 205.

  The operation according to this embodiment configured as described above will be described below. As in the first embodiment, when 0 or 1 is applied to all of the scan paths 203, if the output value of each scan path 203 is normal, the scan path output response comparison circuit 204 outputs 0, When the scan path 203 is out of order, the scan path output response comparison circuit 204 outputs 1. If the output value of the scan path output response comparison circuit 204 is 1, the test end signal generator 205 generates a test end signal and ends the test before the normal test by the built-in self-test circuit is performed.

  As described above, according to the present embodiment, the output from the scan path output response comparison circuit 204 is not output to the outside, but connected to the test end signal generator 205, thereby preventing an increase in external pins, When the failure of the scan path 203 is found, the test can be terminated, and it is possible to prevent the test from being continued unnecessarily even though the scan path 203 itself has failed.

(Embodiment 3)
FIG. 3 is a diagram showing a configuration in the third embodiment (corresponding to claim 3) of the present invention. In FIG. 3, 300 is a pattern generator, 301 is an output response compressor, 302 is a scan flip-flop in the circuit under test, 303 is a scan path in which the scan flip-flop 302 is configured in a chain, and 304 is a scan path output response comparison. Circuit. In this embodiment, the scan path output response comparison circuit 304 includes not only the final output of each scan path 303 as in the first and second embodiments but also the flip-flops 302 at each stage on the scan path 303. The output value of the flip-flop 302 at each stage on the scan path 303 is compared, and if there is a scan flip-flop 302 that outputs a different output value, a test end signal is generated. The

  As described above, according to the present embodiment, since the scan path output response comparison can be performed for the flip-flops 302 at each stage on the scan path 303, not only the test whether there is a failure in the scan path 303, It is possible to specify which stage of the flip-flop 302 on the scan path 303 has a fault.

(Embodiment 4)
FIG. 4 is a diagram showing a basic configuration in the fourth embodiment (corresponding to claim 4) of the present invention. 4, 400 is a pattern generator, 401 is an output response compressor, 402 is a scan flip-flop in the circuit under test, 403 is a scan path in which the scan flip-flop 402 is configured in a chain, and 404 is a scan path output response comparison. A circuit 405 is a scan path in which scan flip-flops 406 for recording the output response comparison result of the scan path 403 are configured in a chain shape. In this embodiment, an output response comparison scan path 405 is added to the third embodiment.

  An operation for detecting a failure in the scan path 405 in the present embodiment will be described below. The result of comparing the output responses of the flip-flops 402 at each stage on the scan path 403 as in the third embodiment is stored in the flip-flops 406 of the output response comparison scan path 405. Since the output response comparison scan path 405 is configured in a chain, the stored comparison result is transferred to the final output signal line of the output response comparison scan path 405 by performing a shift operation of the output response comparison scan path 405. Propagated one after another. As a result, if the value of the final output signal line at each time during the shift operation is observed, the comparison result of the scan flip-flop 406 at each stage can be observed.

  As described above, according to the present embodiment, the output response comparison result for the flip-flop 402 at each stage on the scan path 403 is stored in the output response comparison flip-flop 406. Further, these output response comparison flip-flops 406 are configured in a chain shape, and by shifting the value of each flip-flop 406 on the chain, the output response comparison results can be observed only with one output terminal. Is possible. Thus, it is possible to inspect each scan flip-flop 402 on the scan path 403 to be inspected for a failure while minimizing an increase in the number of external output terminals for observing the output of the scan path output response comparison circuit 404. Can do.

  The built-in self-inspection circuit according to the present invention has a scan path failure detection function, and when the test pattern application itself cannot be normally performed, the test is immediately terminated, so that the test can be continued unnecessarily. This is useful as a semiconductor integrated circuit inspection circuit that can be prevented. It can also be applied to applications such as failure diagnosis of semiconductor integrated circuits.

FIG. 2 is a block diagram showing a basic configuration of a built-in self-test circuit in the first embodiment of the invention corresponding to claim 1. It is a block diagram which shows the basic composition of the built-in self-test circuit in 2nd Embodiment of the invention corresponding to Claim 2. It is a block diagram which shows the basic composition of the built-in self test circuit in the 3rd Embodiment of the invention corresponding to Claim 3. It is a block diagram which shows the basic composition of the built-in self test circuit in 4th Embodiment of the invention corresponding to Claim 4.

Explanation of symbols

100,200,300,400 pattern generator
101,201,301,401 Output response compressor
102,202,302,402 Scan flip-flop
103,203,303,403 Scan campus
104,204,304,404 Scan campus output response comparison circuit
205 Test end signal generator

Claims (4)

  A built-in self-test circuit comprising a plurality of scan paths for performing a test, a pattern generator for supplying a test pattern to the scan path, and an output response compressor for storing an output response from the scan path. A built-in self-test circuit comprising scan path comparison means for comparing output responses between the plurality of scan paths.   The built-in self-test circuit according to claim 1, wherein the scan path comparison means uses the comparison result as a test end signal.   3. The built-in self-test according to claim 1, wherein the plurality of scan paths have a plurality of stages of flip-flops, and the scan path comparison means compares the output responses of the flip-flops of each stage existing on the scan path. circuit. 4. The built-in self-test circuit according to claim 3, wherein the scan path comparison means stores the comparison result output value in a plurality of flip-flops configured in a chain.

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