KR20070038255A - Circuit for merged data test and method for test thereof - Google Patents

Abstract

A merge data test circuit of a semiconductor memory device is disclosed. Such a merge data test circuit includes a register unit for storing merge data to be used for a test for determining a pass or fail of the memory device, and a merge data applying unit for combining and applying merge data stored in the register unit to the memory device. And a merge data comparison unit for comparing merged data stored in the register unit with data read from the memory device. Thus, the present invention provides an improved test circuit of the semiconductor memory device and a test method thereof, thereby improving test coverage by solving a problem in which the format of input or output data cannot be freely combined by a user in a merge data test. Has an effect.

Test, merge, MDQ, register, buffer

Description

Circuit for merged data test and method for test

1 is a block diagram for explaining an example of such a conventional MDQ test.

FIG. 2 is a detailed configuration diagram showing an example of the MDQ test circuit in FIG. 1. FIG.

Figure 3 is a schematic diagram showing an MDQ test circuit according to an embodiment of the present invention.

4 is a detailed configuration diagram of the MDQ test circuit of FIG.

<Description of the symbols for the main parts of the drawings>

Dn, D0 ~ D1: Test pin 30: Merge data applying unit

IB100 ~ IB108: Input buffer TC: Test cell

LAT, LAT100 ~ LAT108: Latch section 32: Merged data comparison section

OB: Output buffer section Qn, Q0 to Q8: Output buffer section

XOR0 to XOR8, XOR10 to XOR18: Exclusive-OR gate

XNOR0: Exclusive Negative Gate

The present invention relates to a semiconductor memory device, and more particularly, to a test circuit and a test method of a semiconductor memory device.

Testing processes for semiconductor integrated circuit devices, especially semiconductor memory devices, include electrical die sorting (EDS) tests to find defective chips in the wafer state before starting the assembly process, and thermal and electrical stress on the device to pre-detect initial defects. Burn-In testing, reliability testing such as T / C (Temperature Cycling) and Pressure Cooker Test (PCT) to verify the reliability of the assembled semiconductor memory device. There is a final production test that checks all electrical characteristics to see if the device is functioning and working, and a quality assurance test to verify that the device has the specifications or quality the customer wants before shipping the final product.

In these test processes, burn-in tests apply high voltages to the semiconductor memory device, and then input specific pins to the semiconductor memory device through the input pins according to predetermined test patterns to verify that the semiconductor memory device is operating properly at high and low temperatures. When data is written and read through the data output pin of the semiconductor memory device, the written data is first outputted correctly. If any data is output different from the original written data, it is regarded as defective.

Data stored in a memory cell of the semiconductor memory device is transferred to a pad of the semiconductor memory device through data bus lines of the semiconductor memory device, or data input to the pad is a memory cell array. Is passed to. The data bus line includes a local I / O line and a global I / O line. Data output from the memory cell array is transferred to the global I / O line through the local I / O line, and to the pad through the global I / O line. A circuit for testing the function of the memory cell array by merging data transmitted through the global I / O line is a merged data (MDQ) test circuit.

In other words, if there are many input / output terminals of a semiconductor memory device, the I / O terminal of the test board must be connected to the input / output terminal of the device one by one, which is necessary for burn-in test using a tester having a limited I / O terminal. It will take longer. Therefore, the concept introduced to shorten the test time is the MDQ test method.

The MDQ test method writes the same data to a semiconductor memory device, and then outputs a plurality of output data coming out through a plurality of DQ terminals only through one DQ terminal, and outputs a value different from other output data among the plurality of output data. If there is data, the device detects this and treats the device as defective. As such, the MDQ test method overcomes the limitation of the tester channel by the number of pins by reducing the number of DQ pins, and enables multi parallel test.

1 is a block diagram for explaining an example of such a conventional MDQ test, Figure 2 is a detailed configuration diagram showing an example of the MDQ test circuit in FIG.

First, referring to FIG. 1, a data receiver DR, an input buffer unit IB, a test cell TC, a latch unit LAT, and an output buffer unit OB are illustrated.

The data receiver DR receives an MDQ test input signal MDQ_IN and converts the MDQ test input signal MDQ_IN to a level required for a test.

The input buffer unit IB receives and buffers the MDQ test input signal MDQ_IN of the converted level from the data receiving unit DR, and applies the buffer to the memory cell TC in the semiconductor memory device under test.

Data written to the test memory cell TC is read by the latch unit LAT, applied to the output buffer unit OB, and then buffered and output as the MDQ test output signal MDQ_OUT. The MDQ test output signal MDQ_OUT is read to determine whether the test memory cell TC passes or fails.

Looking at this in more detail with reference to Figure 2 as follows.

When the MDQ start signal MDQ_EN becomes the high level in the MDQ mode, the transistors TR1 to TR8 are turned on in the data receivers DR1 to DR7 connected to the tester data input pins D1 to D8, respectively, so that the low level signals are turned on. Is applied. When the MDQ test input signal (assuming that the input signal is high level) is applied to the MDQ pin D0, the output signal of the AND gate AND1 is equally applied to each of the OR gates OR1 to OR8. .

The signals applied to the respective OR gates OR1 to OR8 are applied to the respective input buffer parts IB1 to IB8, buffered, and input to the memory cells to be tested. Thus, data is written to the memory cell under test.

In the case of reading the memory cell under test, when the MDQ start signal MDQ_EN is applied to the output buffer units OB1 to OB8, the signal inverted by the inverter INV1 is applied to the output buffer units OB1 to OB8. The output buffer units OB1 to OB8 are disabled. The data stored in the memory cell is latched by the latches LAT0 to LAT8 and then input to XNOR1, negatively multiplied, and then output to the MDQ output pin Q0 to pass or fail the memory cell. It is determined whether or not.

As described above, in the conventional merge data test method, a format of input or output data cannot be freely combined by a user during the merge data test, and the test can only be performed in a fixed format, so that the test coverage can be tested. Has a problem.

Accordingly, an object of the present invention is to provide a merge data test circuit of a semiconductor memory device and a test method therefor for improving the disadvantage that a format of input or output data cannot be freely combined by a user during a merge data test.

Another object of the present invention is to provide a merge data test circuit and a test method thereof of a semiconductor memory device for improving test coverage.

According to an aspect of the present invention, there is provided a merge data test circuit of a semiconductor memory device including: a register unit for storing merge data to be used in a test for determining a pass or fail of the memory device; A merge data applying unit for combining the merge data stored in the register unit and applying the combined data to the memory device; And a merge data comparison unit for comparing merged data stored in the register unit with data read from the memory device.

Here, the register unit preferably applies merged data stored in response to a merge data test start signal to the merge data applying unit.

The merge data applying unit may also receive a merge signal stored in the register unit and a first signal applied to an input pin to perform a logic operation, and apply a first exclusive logical sum gate group to apply the logic operation result to the memory device. It may be provided.

The merge data applying unit may receive a merge signal stored in the register unit and a second signal which is a complement signal of the first signal, perform a logic operation, and apply the logic operation result to the memory device. And a first exclusive OR gate group.

The apparatus may further include an input buffer unit for receiving the logic operation result and applying a buffered signal to the memory device.

The merge data comparison unit may further include: a second exclusive OR gate group for receiving data read and latched from the memory device and merge data stored in the register unit; And a negative exclusive OR gate for receiving a logical operation result of the second exclusive OR gate group, performing a negative exclusive OR operation, and outputting a result signal.

The apparatus may further include an output buffer unit for receiving and buffering the operation result signal of the negative exclusive OR gate and applying the result to the output pin.

According to an aspect of the present invention, there is provided a method of testing merge data of a semiconductor memory device, the method including: storing merge data to be used in a test for determining a pass or fail of the memory device; Applying the merged data and a signal applied to a test signal input pin to the memory device; And comparing the merged data with data read from the memory device.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Since the descriptions in the following embodiments are merely illustrated and limited by way of example and without intention other than the intention of a person having ordinary knowledge in the art to which the present invention pertains more thorough understanding of the present invention, It should not be used to limit the scope.

3 is a schematic view showing an MDQ test circuit according to an embodiment of the present invention, Figure 4 is a detailed configuration of the MDQ test circuit of FIG.

First, referring to FIG. 3, a merge data test circuit for testing a semiconductor memory device includes a register unit REG, a merge data applying unit 30, and a merge data comparison unit 32.

The register part REG is a part for storing merged data to be used in a merge test for determining a pass or a fail of the memory device, and the merged data applying unit 30 The merged data comparison unit 32 is a portion for combining and applying merged data stored in the register unit REG to the memory device, and the merged data comparator 32 reads data read from the memory device and the register unit REG. This is to compare the saved merged data.

When the merge data test start signal (or MDQ enable signal) MDQ_EN is applied, the register unit REG applies the stored merge data to the merge data applying unit 30 in response thereto. In addition, the first signal MDQ_IN applied to the data input pin Dn is also applied to the merge data applying unit 30.

After the data is written to the test cell TC by the input buffer unit IB to the test cell TC, the data compared by the merge data comparison unit 32 is output to the output buffer unit ( Buffered by OB and applied to data output pin Qn.

With reference to FIG. 4, it is as follows.

The merge data applying unit 30 includes first exclusive OR gate groups XOR0 to XOR8. The first signal MDQ_IN applied to the MDQ pin D0, which is a merge data test pin among the data input pins, is applied to each exclusive logic gate constituting the first exclusive OR gate group. In addition, merge data of a specific pattern stored in the register unit REG is applied to the merge data applying unit 30. The merge data applying unit 30 receives a merge data stored in the register unit REG and a first signal MDQ_IN applied to a data input pin to perform a logic operation, and outputs the logic operation result of the memory device. It is applied to the test cell TC.

The calculation result by the merge data applying unit 30 is buffered by the input buffer units IB100 to IB108 and then written to the test cell TC.

In this case, the signal applied to the MDQ pin D0 and applied to the merge data applying unit 30 may be a second signal which is a complement signal of the first signal. Thus, the MDQ test can be performed by reducing the constraint of the I / O format without a separate command.

The merge data comparison unit 32 includes second exclusive OR gate groups XOR10 to XOR18 and negative exclusive OR gates XNOR0.

The second exclusive OR gate group XOR10 to XOR18 is read from a test cell of the memory device, and then receives data latched by the latch units LAT100 to LAT108 and merge data stored in the register unit REG. Compare them.

The negative exclusive OR gate XNOR0 receives a logical operation result of the second exclusive OR gate groups XOR10 to XOR18, performs an NOR operation, and outputs a result signal. The operation result signal of the negative exclusive OR gate XNOR0 is received and buffered by the output buffer unit OB100, and the result is output to the data output pin Q0. Although not specifically illustrated, the output buffer unit connected to the data output pins Q1 to Q8 is disabled by the MDQ start signal MDQ_EN, which is the same as the conventional technique described with reference to FIGS. 1 to 2.

For example, after entering a merge data test mode, specific data (for example, data is referred to as "1011") to be used as a format of merge data is latched in the register section REG and stored therein. The merge data applying unit 30 corresponding to the data input pins connected to the data (as shown in FIG. 4), A0 of the register unit REG has XOR0 corresponding to the data input pin Q0 and A1 of the register unit REG. XOR1 corresponding to the input pin Q1 is connected to the XOR8 corresponding to the input pin Q8 to A8 of the register section REG), and data stored in the register section is applied to the MDQ input pin D0. When data of (for example, data is referred to as "0") is applied, data of the pattern (data "1011") stored in the register is written to the test cell TC. If the complement data (data "1") of the data is applied to the MDQ input pin (D0), the complement data (data "0100") of the data stored in the register is written to the test cell (TC). do. In the case where the data written to the test cell TC is read, a similar method is performed.

The data stored in the register REG can be freely changed, and the path or fail of the semiconductor memory device can be distinguished by using the complementary data without using a separate register using data applied to the MDQ input pin Q0. It becomes possible.

A merge data test method of a semiconductor memory device according to an embodiment of the present invention will now be described with reference to FIGS. 3 to 4.

In a merge data test method of a semiconductor memory device according to an embodiment of the present disclosure, storing merge data to be used for a test for determining a pass or fail of the memory device in a register unit REG in a tester, and a test signal input pin. And applying the merged data and the signal applied to (D0) to the memory device, and comparing the merged data with data read from the memory device.

Thus, the present invention can freely implement the format of the input / output data in the same test pattern in the merge data test, thereby increasing the test coverage for the fail of the semiconductor memory device related to the format of the input / output data.

The merge data test circuit and test method thereof of the semiconductor memory device according to the present invention can be designed and applied in various ways without departing from the basic principles of the present invention. It will be obvious to one.

As described above, the present invention provides an improved test circuit of the semiconductor memory device and a test method thereof, thereby solving the problem that a format of input or output data cannot be freely combined by a user in a merge data test, thereby solving test coverage. Has the effect of raising.

Claims (8)

In a merge data test circuit of a semiconductor memory device: A register unit for storing merged data to be used in a test for determining a pass or a fail of the memory device; A merge data applying unit for combining the merge data stored in the register unit and applying the combined data to the memory device; And And a merge data comparison unit for comparing merged data stored in the register unit with data read from the memory device. The method of claim 1, And the register unit applies merged data stored in response to a merge data test start signal to the merge data applying unit. The method of claim 2, The merge data applying unit includes a first exclusive logical sum gate group for receiving a merge data stored in the register unit and a first signal applied to an input pin and performing a logic operation, and applying the logic operation result to the memory device. Merging data test circuit characterized in that. The method of claim 3, The merge data applying unit receives a merge data stored in the register unit and a second signal that is a complement signal of the first signal, performs a logic operation, and applies a first exclusive value to apply the logic operation result to the memory device. A merged data test circuit comprising an AND gate group. The method according to claim 3 or 4, And an input buffer unit for receiving the logic operation result and applying a buffered signal to the memory device. The method of claim 1, wherein the merge data comparison unit, A second exclusive OR gate group for receiving data read and latched from the memory device and merge data stored in the register unit; And And a negative exclusive OR gate for receiving a logical operation result of the second exclusive OR gate group, performing a negative exclusive OR operation, and outputting a result signal. The method of claim 6, And an output buffer unit for receiving and buffering an operation result signal of the negative exclusive OR gate and applying the result to an output pin. In the merge data test method of a semiconductor memory device: Storing merge data in a register in a tester for use in a test for determining a pass or fail of the memory device; Applying the merged data and a signal applied to a test signal input pin to the memory device; And And comparing the merged data with data read from the memory device.

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