KR20070111563A - Circuit for parallel bit test and method by the same - Google Patents

Abstract

A parallel bit test circuit and a test method thereof are provided to improve test screen ability as shortening test time. A parallel bit test circuit tests a semiconductor memory device, by comparing output data from at least one input/output sense amplifier with expected data corresponding to the output data and then outputting the comparison result to an input/output pin. The parallel bit test circuit comprises data comparison parts(130), an expected data selection part(110), an expected data output part(102) and a data compression and result output part(140). The data comparison parts correspond to each input/output sense amplifier in order to compare the output data with the expected data. The expected data selection part generates an expected data selection signal to transfer the expected data to a corresponding data comparison part selectively. The expected data output part outputs inverted or non-inverted data to the data comparison part by receiving the expected data selection signal. The data comparison and result output part outputs a failure signal when one of comparison results in the data comparison parts is a failure.

Description

Circuit for parallel bit test and method by the same}

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram for explaining a circuit and a method for inputting data predicted in a conventional read command and comparing it with an output of an I / O sense amplifier.

2 is a timing diagram for explaining the operation of the circuit shown in FIG.

3 is a simplified block diagram of a parallel bit test circuit in accordance with an embodiment of the present invention.

4 is a timing diagram for explaining the operation of the circuit shown in FIG.

<Description of the symbols for the main parts of the drawings>

100: expected data selection unit 102: expected data output unit

110: I / O sense amplifier 120: data input multiplexer

130, 132, 134, 136: data comparator 131: exclusive OR gate

140: data compression and result output unit 142: NOR gate

144: NAND gate IN_BURST: burst lead signal

INV1, INV2: Inverter TG1, TG2: Transmission Gate

PETYPE_GEN: Expected data selection signal generator

PCLK: Internal Clock Pulse PCLKD: Delayed Internal Clock Pulse

ACT: active command WRITE: write command

READ: read command

The present invention relates to a test of a semiconductor memory device, and more particularly, to a parallel bit test circuit and a test method of a semiconductor memory device.

Testing of the semiconductor memory device proceeds to isolate the defect in the pre-shipment stage. The test of the semiconductor memory device is performed to test whether the core logic circuit inside the chip is operating normally. The core logic circuit may be a circuit including a memory cell array and a peripheral circuit thereof in a semiconductor memory device, or may be a circuit including a memory cell array and a peripheral circuit thereof in a semiconductor memory device for performing other purposes. It may be a logic circuit for a main function in another integrated circuit device for performing other purposes. In order to test the logic circuit, control signals for DQ output are input to the logic circuit, and as a result, the logic circuit is normally read by reading whether or not to pass / fail the DQ data output from the logic circuit. It is determined whether it works.

Typically, the pass / fail of the product is at the discretion of the tester. That is, the tester generates control signals including a command, an address, a test data pattern, and the like in the order programmed by the engineer, and applies the same to the product. For example, in order to test a semiconductor memory device, test data is written to a corresponding address, and data stored at the same address is read again to output DQ data.

The test then compares the DQ data output from the product with the test pattern expected by the output to determine whether the product passes or fails, and stores the address at that time. This series of test procedures allows the engineer to identify a defective product and to perform an appropriate repair process using the failed address. As one of such test methods, a parallel bit test (PBT) is well known.

Therefore, parallel bit testing, which can greatly reduce the test time, is widely applied to the test of the semiconductor memory device.

A method of compressing data that is sensed and amplified by a data input / output sense amplifier (I / O sense amplifier) in a semiconductor memory device and output to an input / output port (hereinafter referred to as I / O). A method of compressing only the output terminals of the sense amplifier by an exclusive OR is used and a method of comparing the written data with the output terminal of the I / O sense amplifier by an exclusive OR (XOR). One example of the latter is shown in FIG. 1.

That is, FIG. 1 is a conventional parallel bit test circuit and method, which is a block diagram for explaining a circuit and a method for inputting data predicted in a read command and comparing it with an output terminal of an I / O sense amplifier.

Referring to FIG. 1, a conventional parallel bit test circuit includes an I / O sense amplifier (IOSA) 10, a data input multiplexer DINMUX 20, a data comparator 30, and a data compression and result output unit 40. It is provided.

The I / O sense amplifier 10 senses and amplifies the data applied to the I / O sense amplifier 10 in an output stage after being sensed and amplified by the bit line sense amplifier in a data read path during normal operation. Serves to provide. Similarly, in the test mode, that is, the parallel bit test mode, the I / O sense amplifier 10 senses and amplifies the data applied to the I / O sense amplifier 10 after being sensed and amplified by the bit line sense amplifier. The I / O sense amplifier 10 is generally used in the form of a differential amplifier (differential amplifier). The I / O sense amplifier 10 is enabled by the control signal FRP, amplifies the data, and outputs the data to the data comparator FCOMP 30. That is, the I / O sense amplifier 10 detects and amplifies the data written and stored in the memory cell under test when a read command is applied during the test, and outputs the result signal FDO1 to the data comparator 30. The result is compared with the resultant signal FDO0 output from the data input multiplexer 20 described below.

The data input multiplexer 20 latches data written to the test target memory cell and outputs a result signal FDO0 in response to the delayed clock pulse PCLKD generated by an external clock CLK. Output to (30). That is, the result signal FDO0 is expected data (also referred to as expected data or expected data).

The data comparator 30 receives and compares the output signal FDO1 of the I / O sense amplifier 10 and the expected data FDO0 that is an output signal of the data input multiplexer 20, and then compares the result signal. (ECO0B) is provided to the data compression and result output unit 40. Although only one data comparator 30 is shown in detail, the data comparator FCOMP 32, 34, and 36 are similarly implemented. That is, the case where the number of I / O is four is illustrated. The data comparator 30 includes an exclusive OR circuit X31 that performs an exclusive OR. Thus, when the signal applied to the exclusive OR circuit 31 is the same, the result signal ECO0B is at the low level, and when it is different, the result signal ECO0B is at the high level.

The data compression and result output unit 40 outputs the NOR gate 42 and the NOR gate 42 that compress the result signals ECO0B, ECO1B, ECO2B, and ECO3B compared by the data comparison unit 30. And a NAND gate 44 to receive the signal. The NAND gate 44 is enabled by the control signals EPBT and FRPSC to output the output signal FDIOB to the final output terminal. Here, of course, the output signal FDIOB is transmitted to the output pin DQ pin via an output driver.

FIG. 2 is a timing diagram for describing an operation of the circuit diagram shown in FIG. 1.

Referring to FIG. 2, an active command ACT, a read command READ, or the like is applied in response to the external clock CLK, and the data D expected in accordance with the read command READ is a data input multiplexer (FIG. 1, DINMUX). Thus, in response to the delayed clock pulse (PCLKD in FIG. 1), the expected data D is delayed to output the resultant signal (FDO0 in FIG. 1) to the data comparator (30 in FIG. 1). After the comparison in the data comparator (30 in FIG. 1), the result signal Q is passed through the data compression and result output unit (40 in FIG. 1) and an output driver (not shown). )

However, the parallel bit test circuit and test method having the structure and operation shown in FIGS. 1 and 2 have a problem in that a burst read operation is impossible because data to be compared, that is, expected data is fixed and cannot be changed. .

Therefore, there is an urgent need for parallel bit test circuits and test methods to further increase test screen ability while further reducing test time.

It is therefore an object of the present invention to provide an improved parallel bit test circuit and test method for solving the problem that a burst read operation, which is a disadvantage of the conventional parallel bit test circuit and test method, is impossible.

Another object of the present invention is to provide a parallel bit test circuit and a test method which can increase test screen capability while further reducing test time.

According to an aspect of the present invention for achieving the above objects, by comparing the output data from at least one input and output sensor amplifier and the expected data corresponding to the output data to the input and output pins to improve the good or bad of the semiconductor memory device The parallel bit test circuit for testing may include: data comparison units corresponding to respective input / output sensor amplifiers for comparing the output data with the expected data; An expected data selector for generating an expected data selection signal for selectively transmitting the expected data to a corresponding data comparator; An expected data output unit configured to receive the expected data selection signal and output inverted or non-inverted data to the data comparison unit; And a data compression and result output unit for outputting a result signal relating to a failure if any one of the comparison results in the data comparison units is defective.

Here, the expected data selector receives the burst read signal to generate the expected data select signal in response to an internal clock pulse and a test mode select signal generated by an external clock, and the expected data output unit, A first transfer gate turned on when the expected data selection signal is in a first state and turned off in a second state; And a second transmission gate turned on when the expected data selection signal is in the second state and turned off when the expected data selection signal is in the second state.

The first transfer gate may output the expected data to the data comparator in a non-inverted state, and the second transfer gate may invert the expected data and output the inverted data to the data comparator.

In addition, the first state may be at a logic high level, the second state may be at a logic low level, and the burst read signal may be applied from an external pad.

To test the good or bad of the semiconductor memory device by comparing the output data from at least one input and output sensor amplifier and the expected data corresponding to the output data according to an aspect of the present invention to output to the input and output pins A parallel bit test method for performing the steps of: writing a data pattern to memory cells to be tested; Reading data stored in the memory cells and applying the data to the corresponding data comparing unit to perform an exclusive OR operation with the expected data; Controlled by a burst read signal applied from an external pad to cause the expected data to be applied to the data comparator in an inverted or non-inverted state; And receiving all of the comparison results from the data comparison units and outputting a result signal related thereto if one of them is defective.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The accompanying drawings and the following description are by way of example only and are intended to assist those of ordinary skill in the art to understand the present invention. Accordingly, the following descriptions should not be used to limit the scope of the invention.

3 is a simplified block diagram of a parallel bit test circuit according to an embodiment of the present invention.

Referring to FIG. 3, the parallel bit test circuit includes an input / output sense amplifier (IOSA) 110, a data input multiplexer DINMUX 120, a predictive data selector 100, a predictive data output unit 102, and a data comparator ( 130) and data compression and result output unit 140.

The I / O sense amplifier 110 serves to sense and amplify the data during the normal operation and provide it to the output terminal. Similarly in parallel bit test mode. The I / O sense amplifier 110 is enabled by a control signal FRP, amplifies the data, and outputs the data to the data comparator FCOMP 130. That is, the I / O sense amplifier 110 detects and amplifies the data written and stored in the test target memory cell when the read command is applied in the parallel bit test mode, and the resultant signal FDO1 is detected as the result of the data comparator ( 130 to be compared with the resultant signal FDO0 output from the data input multiplexer 120 through the expected data output unit 102.

The data input multiplexer 120 latches data written to the test target memory cell and outputs data expected in response to the delayed clock pulse PCLKD generated by an external clock CLK. 102).

The data comparator 130 outputs an output signal FDO1 of the I / O sense amplifier 110 and a result signal FDO0 output from the data input multiplexer 120 through the expected data output unit 102. After receiving and comparing, the comparison result signal ECO0B is provided to the data compression and result output unit 140. As described above, only one data comparison unit 310 is described in detail, but other data comparison units 32, 34, and 36 are similarly implemented. That is, only the case where the number of I / O is 4 is shown as an example. The data comparator 130 includes an exclusive OR circuit 131 that performs an exclusive OR. Thus, when the signal applied to the exclusive OR circuit 131 is the same, the result signal ECO0B is at the low level, and when it is different, the result signal ECO0B is at the high level.

The data compression and result output unit 140 includes a NOR gate 142 and the NOR that compress the result signals ECO0B, ECO1B, ECO2B, and ECO3B compared by the data comparison units 130, 132, 134, and 136. And a NAND gate 144 that receives the output of the gator 142. The NAND gate 144 is enabled by the control signals EPBT and FRPSC to output the output signal FDIOB to the output terminal. Thus, the data compression and result output unit 140 outputs a result signal regarding the failure when any one of the comparison results in the data comparison units 130, 132, 134, and 136 is defective. Therefore, the output signal FDIOB of the data compression and result output unit 140 may be a result signal for good or a result signal for bad.

The expected data selection unit 100 generates an expected data selection signal PDTYPE for selectively transmitting the expected data to a corresponding data comparison unit 130 among the data comparison units. The expected data selector 100 receives the burst read signal IN_BURST and responds to the internal clock pulse PCLK and the test mode selection signal MOD_SIG generated by the external clock CLK. The data selection signal PDTYPE may be generated. Thus, whether the signal output from the data input multiplexer 120 is inverted and applied to the data comparator 130 by the expected data selection signal PDTYPE, or the data comparator 130 is in a non-inverted state. You can choose whether to apply

In a package state, the burst read signal IN_BURST may be applied from an external pad. The external pad may be newly added, but may be an existing pad, for example, a CKE pad or a DQM pad.

The expected data output unit 102 receives the expected data selection signal PDTYPE and outputs inverted or non-inverted data to the data comparison unit 130. The expected data output unit 102 includes a first transfer gate TG1, a second transfer gate TG2, a first inverter INV1, and a second inverter INV2.

The first transfer gate TG1 may be turned on when the expected data selection signal PDTYPE is in a first state and turned off when in a second state. On the contrary, the second transmission gate TG2 may be turned on when the expected data selection signal PDTYPE is in the second state and turned off when the first data gate is in the first state. Thus, the first transmission gate TG1 may output the expected data, which is an output signal of the data input multiplexer 120, to the data comparison unit 130 in a non-inverted state, and the second transmission gate TG2. May invert the expected data and output the inverted data to the data comparator.

For example, assuming that the first state is a logic high level and the second state is a logic low level, when the expected data selection signal PDTYPE is at the high level, the first transfer gate TG1 is turned on. The second transfer gate TG2 is turned off. Accordingly, the expected data is not inverted and is applied to the data comparator 130 to perform a comparison operation with the output data FDO1 of the I / O sense amplifier. If the first state is a logic low level and the second state is a logic high level, the first transfer gate TG1 is turned off and the second transfer gate TG2 is turned on. The expected data is inverted by the first inverter INV1 and applied to the data comparator 130, and then compared with the output data FDO1 of the I / O sense amplifier.

FIG. 4 is a timing diagram for describing an operation of the circuit shown in FIG. 3.

Referring to FIG. 4, an operation timing diagram when CAS Latency (CL) is 3 and Burst Length (BL) is 4 is illustrated.

In the command CMD, the write command WRITE is applied after the active command ACT, and 0101 (since BL is 4) is applied to the DQ pin. Thus, the 0101 is written to the memory cells and a read command READ is applied after four cycles. Although the timing diagram of the data FDO1 output from the I / O sense amplifier 110 of FIG. 3 is not shown, the timing diagram of the data FDO0 output from the expected data output unit is generally similar to the data FDO0.

When the burst read signal IN_BURST is applied from the external pad, the expected data selector 100 (in FIG. 3) generates an expected data select signal PDTYPE corresponding thereto.

As described with reference to FIG. 3, when the expected data selection signal PDTYPE is at a high level, the output signal FDO1 of the I / O sense amplifier and the expected data FDO0 are equally compared. That is, the expected data FDO0 is a state in which a signal output from the data input multiplexer 120 is not inverted. Then, in order to compare the next data 1, it must be inverted. The characteristic of the exclusive OR operation is to output a low level signal when the two inputs are the same and a high level signal when the two inputs are different. The level signal ECO0B is output from the exclusive-OR operator (131 in FIG. 3). If all is good, all of the data comparison units 130, 132, 134, and 136 output low level signals.

Therefore, since all outputs of the data comparison units 130, 132, 134, and 136 are input to the NOR gate 142 of the data compression and result output unit 140, the data comparison units 130, 132, 134, and 136. If all of the outputs are low level, the NOR gate 142 outputs a high level signal. Therefore, this case is a pass, and in other cases, it is a fail.

As described above, the parallel bit test circuit according to the present invention includes an expected data output unit and an expected data selector capable of inverting expected data, thereby enabling burst read operation.

The parallel bit test method according to the present invention can be described with reference to FIGS. 3 and 4.

According to the present invention, in the parallel bit test method for testing the good or bad of the semiconductor memory device by comparing the output data from at least one input and output sensor amplifier and the expected data corresponding to the output data to the input and output pins, Writing a predetermined data pattern (0101 in FIG. 4) to the memory cells to be tested; corresponding to one or more data comparison units for reading data stored in the memory cells after writing and performing an exclusive OR operation with the expected data; Applying to the data comparator 130 (FIG. 3), controlled by a burst read signal IN_BURST applied from an external pad (e.g., CKE, DQM, etc.) so that the expected data is stored in the data comparator (FIG. 3). 130 to be applied in an inverted or non-inverted state, and the data comparison units ( Receiving all the comparison results in 130, 132, 134, 136 of Figure 3, and if any one of them is characterized in that it comprises the step of outputting the result signal to the output terminal.

Thus, the parallel bit test method according to the present invention can invert expected data, which is data written to a memory cell to be tested, thereby enabling burst read operation, which was difficult to implement in the conventional parallel bit test method, while reducing test time. It also has the effect of improving screen capabilities.

The parallel bit test circuit and the test method according to the present invention are not limited to the above embodiments, and can be variously designed and applied without departing from the basic principles of the present invention. It will be obvious to those who have.

As described above, the present invention provides an improved parallel bit test circuit and test method, which has the effect of solving the problem that a burst read operation is impossible in a conventional test. Thus, the present invention has the effect of increasing the test screen ability while further shortening the test time.

Claims (8)

A parallel bit test circuit for testing good or bad semiconductor memory devices by comparing output data from at least one input / output sensor amplifier with expected data corresponding to the output data and outputting the comparison result to the input / output pins: Data comparison units corresponding to respective input / output sensor amplifiers for comparing the output data with the expected data; An expected data selector for generating an expected data selection signal for selectively transmitting the expected data to a corresponding data comparator; An expected data output unit configured to receive the expected data selection signal and output inverted or non-inverted data to the data comparison unit; And And a data compression and result output unit for outputting a result signal relating to a failure if any one of the comparison results in the data comparison units is defective. The method of claim 1, And the expected data selector receives the burst read signal to generate the expected data select signal in response to an internal clock pulse generated by an external clock and a test mode select signal. The method of claim 2, wherein the expected data output unit, A first transfer gate turned on when the expected data selection signal is in a first state and turned off in a second state; And And a second transmission gate turned on when the expected data selection signal is in a second state and turned off when the expected data selection signal is in a second state. The method of claim 3, And the first transmission gate outputs the expected data to the data comparator in a non-inverted state. The method of claim 3, And the second transfer gate inverts the expected data and outputs the expected data to the data comparator. The method of claim 3, And said first state is a logic high level and said second state is a logic low level. The method of claim 2, And the burst read signal is applied from an external pad. A parallel bit test method for testing good or bad semiconductor memory devices by comparing output data from at least one input / output sensor amplifier and expected data corresponding to the output data and outputting the comparison result to the input / output pins: Writing a data pattern to the memory cells to be tested; Reading data stored in the memory cells and applying the data to the corresponding data comparing unit to perform an exclusive OR operation with the expected data; Controlled by a burst read signal applied from an external pad to cause the expected data to be applied to the data comparator in an inverted or non-inverted state; And And receiving all the comparison results from the data comparison units, and outputting a result signal to the output terminal if any one of them is defective.

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