KR20070104165A - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device is provided to save test time and cost by performing test all data paths regardless of an untested data input/output path by screening a defect to the data path of the semiconductor memory device of test target. A semiconductor memory device comprises a plurality of data input/output pads. A plurality of input circuits(121) generates write data to a plurality of write data lines by processing input data applied to a plurality of data input/output pads during a normal write operation and a test write operation. A test input data generation part(100) generates test input data to a plurality of data input lines between the data input/output pads and the input circuits during the test write operation. A plurality of first phase comparison parts compares phases of signals of adjacent lines of the write data lines during the test write operation. A memory cell array stores the write data during the normal write operation, and generates read data to a plurality of read data lines during a normal read operation. A plurality of input/output sense amplifiers(131) amplifies read data during the normal read operation, and outputs amplified read data to a plurality of signal lines. A test output data generation part(400) generates test output data to the plurality of signal lines during the test read operation. A plurality of output circuits(133) generates output data to a plurality of data output lines connected to the data input/output pads by processing the test output data during the normal read operation and the test read operation. A plurality of second phase comparison parts compares phases of signals between adjacent lines of the plurality of data output lines during the test read operation.

Description

Semiconductor memory device

1 is a block diagram of detecting a defect in a data path of a conventional semiconductor memory device.

2 is a block diagram for detecting a defect in a data path of a semiconductor memory device of the present invention.

3 is a block diagram for generating a test mode control signal of the present invention.

4 is a diagram illustrating values of a test data level check and a phase comparison control signal according to a combination of test mode control signals in the semiconductor memory device of the present invention.

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of testing all unchecked untested data write / lead paths generated when testing using the merged data request test mode. .

As the integration of semiconductor memory devices increases, the technology for testing has evolved to reduce test costs and test time. The semiconductor memory device is tested after completion of the manufacturing process, and if it is rejected, a process related to wafer testing is found to analyze the cause of the defect, and the defect is analyzed and reflected in the manufacturing process to manufacture a more complete semiconductor memory device. Doing. The purpose of such a wafer test is to find defect chips before assembly and to reduce the effort and time spent in the semiconductor manufacturing process.

In general, semiconductor memory test means that the test engineer applies instructions, addresses, and data types programmed by the circuit design engineer to the tester, and operates the test target semiconductor memory in the order specified in the program. The test pass or test fail is determined depending on whether or not it is.

However, as the degree of integration of semiconductor memory devices increases and the minimum line width of the chip gradually decreases, semiconductor memory defects occur in many cases. As a result, the types of items to be tested are diversified and test time is greatly increased, which in turn has a great influence on the manufacturing cost of semiconductor memories.

As described above, a semiconductor memory device having a plurality of input / output pads uses a merged data request (MDQ) test mode to reduce test costs. In this mode, 64 test data line mode semiconductor memory devices can be tested in 1 test data line mode, and the number of input / output pins of the test equipment can be dramatically reduced, thereby enabling multi-parameter test. Therefore, in general, most semiconductor memory devices perform various types of tests in the merged data request (MDQ) test mode as described above.

However, if the semiconductor memory device is tested using the merged data request (MDQ) test mode, an unchecked untested input / output pad and a corresponding untested data write / lead path are generated. Explain.

In general, when the data write signal of the semiconductor memory is input, the incoming data is loaded on the write data line and the write data bar line, in which the inverted value and the normal value are a pair of data lines between the input circuit and the memory cell array. The signal is input between the memory cell array and the input / output sense amplifier and the values of the read data line and the data output bar line are input to the input / output sense amplifier and output the result through the output circuit. Therefore, data input / output lines, input / output sense amplifiers, and output circuits are included to detect a failure of the data write / read path.

1 is a block diagram of detecting defects in a data write and a read path of a conventional semiconductor memory device. A semiconductor memory device having four external data input / output pads and accessing a memory cell array with 4 bits for input / output of data is an example. It is shown as.

As shown in FIG. 1, a conventional semiconductor memory device may store data from a memory cell array 110 storing data, data input / output pads DQ1 to DQ4, and data input / output pads DQ1 to DQ4 during a data write operation. A data write circuit 120 that receives and writes data to the memory cell array 110, and a data read that reads data from the memory cell array 110 and transmits the data to the data input / output pads DQ1 to DQ4 during a data read operation. It consists of a circuit 130.

In addition, the data write circuit 120 receives 4 bits from the data input / output pads DQ1 to DQ4 and transfers data to the input circuit 121 in the normal mode under the control of the test mode control signal, and demultiplexer stage in the test mode. A first test mode selector 123 for transmitting data to the 122, a demultiplexer stage 122 for receiving 2 bits of data from the first test mode selector 123 in the test mode and outputting 4 bits; 1 is an input circuit 121 for receiving data from the test mode selection unit 123 or the demultiplexer stage 122 and writing data to the memory cell array 110.

In addition, the data read circuit 130 receives four bits from the input / output sense amplifiers 131 and the input / output sense amplifiers 131 that sense data from the memory cell array and output the amplified data, respectively, to control the test mode. The second test mode selector 134 transfers data to the output circuit 133 in the normal mode and the data to the comparator 132 in the test mode under the control of the signal, and the input / output sense amplifiers 131 in the test mode. Data received from the comparator 132, the second test mode selector 134, or the comparator 132, which receives 4-bit data, converts the 2-bit data into 2-bit data, and outputs the data to the output circuit 133. The output circuit 133 transmits to the fields DQ1 to DQ4.

Here, the light and lead paths are limited to four paths for better understanding. However, the present invention can be applied to the paths of 64 or more light and lead paths in practical applications.

The test of the conventional semiconductor memory device shown in FIG. 1 is as follows.

Data of 1 or 0 is input from the test equipment to the first test mode selector 123 by 2 bits through the odd-numbered data input / output pads DQ1 and DQ3. The input 2-bit data is transferred to the demultiplexer stage 122 under the control of the test mode control signal, that is, the phase comparison control signal LCOM indicating the test mode, and is converted into 4-bit data in the demultiplexer stage 122 and input. Data is written to the memory cell array 110 through the circuit 121.

The data written to the memory cell array 110 is a phase comparison control signal LCOM indicating that the data is written in the test mode as in the data write path through the input / output sense amplifiers 131-1 to 131-4 by 4 bits in the data read path. Is transmitted to the comparator 132 according to the control. Each of the comparators 132-1 to 132-2 constituting the comparator 132 outputs 1 when the two inputs are the same, and outputs 0 when the two inputs are different. The comparator 132 receives 4 bits of data, generates 2 bits of data, and outputs the odd bits of data input / output pads DQ1 and DQ3 through the output circuit 131. If the data output to the data input / output pads DQ1 and DQ3 is the same as the data input to the data input / output pads DQ1 and DQ3 at the time of data writing, the semiconductor device is judged to be good, otherwise the semiconductor device is bad. Judging by

However, when the semiconductor memory device is tested using the conventional merged data request (MDQ) test mode as described above, the test equipment 140 performs comparison of the comparison result data input / output through only the data input / output pads DQ1 and DQ3. The state is determined to determine the address of the defective memory cells, and the remaining data input / output pads DQ2 and DQ4 are left unchecked.

However, as memory process technology advances, as memory chips become denser and operate faster, testing of faults that cause malfunctions according to the state of neighboring cells becomes more complicated and time consuming. Since the test time will soon lead to the test cost, reducing this is very important. Using the conventional merged data request (MDQ) test mode, the untested data input / output pads (DQ2) not checked as shown in FIG. , DQ4) occurs, and an additional effort and time required to repeat another test process is required to test whether the data write / lead path connected to the data input / output pads is defective.

That is, when the semiconductor memory device is tested using the merged data request (MDQ) test mode to detect defects in the paths of the write and read paths of the conventional semiconductor memory device, the number of input / output pins of the test equipment can be reduced. The path from the write data lines DIL2 and DIL4 or the write data bar lines DIBL2 and DIBL4 to the data input / output pads DQ2 and DQ4, which allows for multi-parameter testing but is an unchecked untested write path. A path from the data input / output pads DQ2 and DQ4 that are the untested read paths to the memory cell array 110 is generated. To test for defects on these unchecked untested data write / lead paths, additional effort and time was required to repeat another test procedure.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that can test all data paths without untested data input / output paths by screening defects in the data paths for the semiconductor memory device under test, thereby saving test time and cost. have.

The semiconductor memory device of the present invention for achieving the above object is processed into a plurality of write data lines by processing the input data applied to the plurality of data input and output pads, the normal write operation and the test write operation in the plurality of data input and output pads A plurality of input circuits for generating write data, a test input data generator for generating test input data on a plurality of data input lines between the plurality of data input / output pads and the plurality of input circuits during a test write operation, and a test A plurality of first phase comparators for comparing phases of signals between adjacent lines of the plurality of write data lines in a write operation, storing write data in a normal write operation, and a plurality of read data lines in a normal read operation Memory cells that generate read data The input / output sense amplifiers may amplify read data in a normal read operation to output amplified read data into a plurality of signal lines, and generate a test output data in a plurality of signal lines in a test read operation. An output data generator, a plurality of output circuits for processing the test output data during normal read operation and the test read operation to generate output data to a plurality of data output lines connected to the plurality of data input / output pads, and a test And a plurality of second phase comparators for comparing phases of signals between adjacent lines of the plurality of data output lines during a read operation.

Hereinafter, a semiconductor memory device of the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a block diagram for detecting a defect in a data path of a semiconductor memory device of the present invention, wherein a test operates under control of a test mode control signal for an input / output terminal that cannot be tested in the configuration of the conventional semiconductor memory device shown in FIG. The input data generator 100, the write data line phase comparators 200-1 to 200-3, the test output data generator 400, and the read data line phase comparators 300-1 to 300-3 are added. It is composed.

Since the functions of each of the blocks shown in FIG. 2 are the same as the functions of the corresponding blocks shown in FIG. 1, description thereof will be omitted. Here, the test input data generator 100 and the write data line phase comparison, which is an additional block, are omitted. Only the configurations and functions of the parts 200-1 to 200-3, the test output data generator 400, and the read data line phase comparators 300-1 to 300-3 will be described.

The test input data generator 100 is positioned between each of the data input / output pads DQ1 and DQ3 and each of the first test mode selectors 123-1 and 123-2 in the data write path, and generates test output data. The unit 400 is positioned between each of the comparators 132-1 to 132-4 and the respective output circuits 133-1 to 133-4 in the data lead path, and each PMOS is connected to a power supply voltage. The transistors P1 to P4 and each of the NMOS transistors N1 to N4 having one side connected to the ground voltage are constituted by a CMOS transistor connected in series.

Meanwhile, the test mode register programs and stores various options corresponding to each of a plurality of test modes used by the semiconductor memory device. When a command for setting a specific test mode is input from an external device, the test mode register corresponds to the input command. To determine the test mode and generate a test mode setting signal that can be set to the identified test mode. In the present invention, three bits (TMRS [2: 0]) of the test mode register are used as bits for normal mode or test mode setting and bits for high level data or low level data check in the test mode. That is, TMRS [2] is used for normal mode or test mode setting, TMRS [1] is used for high level data check, and TMRS [0] is used for low level data check. It is generated by combining the mode setting signal applied through.

3 is a block diagram for generating a test mode control signal of the present invention, and includes an address latch unit 150, an instruction decoder 250, and a test mode control signal generator 350. The address latch unit 150 receives and stores the mode setting signal MA [12: 0] from the outside through the address bus A [12: 0] and outputs the result after a predetermined time elapses. The command decoder 250 Mode is controlled by receiving command signals (/ CS (Chip Select bar), / RAS (Row Address Strobe bar), / CAS (Column Address Strobe bar), / WE (Write Enable bar)) for mode selection from the outside Outputs a signal MRS, and the test mode control signal generator 350 receives the mode setting signal MA [12: 0] and the mode control signal MRS and receives a test mode control signal TMRS [2:]. 0]).

In FIG. 2, a high level check (H-CK) signal is applied to gates of the PMOS transistors P1 to P4 in the test input data generator 100 and the test output data generator 400, and the NMOS transistors N1. To low level check (L-CK) signals are applied to the gates of N4 to N4). The contacts of each of the PMOS transistors P1 to P4 and the NMOS transistors N1 to N4 are connected to the respective data input / output pads DQ1 and DQ3 and the respective first test mode selectors 123-1 to the data write path. In the contact and data lead path of 123-2, the respective comparators 132-1 and 132-2 and the second test mode selectors 134-2 and 134-4 and the respective output circuits 133-1. To 133-4), respectively.

The write data line phase comparators 200-1 to 200-3 are disposed between adjacent write data lines between the respective input circuits 121-1 to 121-4 and the memory cell array 110 in the data write path. The transfer gates TG1 to TG3 and TGB1 to TGB3 and each of the transfer gates TG1 to TG3 that are positioned to connect each of the adjacent write data lines WDL1 to WDL4 and each of the write data bar lines WDBL1 to WDBL4. And inverters INV1 to INV3 and INVB1 to INVB3 connected to the gates of the PMOS transistors TGB1 to TGB3.

The PMOS transistors of the transfer gates TG1 to TG3 respectively connect the adjacent write data lines WDL1 to WDL4 between the respective input circuits 121-1 to 121-4 and the memory cell array 110. The output signal in which the phase comparison control signal LCOM for the normal mode or the test mode setting is inverted by the inverters INV1 to INV3 is applied to the gate, and the normal mode is applied to the gate of the NMOS transistors of the transfer gates TG1 to TG3. Alternatively, the phase comparison control signal LCOM for setting the test mode is directly applied.

Similarly, the phase comparison control signal LCOM for normal mode or test mode setting is applied to the gates of the PMOS transistors of the transfer gates TGB1 to TGB3 connecting the adjacent write data bar lines WDBL1 to WDBL4. The output signal inverted by INVB3 is applied, and the phase comparison control signal LCOM for normal mode or test mode setting is directly applied to the gates of the NMOS transistors of the transfer gates TGB1 to TGB3.

The read data line phase comparators 300-1 to 300-3 are adjacent to each of the data input / output pads DQ1 to DQ4 and the respective output circuits 133-1 to 133-4 in the data lead path. The PMOS transistors of the transfer gates TG1 to TG3 and the respective transfer gates TG1 to TG3 that are positioned between the data output lines DOL1 to DOL4 and connect adjacent data output lines DOL1 to DOL4. It consists of inverters INV1 to INV3 connected to the gate.

Transfer gates TG1 to TG3 connecting the respective data input / output pads DQ1 to DQ4 and adjacent data output lines DOL1 to DOL4 between the respective output circuits 133-1 to 133-4. The output signal in which the phase comparison control signal LCOM for the normal mode or the test mode setting is inverted by the inverters INV1 to INV3 is applied to the gate of the PMOS transistor of the PMOS transistor, and the NMOS transistors of the transfer gates TG1 to TG3 are applied. The gate is directly applied with the phase comparison control signal LCOM for setting the normal mode or the test mode.

Accordingly, the test input data generator 100 controls the test mode control signal combination TMRS [2: 0] instead of receiving the write test data through the data input / output pads DQ1 and DQ3 in the data write path. The phase of the write test data is controlled by applying a power supply voltage or a ground voltage.

The test output data generator 400 may control the power supply voltage or the power supply voltage by the control of the test mode control signal combination TMRS [2: 0] in the data read path instead of receiving the read test data from the memory cell array 110. The phase of the read test data is controlled by applying a ground voltage.

In addition, the write data line phase comparison units 200-1 to 200-3 distinguish the normal mode from the test mode in the data write path, and write light bars adjacent to and adjacent to the adjacent write data lines WDL1 to WDL4 in the test mode. By checking whether the current flows between the lines WDBL1 to WDBL4 and measuring the phase difference between the two lines, it is determined whether there is a process defect of the semiconductor device under test or whether there is a short of the data write path wiring.

The lead data line phase comparison units 300-1 to 300-3 also distinguish the normal mode from the test mode in the data lead path, and check the current flow between adjacent data output lines in the test mode to check the phase difference between both lines. Is determined to determine whether there is a process defect in the semiconductor device under test or a short circuit in the data lead path wiring.

For example, when the semiconductor memory device under test operates normally, the value of the current measured through the power pad VCC in the ammeter 140-1 in the test equipment 140 is several uA while the bridge is in the data path. If there is a shorted part such as), the measured current value increases to several mA so that the data write and the read path of the semiconductor memory device under test can be tested for defects.

Next, an operation of the semiconductor memory device of the present invention will be described with reference to FIGS. 2 and 4. 4 is a diagram illustrating values of a test data level check and a phase comparison control signal according to a combination of test mode control signals in the semiconductor memory device of the present invention, where TMRS [2] is for normal mode setting and TMRS [1] is high. For the level data check, TMRS [0] is the test mode control signals for the low level data check, H-CK represents the high level check signal, L-CK represents the low level check signal, and LCOM represents the phase comparison control signal.

First, in the normal mode in the data write path, as shown in the table of FIG. 4, the gate of the PMOS transistors P1 and P2 in the test input data generator 100 is controlled by the control of the combination of the test mode control signal TMRS [2: 0]. When the level check (H-CK) signal is applied at the high level and the low level check (L-CK) signal is applied at the low level to the gates of the NMOS transistors N1 and N2, both transistors P1 to P4 and N1 are applied. To N4), all of them are turned off so that the first test mode selector 123 receives data through the data input / output pads DQ1 and DQ3 instead of the power voltage or the ground voltage. In the normal mode, the data is transferred directly to the input circuit 121 without passing through the demultiplexer stage 122 as the phase comparison control signal LCOM is applied low.

Phase comparison control signal LCOM for normal mode or test mode setting is applied to the PMOS transistor gates of the transfer gates TG1 to TG3 and TGB1 to TGB3 in the write data line phase comparison units 200-1 to 200-3. Inverted by (INV1 to INV3, INVB1 to INVB3) and applied to a high level, both transistors are turned off when the phase comparison control signal LCOM for normal mode or test mode setting is applied to the gate of the NMOS transistor at a low level. The transfer gates TG1 to TG3 and TGB1 to TGB3 are in a disabled state so that data is inputted without measuring the flow of current between the write data lines WDL1 to WDL4 or between the write data bar lines WDBL1 to WDBL4. The data is normally transferred to the memory cell array 110 at 121-1 to 121-4.

Next, in order to test the high level data in the test mode of the data write path, as shown in the table of FIG. 4, the PMOS transistors P1 and P2 and the NMOS transistors in the test input data generator 100 are controlled by the control of the test mode control signal. The high level check (H-CK) signal and the low level check (L-CK) signal are applied to the (N1, N2) gates at low levels, respectively, and the write data line phase comparison units 200-1 to 200-3 A phase comparison control signal (LCOM) for normal mode or test mode setting is applied at a high level.

Accordingly, the PMOS transistors P1 and P2 in the test input data generator 100 are turned on and the NMOS transistors N1 and N2 are turned off so that the power supply voltage is the first test mode selector 123-1, 123. -2), and this data is applied to the demultiplexer stage 122 as the phase comparison control signal LCOM is applied high in the test mode, so that each demultiplexer 122-1 and 122-2 has one bit. The controller converts the data into two bits and outputs the data to the input circuit 121. The input circuits 121-1 to 121-4 receive the data and transfer the data to the write data lines WDL1 to WDL4, and the data inverted to the low level is transferred to the write data bar lines WDBL1 to WDBL4. do.

In addition, the PMOS and NMOS transistors of the transfer gates TG1 to TG3 and TGB1 to TGB3 in the write data line phase comparison units 200-1 to 200-3 are turned on to the write data lines DIL1 to DIL3. The transferred high level data is transmitted to adjacent write data lines DIL2 to DIL4 and the low level data transferred to write data bar lines WDBL1 to WDBL3 is transmitted to adjacent write data bar lines WDBL2 to WDBL4. .

If the low level data is to be tested, the PMOS transistors P1 and P2 and the NMOS transistors N1 and N2 gates in the test input data generator 100 may be controlled by the control of the test mode control signal as shown in the table of FIG. 4. A phase check (H-CK) signal and a low level check (L-CK) signal are applied at a high level, and phase comparison for normal mode or test mode setting of the write data line phase comparison units 200-1 to 200-3 is performed. Apply the control signal LCOM to the high level.

Accordingly, the PMOS transistors P1 and P2 in the test input data generator 100 are turned off and the NMOS transistors N1 and N2 are turned on so that the ground voltage is the first test mode selector 123-1 and 123. -2), and this data is applied to the demultiplexer stage 122 as the phase comparison control signal LCOM is applied high in the test mode, so that each demultiplexer 122-1 and 122-2 has one bit. The controller converts the data into two bits and outputs the data to the input circuit 121. The input circuits 121-1 to 121-4 receive the data and transfer the data to the write data lines WDL1 to WDL4, and the data inverted to the low level is transferred to the write data bar lines WDBL1 to WDBL4. do.

In addition, the PMOS and NMOS transistors of the transfer gates TG1 to TG3 and TGB1 to TGB3 in the write data line phase comparison units 200-1 to 200-3 are all turned on to the write data lines WDL1 to WDL4. The transferred high level data is transmitted to adjacent write data lines WDL1 to WDL4 and the low level data transferred to write data bar lines WDBL1 to WDBL3 is transmitted to adjacent write data bar lines WDBL2 to WDBL4. .

At this time, if there is no process defect or short circuit of the semiconductor memory device under test, all adjacent write data lines WDL1 to WDL4 of the write data line phase comparison units 200-1 to 200-3 and Since the same level of data will be transmitted to the write data bar lines WDBL1 to WDBL4 respectively, the potential is the same, so that the increase of the current between the two lines through the power pad VCC in the ammeter 140-1 in the test equipment 140 is performed. Not measured

However, if there is a process defect or a short circuit in the semiconductor memory device under test, the defective write data lines or the write data bar lines of the write data line phase comparison units 200-1 to 200-3 may be normal. Since different levels of data will be transmitted to the write data lines or the write data bar lines, the potentials are different so that the increase of the current between the two lines through the power pad VCC in the ammeter 140-1 in the test equipment 140 can be achieved. Will be measured.

As a result, the test mode control signal is applied to all the data input / output pads DQ1 and DQ3 of the semiconductor memory device under test instead of receiving test data through the data input / output pads DQ1 and DQ3. The combination control makes it simple to test.

Similarly, in the normal mode in the data read path, as shown in the table of FIG. 4, the high level check (H-CK) signal is high on the gates of the PMOS transistors P1 to P4 in the test output data generator 400 under the control of the test mode control signal. When the level is applied and the low level check signal L-CK is applied at the low level to the gates of the NMOS transistors N1 to N4, both transistors are turned off. In addition, when the phase comparison control signal LCOM is applied at a low level, when the data from the memory cell array passes through the input / output sense amplifiers 131 and is applied to the second test mode selector 134, the comparator 132 is turned on. The data is transferred directly to the output circuit 133 without passing through.

Phase comparison control signal LCOM for normal mode or test mode setting is applied to the PMOS transistor gates of the transfer gates TG1 to TG3 and TGB1 to TGB3 in the read data line phase comparison units 300-1 to 300-3. Inverted by (INV1 to INV3, INVB1 to INVB3) and applied to a high level, both transistors are turned off when the phase comparison control signal LCOM for normal mode or test mode setting is applied to the gate of the NMOS transistor at a low level. The transfer gates TG1 to TG3 and TGB1 to TGB3 are in a disabled state and adjacent data output lines DOL1 to DOL4 between the output circuits 133-1 to 133-4 and the data input / output pads DQ1 to DQ4. Data is normally transferred from the output circuits 133-1 to 133-4 to the data input / output pads DQ1 to DQ4 without measuring the flow of current therebetween.

Next, in order to test the high level data in the test mode of the data lead path, as shown in the table of FIG. 4, the gates of the PMOS transistors P1 to P4 and the NMOS transistors N1 to N4 in the test output data generator 400 are used. The high level check (H-CK) signal and the low level check (L-CK) signal are applied at a low level, and the phases for setting the normal mode or the test mode of the read data line phase comparators 300-1 to 300-3. The comparison control signal LCOM is applied at a high level.

Accordingly, the PMOS transistors P1 to P4 in the test output data generator 400 are turned on and the NMOS transistors N1 to N4 are turned off so that the power supply voltages are output circuits 133-1 to 133-4. The data is applied to the data output lines DOL1 to DOL4 between the data input / output pads DQ1 to DQ4 through the output circuits 133-1 to 133-4.

In addition, the PMOS and NMOS transistors of the transfer gates TG1 to TG3 and TGB1 to TGB3 in the read data line phase comparison units 300-1 to 300-3 are turned on to output the circuits 133-1 to 133-. The high level data transferred to the data output lines DOL1 to DOL3 between 4) and the data input / output pads DQ1 to DQ4 are transmitted to the adjacent data output lines DOL2 to DOL4.

If the low level data is to be tested, the PMOS transistors P1 to P4 and the NMOS transistors N1 to N4 gates in the test output data generator 400 are controlled by the control of the test mode control signal as shown in the table of FIG. 4. A phase check (H-CK) signal and a low level check (L-CK) signal are applied at a high level, and phase comparison for normal mode or test mode setting of the read data line phase comparison units 300-1 to 300-3 is performed. Apply the control signal LCOM to the high level.

Accordingly, the PMOS transistors P1 to P4 in the test output data generator 400 are turned off and the NMOS transistors N1 to N4 are turned on so that the ground voltage is output to the output circuits 133-1 to 133-4. The data is applied to the data output lines DOL1 to DOL4 between the data input / output pads DQ1 to DQ4 through the output circuits 133-1 to 133-4.

In addition, the PMOS and NMOS transistors of the transfer gates TG1 to TG3 and TGB1 to TGB3 in the read data line phase comparison units 300-1 to 300-3 are turned on to output the circuits 133-1 to 133-. Low level data transferred to the data output lines DOL1 to DOL3 between 4) and the data input / output pads DQ1 to DQ4 are transmitted to the adjacent data output lines DOL2 to DOL4.

At this time, if there is no process defect or a short circuit of the semiconductor memory device under test, the adjacent data output line between all the output circuits 133-1 to 133-4 and the data input / output pads DQ1 to DQ4. Since the same level of data will be transmitted to each of the fields DOL1 to DOL4, the increase in current between the two lines is not measured through the power pad VCC in the ammeter 140-1 in the test equipment 140.

However, if there is a process defect or a short circuit of the wiring, different levels of data will be transmitted to the defective data line and the normal data line, so that the potential is different and thus the power pad in the ammeter 140-1 in the test equipment 140. The increase in current between both lines will be measured via (VCC).

Through this, all data input / output pads DQ1 to DQ4 of the semiconductor memory device to be tested are simply tested by controlling the test mode control signal combination instead of receiving data from the memory cell array. You can do it.

In the above description, a method of detecting defects in the write and read paths of the semiconductor memory device of the present invention has been described with only four data input / output pads provided for convenience of description. Applicable, of course, described with reference to the preferred embodiment of the present invention, those skilled in the art will be understood that the present invention without departing from the spirit and scope of the invention described in the claims below It will be understood that various modifications and changes can be made.

The semiconductor memory device of the present invention allows screening of data path defects for the semiconductor memory device under test so that all data paths can be tested without untested data input / output pads and data write / lead paths. You can save money.

Claims (7)

A plurality of data input / output pads; A plurality of input circuits configured to process input data applied to the plurality of data input / output pads during normal write operation and test write operation to generate write data from the plurality of write data lines; A test input data generator configured to generate test input data on a plurality of data input lines between the plurality of data input / output pads and the plurality of input circuits during the test write operation; A plurality of first phase comparison units configured to compare phases of signals between adjacent lines of the plurality of write data lines during the test write operation; A memory cell array configured to store the write data in the normal write operation and generate read data in a plurality of read data lines in the normal read operation; A plurality of input / output sense amplifiers configured to output read data amplified to a plurality of signal lines by amplifying read data in the normal read operation; A test output data generator for generating test output data on the plurality of signal lines in a test read operation; A plurality of output circuits for processing the test output data during the normal read operation and the test read operation to generate output data with a plurality of data output lines connected to the plurality of data input / output pads; And And a plurality of second phase comparators for comparing phases of signals between adjacent lines of the plurality of data output lines during the test read operation. The method of claim 1, The test input data generator is Generating a supply voltage or a ground voltage to the plurality of data input lines by control of a first or second control signal combination; The test output data generator And a power supply voltage or a ground voltage is generated in the plurality of signal lines by the control of the first or second control signal combination. The method of claim 1, The test output data generator and the test input data generator One PMOS transistor connected at one side to the supply voltage and one NMOS transistor connected at one side to the ground voltage consist of CMOS transistors connected in series. The high level check signal is applied to the gate of the PMOS transistor, and the low level check signal is applied to the gate of the NMOS transistor. The method of claim 1, The semiconductor memory device The adjacent write data lines and the adjacent write data bar lines; Each of the plurality of first phase comparison units Transmission gates connecting the adjacent write data lines and the adjacent write data bar lines, respectively; And an inverter configured to receive a third control signal, invert the data value, and apply the same to the gates of the PMOS transistors of each of the transfer gates. The method of claim 1, The semiconductor memory device The adjacent write data lines and the adjacent write data bar lines; Each of the plurality of second phase comparison units A transmission gate connecting the adjacent data output lines, respectively; And an inverter configured to receive a third control signal, invert the data value, and apply the same to the gate of the PMOS transistor of the transfer gate. The method according to claim 4 or 5, The semiconductor memory device includes a power pad, And an ammeter in the test equipment measures whether a data write or a read path of the semiconductor memory device under test is defective by measuring a change in current value through the power pad. The method according to claim 4 or 5, The semiconductor memory device An address latch unit receiving a mode setting signal from an external device via an address bus and storing the same, and outputting the predetermined time after a predetermined time elapses; A command decoder configured to receive command signals for mode selection from the outside and output a mode control signal; And a test mode control signal generator configured to receive the mode setting signal and the mode control signal to generate the first to third control signals.

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