JP2014006951A - Semiconductor device, method for testing semiconductor device, and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can test, from a specific terminal, a buffer circuit connected to another terminal.SOLUTION: A semiconductor device includes an input selection circuit, an output selection circuit, and an output switching circuit. The input selection circuit supplies an input signal, which is input to a plurality of input/output terminals, to a plurality of nodes via an input buffer, in a first mode; and supplies an input signal, which is input to a first input/output terminal out of the plurality of input/output terminals, to the plurality of nodes via a corresponding first input buffer, in a second mode. The output selection circuit, which is connected to the output sides of the plurality of input buffers except the first input buffer, and selectively outputs one of the outputs of the plurality of input buffers except the first input buffer according to a selection signal. The output switching circuit, which is inserted and connected in the middle of a connection line between a first node being one of the plurality of nodes and a first output buffer connected to the first input/output terminal, supplies an output signal, which is supplied to the first node, to the first output buffer in the first mode, and supplies the output of the output selection circuit to the first output buffer in the second mode.

Description

  The present invention relates to a semiconductor device, and more particularly to a test method thereof and a method of manufacturing a semiconductor device using the same.

  The semiconductor device described in Patent Document 1 includes a plurality of terminals, a plurality of drive units corresponding to the plurality of terminals, and a data control unit connected between the plurality of terminals and the plurality of drive units. It is out.

  In the normal mode, the data control unit outputs the parallel data input to the plurality of terminals to the plurality of driving units. In the test mode, the data control unit converts serial data input to a specific one of the plurality of terminals into parallel data, and outputs the converted parallel data to the plurality of driving units.

JP 2010-182358 A

  In the semiconductor device described in Patent Document 1, data input to a specific terminal can be output (write operation) to a plurality of drive units in a test mode. For this reason, it can be expected that the number of terminals to be brought into contact with the probe in the test mode is smaller than the actual number of terminals. However, this semiconductor device has a problem that in order to perform an operation test of the buffer circuit connected to each terminal, the probe must be in contact with all the terminals.

  Further, Patent Document 1 does not include a description of data output (reading operation) from a plurality of driving units to a specific terminal. Therefore, the semiconductor device of Patent Document 1 has a problem that the probe must be brought into contact with all the terminals in order to perform the read operation test. Even in the read operation, even if the same signal path as that in the write operation can be used, the operation test of the buffer circuit connected to a terminal other than the specific terminal cannot be performed as described above.

  As described above, the semiconductor device described in Patent Document 1 has a problem in that it is not possible to test the buffer circuit connected to the terminals unless the probes are in contact with all the terminals.

  A semiconductor device according to an embodiment of the present invention is connected to a plurality of input / output terminals including a first input / output terminal, to the plurality of input / output terminals, and to the first input / output terminal. A plurality of input buffers including a first input buffer; a plurality of output buffers each connected to the plurality of input / output terminals and including a first output buffer connected to the first input / output terminal; A plurality of nodes each including a first node corresponding to the first input / output terminal, and connected between the plurality of input buffers and the plurality of nodes, In the mode, input signals respectively input to the plurality of input / output terminals are supplied to the plurality of nodes via the plurality of input buffers, respectively, and in the second mode, to the first input / output terminal. Input entered An input select circuit that switches an input signal path according to a mode signal so as to supply a signal to the plurality of nodes via the first input buffer, and between the plurality of nodes and the plurality of input / output terminals. And a plurality of connection lines for supplying output signals supplied to the plurality of nodes to the plurality of input / output terminals, respectively, and connected to output sides of the plurality of input buffers excluding the first input buffer An output select circuit that selects and outputs one of the outputs of the plurality of input buffers excluding the first input buffer according to a selection signal; the first node; and the first output buffer. And in the first mode, an output signal supplied to the first node is supplied to the first output buffer, and is connected to the first output buffer. When the second mode, including an output switching circuit for supplying to said first output buffer an output of said output select circuit.

  A semiconductor device according to another embodiment of the present invention includes a first pad, a second pad, an input side connected to the first pad, and an output side connected to a first node. A buffer, an input side connected to the second node, an output side connected to the first pad, an input side connected to the second pad, and an output side connected to the third node A third buffer, a fourth buffer whose input side is connected to the fourth node, and whose output side is connected to the second pad; and while the first control signal is active, A first control circuit for controlling the logic level of the potential to be the same as the logic level of the potential of the third node; and whether the second node is either the first node or the fifth node 1st switch to switch to connect to either Including a circuit instead, an internal circuit connected to said first and fourth nodes, the.

  A test method for a semiconductor device according to still another embodiment of the present invention includes a first pad disposed on a semiconductor substrate and electrically connected to an internal circuit via a first input / output circuit. Contacting the probe; transmitting the test input signal to the internal circuit via the first pad and the first input / output circuit by inputting a test input signal to the probe; A test output signal output from the internal circuit in response to the test input signal, a second input / output circuit connected to a second pad on the semiconductor substrate, the first input / output circuit, and the Reading from the probe through a first pad.

  According to the present invention, the output of the output buffer connected to an input / output terminal other than the specific input / output terminal is output to the specific input / output terminal via the input buffer connected to the same input / output terminal. By selectively supplying to the buffer, it is possible to perform an operation test of the input buffer and the output buffer connected to all the input / output terminals from a specific input / output terminal.

1 is a schematic diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram illustrating a configuration of a main part of a DQ input / output circuit included in the semiconductor device of FIG. 1. FIG. 3 is a diagram for explaining a write operation in a test mode of the DQ input / output circuit of FIG. 2. FIG. 3 is a diagram showing a first state of a read operation in a test mode of the DQ input / output circuit of FIG. 2. It is a figure which shows an example of the circuit which outputs a selection signal. FIG. 6 is a diagram showing a second state of the read operation in the test mode of the DQ input / output circuit of FIG. 2. FIG. 10 is a diagram showing a third state of the read operation in the test mode of the DQ input / output circuit of FIG. 2.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  First, an overall schematic configuration of a semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. Here, a DRAM (Dynamic Random Access Memory) is exemplified as the semiconductor device, but the present invention is also applicable to other semiconductor devices having a plurality of input / output terminals.

  The illustrated semiconductor device 10 includes an internal clock generation circuit 101, a command decoder 102, a control circuit 103, a mode register 104, a row address buffer / refresh counter 105, a column address buffer / burst counter 106, a memory cell array 107, a row decoder 108, a column. A decoder 109, a sense amplifier 110, a data control circuit 111, a latch circuit 112, a DLL (Dray Locked Loop) 113, a DQ (data) input / output circuit 114, and a data input / output terminal 115 are provided.

  The semiconductor device 10 is included in the memory cell array 107 according to a clock signal (CK, / CK, CKE), an address signal (Address), and a command signal (/ CS, / RAS, / CAS, / WE) given from the outside. The data inputted from the data terminals DQ0 to DQn can be written into the memory cell to be written, and the written data can be read out. Further, the semiconductor device 10 can operate in accordance with various operation modes including a normal mode and a test mode by a combination of the above signals. Since these writing operation, reading operation and mode switching operation are well known, detailed description thereof will be omitted here.

  Hereinafter, characteristic portions of the present invention will be described in detail. The present invention particularly relates to the DQ input / output circuit 114 among the above configurations. Note that the components closer to the memory cell array 107 than the DQ input / output circuit 114 may be collectively referred to as an internal circuit.

  As shown in FIG. 2, the DQ input / output circuit 114 is connected to a plurality (four in this case, first to fourth) of data input / output terminals (or pads) (DQ0 to DQ3) 115 respectively. 1 to 4) input / output circuits 300-1 to 300-4. The first input / output circuit 300-1 includes first and second buffers, that is, a first input buffer 201-1 and a first output buffer 202-1. The second input / output circuit 300-2 includes third and fourth buffers, that is, a second input buffer 201-2 and a second output buffer 202-2. The third input / output circuit 300-3 includes fifth and sixth buffers, that is, a third input buffer 201-3 and a third output buffer 202-3. The fourth input / output circuit 300-4 includes seventh and eighth buffers, that is, a fourth input buffer 201-4 and a fourth output buffer 202-4.

  The DQ input / output circuit 114 includes an input select circuit 203, an output select circuit (first control circuit) and 204, and an output switching circuit (first switching circuit) 205.

  Here, the plurality of data input / output terminals 115 are classified into a specific input / output terminal (first input / output terminal, here DQ3) and other input / output terminals (DQ0 to DQ2). The first input / output terminal (DQ3) is a (probing) terminal to which a tester probe is pressed when the semiconductor device 10 is tested. In the present embodiment, the number of first input / output terminals is one, but may be two or more according to the number of data input / output terminals 115.

  Among the plurality of input buffers, the output side of the (first) input buffer 201-1 whose input side is connected to the first input / output terminal (DQ3) is associated with the first input / output terminal (DQ3). Is connected to the (first) node 206-1 by a connection line.

  Also, among the plurality of output buffers, the (first) output buffer 202-1 whose output side is connected to the first input / output terminal (DQ3) is one of the connection terminals of the output switching circuit 205. 2 nodes.

  Output buffers 201-2 to 201-4 connected to input / output terminals (DQ0 to DQ2) other than specific input terminals are switches (second to fourth switching circuits) included in the input select circuit 203. It is connected to one of the connection terminals 207-1 to 207-3 (third, sixth and eighth nodes). The switches 207-1 to 207-3 are connected to the nodes 206-2 to 206-4 (fourth, seventh and ninth) associated with the other input / output terminals (DQ0 to DQ2), respectively.

  Also, the input side of the output buffers 202-2 to 202-4 connected to the input / output terminals (DQ0 to DQ2) other than the specific input terminals is the corresponding (fourth, seventh and ninth) nodes 206-2 to 206-4 are connected to each other by a connection line.

  The input select circuit 203 includes a plurality (three in this case) of switches 207-1 to 207-3 as described above. These switches 207-1 to 207-3 are controlled by a test mode signal. Specifically, these switches 207-1 to 207-3 output the outputs of the input buffers 201-2 to 201-4 connected to the other input / output terminals (DQ0 to DQ2) according to the test mode signal. The signals are supplied to the corresponding nodes 206-2 to 206-4, or the output of the input buffer 201-1 connected to the first input / output terminal (DQ3) is supplied to the nodes 206-2 to 206-4. In other words, these switches 207-1 to 207-3 connect the fourth, seventh and ninth nodes 206-2 to 206-4 to the third, sixth and eighth nodes according to the test mode signal. Or connect to the first node.

  The output select circuit 204 includes a plurality of NAND circuits and one or more NOT circuits. The plurality of NAND circuits are connected to the input buffers 201-2 to 202-4 connected to the other input / output terminals (DQ0 to DQ2), respectively (three in this case) first NAND circuits 208-1. To 208-3 and one or more (two in this case) second NAND circuits 209-1 to 209-2 that cascade-connect the plurality of first NAND circuits. The NOT circuit 210 is connected to the output side of the NAND circuit of the odd-numbered stage (here, the first stage) of the second NAND circuit. The output select circuit 204 selects one of the outputs of the input buffers 201-2 to 202-4 in accordance with a selection signal composed of the decode signals 1 to 3 (first to third control signals), and switches the output. Output to the circuit 205. In other words, the output select circuit 204 selects one of the third, sixth, and ninth nodes in accordance with the first to third control signals, and the logic level of the potential of the fifth node is selected. It is controlled so as to be the same as the logic level of the potential.

  Output switching circuit 205 includes a switch controlled by a test mode signal. This switch includes a connection terminal to which the first node 206-1 is connected, a connection terminal to which the second buffer is connected (second node), and a connection terminal (fifth terminal) connected to the output of the output select circuit 204. Node). The output switching circuit 205 selects the node 206-1 or the output select circuit 204 (fifth node) according to the test mode signal, and connects it to the output buffer 202-1 (second node).

  Next, the operation of the DQ input / output circuit 114 configured as described above will be described. Note that the test mode signal and the selection signal are supplied from the control circuit 103 (see FIG. 1). An enable / disable control signal for controlling enable / disable of the input buffers 201-1 to 201-4 and the output buffers 202-1 to 202-4 is also given from the control circuit 103 (see FIG. 1).

  First, the operation in the normal mode (first mode) will be described with reference to FIG.

  In the normal mode, the test mode signal is “L”, and the switches 207-1 to 207-3 of the input select circuit 203 output the outputs of the input buffers 201-2 to 202-4 to the corresponding nodes 206-2 to 206-. 4 is ready to be supplied. In addition, the output switching circuit 205 is in a state of supplying the signal supplied to the node 206-1 to the output buffer 202-1.

  When performing the write operation, the input buffers 201-1 to 201-4 are enabled, and the output buffers 202-1 to 202-4 are disabled. As a result, input signals (write data) input to the plurality of DQ input / output terminals 115 are supplied to the corresponding nodes 206-1 to 206-4 via the corresponding input buffers 201-1 to 201-4, respectively. Is done. The write data supplied to the nodes 206-1 to 206-4 is written into the corresponding cell of the memory cell array 107.

  When performing a read operation, the input buffers 201-1 to 201-4 are disabled, and the output buffers 202-1 to 202-4 are enabled. As a result, the read data (output signal) read from the memory cell array 107 and supplied to the plurality of nodes 206-1 to 206-4 is transferred to the corresponding DQ via the corresponding output buffers 202-1 to 202-4. It is supplied to the input / output terminal 115.

  The output select circuit 204 is a simple load on the input buffers 201-1 to 201-4 during the normal mode operation. This load is not large enough to affect normal operation.

  Next, the operation in the test mode (degeneration mode; second mode) will be described with reference to FIGS.

  In the test mode, the test mode signal is “H”, and the switches 207-1 to 207-3 of the input select circuit 203 supply the output of the input buffer 201-1 to all the nodes 206-1 to 206-4. It becomes a state. In other words, the first node 206-1 is connected to the fourth, seventh and ninth nodes 206-2 to 206-4. The output switching circuit 205 is in a state of supplying the output of the output selection circuit 204 to the output buffer 202-1. In other words, the fifth node is connected to the second node.

  A write operation will be described with reference to FIG. During a write operation, all input buffers 201-1 through 202-4 are enabled, and all output buffers 202-1 through 202-4 are disabled.

  A probe 301 of a tester (not shown) is pressed against the first data input / output terminal (DQ3). Other data input / output terminals (DQ0 to DQ2) are not used at this time.

  The test input signal input to the first data input / output terminal (DQ3) is supplied to the corresponding node 206-1 via the input buffer 201-1 and branched via the input select circuit 203. It is also supplied to all other nodes 206-2 to 206-4.

  At this time, the output select circuit 204 is connected to the output buffer 202-1 via the output switching circuit 205, but is not involved in the operation because the output buffer 202-1 is disabled.

  The test input signals (write data) supplied to the nodes 206-1 to 206-4 are transmitted in parallel to the internal circuit side and are written into the corresponding memory cells of the memory cell array 107.

  Next, a read operation in the test mode will be described. During the read operation, all of the input buffers 201-1 to 202-4 and the output buffers 202-1 to 202-4 are enabled. Further, the output selection circuit 204 is controlled by the selection signal, and it is selected which of the nodes 206-1 to 206-4 to output the read data (test output signal) supplied to the output switching circuit 205. . In other words, the input buffer connected to which data input / output terminal and the output buffer are to be tested are determined by the selection signal.

  The selection signal can be generated using, for example, a counter. By using an AND circuit having an output enable input as shown in FIG. 5, the selection signals (decode signals 1 to 3) are not output in the normal mode, but the selection signals (decode signals 1 to 3) are output in the test mode. You can make it. The selection signal is sent to the first NAND circuits 208-1 to 208-3 respectively connected to the input buffers 201-2 to 201-4 as decoded signals 1 to 3 (first to third control signals) for each bit. Supplied.

  Data is read from the memory cell array 107 in parallel with respect to a plurality of memory cells. Read data read from the plurality of memory cells is output to the corresponding nodes 206-1 to 206-4, respectively.

  In FIG. 4, the read data read to the node 206-2 corresponding to the data input / output terminal DQ0 is output from the output select circuit 204 via the input buffer 201-2 connected to the data input / output terminal DQ0. A case of outputting to the switching circuit 205 (first state) is shown. The test targets in this case are the input buffer 201-2 and the output buffer 202-2.

  When the decode signal 1 of the selection signal is set to “H” (the first control signal is active), the output of the first NAND circuit 208-1 connected to the input buffer 201-2 is logically inverted from the read data. Signal. Also, by setting the other decode signals 2 and 3 to “L” (the second and third control signals are inactive), the first NAND circuit 208-connected to the input buffers 201-3 and 201-4 is used. The output of 2,208-3 is fixed to “H”. As a result, the output of the first NAND circuit 208-1 is output to the output switching circuit 205 via the second NAND circuits 209-1 and 209-2 and the NOT circuit 210 connected therebetween. . The signal output from the output select circuit 204 is output to the data input / output terminal DQ3 via the output switching circuit 205 and the output buffer 202-1.

  The output signal output to the data input / output terminal DQ3 is output to a tester (not shown) via the probe 301.

  The output signal output to the data input / output terminal DQ3 passes through the output buffer 202-2 and the input buffer 201-2 connected to the data input / output terminal DQ0. Therefore, based on this output signal, it is possible to detect the operation state of the input buffer 201-2 and the output buffer 202-2, for example, a failure.

  Note that the read data supplied to the nodes 206-1, 206-3, and 206-4 is not output to any data input / output terminal 115, and the operations of the input select circuit 203 and the output select circuit 204 are not performed. Also not involved in.

  FIG. 6 shows a case where the read data read to the node 206-3 is output to the first data input / output terminal (DQ3) (second state in which the second control signal is activated). FIG. 7 shows a case where the read data read to the node 206-4 is output to the first data input / output terminal (DQ3) (third state in which the third control signal is activated). .

  Also in the case shown in FIG. 6 and FIG. 7, the read signal input to the first NAND circuit 208 selected by the selection signal (decode signals 1 to 3) is the same as described with reference to FIG. 4. It is selectively output to the first data input / output terminal DQ3. Since this signal also passes through the output buffer and the input buffer to be tested, the operation states of the output buffer and the input buffer to be tested can be detected based on these signals.

  As described above, in the semiconductor device according to the present embodiment, the operation of the output buffers and input buffers connected to all the data input / output terminals in the test mode in which data is written and read from the specific data input / output terminals. Tests can be performed selectively.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above-described embodiments, and various modifications and changes can be made without departing from the spirit of the present invention. For example, as described in Patent Document 1, the write operation may be performed using a serial / parallel conversion circuit and a switch unit.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 101 Internal clock generation circuit 102 Command decoder 103 Control circuit 104 Mode register 105 Row address buffer / refresh counter 106 Column address buffer / burst counter 107 Memory cell array 108 Row decoder 109 Column decoder 110 Sense amplifier 111 Data control circuit 112 Latch circuit 113 DLL
114 DQ input / output circuit 115 Data input / output terminal 201-1 to 201-4 Input buffer 202-1 to 202-4 Output buffer 203 Input select circuit 204 Output select circuit 205 Output switching circuit 206-1 to 206-4 Node 207- 1 to 207-3 switch 208-1 to 208-3 first NAND circuit 209-1 to 209-2 second NAND circuit 210 NOT circuit 300-1 to 300-4 input / output circuit

Claims (20)

A plurality of input / output terminals including a first input / output terminal;
A plurality of input buffers each connected to the plurality of input / output terminals and including a first input buffer connected to the first input / output terminal;
A plurality of output buffers each connected to the plurality of input / output terminals and including a first output buffer connected to the first input / output terminal;
A plurality of nodes each corresponding to the plurality of input / output terminals and including a first node corresponding to the first input / output terminal;
Connected between the plurality of input buffers and the plurality of nodes, and in the first mode, input signals respectively input to the plurality of input / output terminals are input to the plurality of nodes via the plurality of input buffers. According to the mode signal so that the input signal input to the first input / output terminal is supplied to the plurality of nodes via the first input buffer in the second mode. An input select circuit for switching the input signal path;
A plurality of connection lines that are respectively connected between the plurality of nodes and the plurality of input / output terminals, and that supply output signals supplied to the plurality of nodes to the plurality of input / output terminals, respectively;
Connected to the output side of the plurality of input buffers excluding the first input buffer, and selects and outputs one of the outputs of the plurality of input buffers excluding the first input buffer according to a selection signal An output select circuit to
Inserted and connected in the middle of a connection line connected between the first node and the first output buffer, and in the first mode, an output signal supplied to the first node is sent to the first node. An output switching circuit that supplies the output of the output select circuit to the first output buffer in the second mode;
A semiconductor device comprising:   The semiconductor device according to claim 1, further comprising a control circuit that controls enable / disable of the plurality of input buffers and the plurality of output buffers and generates the selection signal. The output select circuit is
A plurality of first NAND circuits for outputting a negative logical product of each of the outputs of the plurality of input buffers excluding the input buffer corresponding to the first input / output terminal and a corresponding bit of the selection signal;
A plurality of second NAND circuits that cascade connect the plurality of first NAND circuits;
One or a plurality of NOT circuits that logically invert the output of the NAND circuit located at the odd-numbered stage among the plurality of second NAND circuits and output to the next stage;
The semiconductor device according to claim 1, further comprising: A first pad;
A second pad;
A first buffer having an input side connected to the first pad and an output side connected to a first node;
A second buffer having an input side connected to the second node and an output side connected to the first pad;
A third buffer having an input side connected to the second pad and an output side connected to a third node;
A fourth buffer having an input side connected to the fourth node and an output side connected to the second pad;
A first control circuit for controlling the logic level of the potential of the fifth node to be the same as the logic level of the potential of the third node while the first control signal is active;
A first switching circuit that switches the second node to connect to either the first node or the fifth node;
An internal circuit connected to the first and fourth nodes;
A semiconductor device comprising:   5. The semiconductor device according to claim 4, further comprising a second switching circuit that switches the fourth node so as to be connected to either the first node or the third node. 6. .   The second switching circuit connects the third node and the fourth node while the first switching circuit switches to connect the first node and the second node. The semiconductor device according to claim 5, wherein switching is performed so as to perform.   7. While the first control signal is active, the first switching circuit switches so that the second node is connected to the fifth node. The semiconductor device according to item.   8. The semiconductor device according to claim 4, wherein both of the first and second buffers are in an operating state while the first control signal is active. 9.   5. The signal from the outside is not supplied to the second pad while the first control signal is active, and a signal is supplied to the first pad by probing. The semiconductor device as described in any one of thru | or 8. A third pad;
A fifth buffer having an input side connected to the third pad and an output side connected to a sixth node;
A sixth buffer having an input side connected to the seventh node and an output side connected to the third pad;
The first control circuit controls the logic level of the potential of the fifth node to be the same as the logic level of the potential of the sixth node while the second control signal is active,
The semiconductor device according to claim 4, wherein the internal circuit is also connected to the seventh node.   11. The semiconductor device according to claim 10, further comprising a third switching circuit that switches the seventh node to be connected to either the sixth node or the first node. 11. . A step of bringing a probe into contact with a first pad disposed on a semiconductor substrate and electrically connected to an internal circuit via a first input / output circuit;
Transmitting the test input signal to the internal circuit via the first pad and the first input / output circuit by inputting a test input signal to the probe;
A test output signal output from the internal circuit in response to the test input signal, a second input / output circuit connected to a second pad on the semiconductor substrate, the first input / output circuit, and the Reading from the probe through a first pad;
A method for testing a semiconductor device including: Transmitting the test input signal includes branching the test input signal into a plurality of branch input signals, and transmitting the plurality of branch input signals to the internal circuit in parallel;
The step of reading the test output signal includes a step of obtaining a plurality of read signals in parallel from the internal circuit, and selectively selecting a signal corresponding to the second pad among the plurality of read signals as the test output signal. Supplying to the first pad,
13. The method for testing a semiconductor device according to claim 12, wherein: The step of reading the test output signal further includes:
Changing the signal path;
A signal corresponding to a third pad on the semiconductor substrate among the plurality of read signals is selected via a third input / output circuit connected to the third pad and the first input / output circuit. Typically supplying the first pad as the test output signal;
The method of testing a semiconductor device according to claim 13, comprising: The step of reading the test output signal further includes:
Including the step of bringing both an input buffer and an output buffer included in each of the first input / output circuit and the second input / output circuit into an operating state,
14. The method of testing a semiconductor device according to claim 12 or 13, The step of reading the test output signal further includes:
Including a step of bringing both an input buffer and an output buffer included in the first input / output circuit, the second input / output circuit, and the third input / output circuit into an operating state, respectively.
15. The method for testing a semiconductor device according to claim 14, wherein: On a semiconductor substrate, an internal circuit, a first input / output circuit, a first pad electrically connected to the internal circuit via the first input / output circuit, and a second input / output circuit Forming a second pad electrically connected to the internal circuit via the second input / output circuit;
Testing the second input / output circuit;
The step of testing includes
Contacting a probe with the first pad;
Transmitting the test input signal to the internal circuit via the first pad and the first input / output circuit by inputting a test input signal to the probe;
A step of reading a test output signal output from the internal circuit in response to the test input signal from the probe via the second input / output circuit, the first input / output circuit, and the first pad. A method of manufacturing a semiconductor device, comprising: Transmitting the test input signal includes branching the test input signal into a plurality of branch input signals, and transmitting the plurality of branch input signals to the internal circuit in parallel;
The step of reading the test output signal includes a step of obtaining a plurality of read signals in parallel from the internal circuit, and selectively selecting a signal corresponding to the second pad among the plurality of read signals as the test output signal. Supplying to the first pad,
The method of manufacturing a semiconductor device according to claim 17. The step of reading the test output signal further includes:
Changing the signal path;
A signal corresponding to a third pad on the semiconductor substrate among the plurality of read signals is selected via a third input / output circuit connected to the third pad and the first input / output circuit. Typically supplying the first pad as the test output signal;
The method for manufacturing a semiconductor device according to claim 18, comprising: The step of reading the test output signal further includes:
Including the step of bringing both an input buffer and an output buffer included in each of the first input / output circuit and the second input / output circuit into an operating state,
19. The method for manufacturing a semiconductor device according to claim 17, wherein the method is a semiconductor device manufacturing method.

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