KR0185643B1 - Stress voltage forcing apparatus of a semiconductor memory - Google Patents

Abstract

The present invention performs various mode tests with a minimum number of pins by controlling the enable and disable of word lines as redundant transistors. The present invention relates to a stress voltage applying device capable of applying a stress voltage, and an object of the present invention is to apply a stress voltage to a memory cell without loss of layout area using a minimum number of pins, thereby allowing a weak bit to be screened. And an application method thereof. According to an aspect of the present invention, memory cells connected to a plurality of bit lines or complementary bit lines, memory cell transistors for controlling an operation of writing data to or reading data from the memory cells, and the memory cells A plurality of word lines connected to the gates of the plurality of gate lines, a plurality of bit line sense amplifiers for sensing and amplifying the bit line and the complementary bit line, and precharging the bit line and the complementary bit line A stress voltage applying device of a semiconductor memory device having a plurality of equalization transistors includes a pad connected to one side of the equalization transistors, and a logic circuit combining the gate signals to output control signals for a wafer burn-in mode and a normal mode. Even word lines and odd number words among the word lines in the wafer state Alternating drive is enabled by the gate signal, and the voltage stress over the pad characterized in that it is applied to the memory cell.

Description

Stress voltage applying device of semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and in particular, to enable and disable word lines as redundant transistors, thereby controlling various modes with a minimum number of pins. The present invention relates to a stress voltage applying device capable of performing a test of.

In recent years, due to the development of overall technology for semiconductor memory devices, design rules of circuits have become smaller and smaller, and more memory cells have been arranged in a small area. Due to the reduction of the design rule, the ratio of the prime good die for all the memory chips to perform the correct operation is reduced, and thus the redundancy cells are prepared and failed. You are using the opposite method. The highest quality die or repairable good die is subjected to various tests to make a complete package, in which a good die is tested in a wafer state. Often, the die becomes a bad die. When analyzing these packages, the main causes of failures are word lines, word lines, bit lines and bit lines, bit line pairs and bit line pairs, and shorts between lines. Or, due to the micro bridge (Micro Bridge) is mainly dominated.

A method for screening ahead of time that a good cell turns out to be a bad cell after the above-described package step has been studied. One of them is wafer burn-in, and this wafer burn-in is used for all words. By enabling or disabling the lines at the same time, a method of stressing a memory cell in a shorter time than a package burn-in and screening a weak bit is used.

However, in order to perform the test on the wafer, a background write must be performed on the memory cell before the test, and thus all the pins are required, so that a large amount of die cannot be tested within a predetermined time.

1 is a configuration diagram of a stress voltage applying device configured to test a memory chip according to the prior art.

Referring to FIG. 1, memory cells 106 and 110 included in a memory cell array include a word line WL1WLn and a bit line pair BLm, A transistor T1 connected to a gate and a drain, respectively, and a capacitor C1 connected to the source of the transistor T1 are provided at the intersection. In addition, a plate voltage is applied to the other end of the capacitor C1. And a circuit for driving the memory cells includes a bit line pair BLm and A type sense amplifier 104 and an n-type sense amplifier positioned between each other, and configured to sense data read from the memory cells 106 and 110 or data to be written to the memory cells from the outside. 105) and the bit line BLm and the complementary bit line after the above-described sensing operation. An equalization transistor 103 is provided for precharging the capacitor. At this time, the bit line BLm and the complementary bit line A transistor 103 for precharging and the bit line pair BLm, Equalization control using a precharge voltage VBL for precharging the voltage level of the voltage level, that is, a signal applied to the gates of the transistors 101 and 102 for setting the voltage level to about half of the external power supply voltage. A signal PEQ is used, and if the signal PEQ is enabled, the bit line pair BLm, The bit line BLm and the complementary bit line BLmB are precharged to the level of the precharge voltage VBL by the precharge voltage VBL provided at.

In addition, transistors 111 to 115 are provided at one side of each word line WL, and a stress voltage Vstress applied to an external pad to gates and sources of the transistors 111 to 115. And the gate signal Vg are input to select all word lines WL at the same time.

Frequently occurring failures in the above-described structure are short bridges between V and V, word lines and word lines, bit lines and bit lines. In the prior art configuration method, since all pins must be used for background writing of data 1 or data 0 into the memory pin before the test, there is a limitation in performing a large amount of die through a wafer burn-in test within a predetermined time. The proposed technique to solve this constraint is shown in FIG.

2 is a diagram illustrating a stress voltage applying device configured to test memory cells according to the related art.

Referring to the configuration of FIG. 2, the circuits described in FIG. 1 are the same except that the sources of the transistors 111 to 115 connected to one side of the word lines WL are connected to different lines L1L4. The gate signal PWBE0PWBE4 is induced through these lines L1L4. In addition, the gates of the transistors 111 to 115 are connected to a signal WLC.

In the method of applying background data 1 to the memory cell in FIG. 2, the transistors 111 to 115 connected to one side of all word lines WL are enabled and equalized by applying a high level signal WLC. The signal PEQ keeps low level. The gate signals PWBE0 and PWBE3 are at a high level, and the gate signals PWBE1 and PWBE2 are at a low level, thereby charging all word lines WL connected to the transistors 111 to 115 to a high level and a low level, respectively. . Subsequently, enable equalization control signal PEQ so that bit line pair BLm, A high level bias is applied to the voltage VBL through the equalization transistors 101 and 102 connected to the data cell 1 to allow the data sense 1 to be written to the memory cells 106, 109 and 110, and then drives the type sense amplifier 104 and the type sense amplifier 105 to drive the bit line. BLm goes high and complementary bitline This low level causes cell stress to be performed on the memory cells connected to the bit line BLm. The voltage level between them will show a big difference, Short-circuit bridges and the like can be found, and various combinations of PWBE1PWBE4 enable testing of various patterns with a small number of pins that could not be performed in the conventional manner.

However, even in the circuit diagram shown in Fig. 2, five dummy pads are required, and four additional lines L1L4 are required, which is a great loss in the layout area. In particular, in the split word line driving method, an increase in chip size causes a decrease in a net die.

Accordingly, an object of the present invention is to provide a stress voltage applying device and a method of applying the same, wherein a weak bit can be screened by applying a stress voltage to a memory cell without losing a layout area using a minimum number of pins.

Another object of the present invention is to provide a stress voltage applying device and a method of applying the same, which can test a large amount of die within a predetermined time and can perform various modes of testing.

1 is a circuit diagram for applying a stress voltage to a memory cell according to a first embodiment of the prior art;

2 is a circuit diagram for applying a stress voltage to a memory cell according to a second embodiment of the prior art;

3A, 3B, and 3C are circuit block diagrams showing control signals required for performing a background write to a memory cell according to an embodiment of the present invention.

4 is a detailed circuit diagram of a word line driver constructed in accordance with the first embodiment of the present invention;

5 is a logic circuit diagram for providing a wafer burn-in control signal constructed in accordance with a second embodiment of the present invention.

6 is a detailed circuit diagram of an equalization signal generator for providing an equalization signal according to a third embodiment of the present invention.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

It should be noted that like elements and parts in the figures represent the same numerals wherever possible.

Before describing the present invention, first of all, it is necessary to know which test pattern can most effectively screen the wick bit from the memory cell point of view. The Low Stripe Pattern can screen the weak beat most effectively. Therefore, in the present invention, a method of writing data into a memory cell through the precharge voltage VBL to write a row stripe pattern into the memory cell without an address pin will be described as an embodiment.

3A to 3C are circuit block diagrams showing control signals required for performing a background write to a memory cell according to an embodiment of the present invention.

Referring to FIGS. 3A, 3B, and 3C, when VPP is applied to the odd gate signal PWBE-O, the odd-numbered word lines WL1, WL3, WL5, ... are enabled, and VPP is applied to the equalization control signal PEQ. The data is transferred to write data 1 to the selected memory cell through the VBL pad. Subsequently, when VPP is applied to the even-gate signal PWBE-E, the even-numbered word line WL is enabled and VPP is transferred to the equalization control signal PEQ to write data 0 to the selected memory cell through the VBL pad. The row stripe pattern is then written to all the memory cells, effectively screening the memory cells. As shown in FIGS. 3A and 3B, the operation is repeatedly performed to alternate odd and even word lines WL to perform a refresh operation to screen the short bridge after sufficiently stressing the memory cell. Let's do it.

As described above, in order to write a row stripe pattern to a memory cell without using an address pin, a combination of these signals PWBE-E and PWBE-O, in addition to the gate signals PWBE-E and PWBE-O flowing through the dummy pad, may be used. Signals PWBE-M, PWBE-C, PWBE-P are required, which is shown in FIG. In order to apply a stress voltage to a memory cell, a word line and a bit line must be controlled. For this, a word line driver, an equalization signal generator, and a bit line voltage generator for providing the bit line voltage VBL are required. Therefore, when only one of the PWBE-E and PWBE-O is selected, the PWBE-M is enabled and the even or odd word lines are enabled to stress the word lines, thereby controlling the bit line precharge of the memory cell. Spoly bridges and dielectric defects are stressed out. During the stress operation, the equalization control signal PEQ, which controls the precharge to transfer to the memory cell without dropping the bit line voltage VBL level, is boosted to VPP-Vtn (threshold voltage of the NMOS transistor).

4 is a detailed circuit diagram of a word line driver constructed in accordance with an embodiment of the present invention.

Referring to FIG. 4, the stress voltage is applied to the word line WL by using the NMOS transistor 403 which serves to maintain the word line at the ground level in the normal mode. In the figure, signal NWEi is a row decoded signal, signal PXi is a boosted row decoded signal, and a signal Is the inverted signal of the signal PXI.

Referring to FIG. 5, a signal PWBE-M output through an exclusive logical sum 501 inputting the two signals PWBE-E and PWBE-O includes a word line driver, an equalization control signal generator, and a bit line voltage during wafer burn-in. A signal for controlling the generator, and a signal PWBE-C output through the AND gate 502 which takes the two signals PWBE-E and PWBE-O as inputs is a signal for controlling the CBR logic at the time of wafer burn-in. The signal PWBE-P, which is output through the noah gate 503 that inputs the two signals PWBE-E and PWBE-O, is a signal for controlling the buffer and other DC circuits that input the column address strobe signal at wafer burn-in. to be.

6 is a detailed circuit diagram of an equalization control signal generator constructed in accordance with another embodiment of the present invention.

When the level of the signal PWBE-M is at a high level, that is, a circuit diagram for providing VPP as the equalization control signal PEQ.

As described above, according to the present invention, a weak bit can be screened by applying a stress voltage to a memory cell without losing a layout area using a minimum number of pins. The present invention also has the advantage of being able to test a large amount of die in a certain amount of time, as well as conducting various modes of testing.

Claims (7)

Memory cells connected to a plurality of bit lines or complementary bit lines, memory cell transistors for controlling an operation of writing or reading data to the memory cells, and a plurality of word lines connected to gates of the memory cells, respectively. And a plurality of bit line sense amplifiers for sensing and amplifying the bit line and the complementary bit line, and a plurality of equalization transistors for precharging the bit line and the complementary bit line. In the stress voltage application device: A pad connected to one side of the equalization transistor and a logic circuit for combining the gate signals to output control signals for the wafer burn-in mode and the normal mode, and an even word word and an odd word word among the word lines in a wafer state And applying a stress voltage to the memory cells through the pads alternately with the gate signal. The apparatus of claim 1, wherein the signal applied to the gate of the equalization transistor when the stress voltage is applied is a signal having a voltage value between a power supply voltage and a program voltage. The semiconductor device of claim 1, wherein the gate signals are divided into an odd gate signal for enabling the odd word lines and an even gate signal for enabling the even word lines. Device. 4. The logic circuit of claim 3, wherein the logic circuit comprises an exclusive logic sum for outputting various control signals required for the wafer burn-in test using the odd gate signal and the even gate signal as two inputs, and an AND gate and a no gate. A stress voltage applying device for a semiconductor memory device. The apparatus of claim 1, wherein the stress voltage is a voltage having a value of 1.4 to 2 times the power supply voltage. 2. The method of claim 1, wherein high level data is filled in memory cells connected to the odd word line among the memory cells, and low level data is filled in memory cells connected to the even word line. A stress voltage applying device for a semiconductor memory device. Memory cells connected to a plurality of bit lines or complementary bit lines, a plurality of word lines respectively connected to gates of the memory cells, and a plurality of bit line senses for sensing and amplifying the bit lines and complementary bit lines. A wafer of a semiconductor memory device having amplifiers, a plurality of equalization transistors for precharging the bit lines and complementary bit lines, and a gate signal for controlling bit line levels through pads connected to one side of the equalization transistors. In the stress voltage application method in the state: Charging data complementary to each other through the gate signal by alternating between even and odd word lines among the word lines; And applying a stress voltage to the memory cell through the gate signal.