CN106896317B

CN106896317B - Circuit debugging method and circuit debugging system executed by scan chain of scan test

Info

Publication number: CN106896317B
Application number: CN201610820540.3A
Authority: CN
Inventors: 郭俊仪; 陈莹晏; 李日农
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2015-12-21
Filing date: 2016-09-13
Publication date: 2020-03-31
Anticipated expiration: 2036-09-13
Also published as: TW201723516A; CN106896317A; TWI625534B

Abstract

The present disclosure provides a circuit debug method and a circuit debug system performed by a scan chain of a scan test. The debugging method comprises the following steps: utilizing a fault-clearing circuit to judge an operation state of a specific circuit and generate a judgment result; storing the determination result through a register on a scan chain path, wherein the scan chain path is used for executing a scan test; and outputting the determination result through an output connection pad on the scan chain path, wherein the determination result is observed to be used for debugging the specific circuit. The debugging method provided by the disclosure can save a large number of output pads so as to save the manufacturing cost.

Description

Circuit debugging method and circuit debugging system executed by scan chain of scan test

Technical Field

The present disclosure relates to the field of integrated circuit testing technologies, and in particular, to a method and a system for performing a circuit debug by a scan chain of a scan test.

Background

In the field of integrated circuit testing, because the number of signal lines of a digital or analog integrated circuit is large, it is a significant consideration of the integrated circuit design in terms of controlling the number of connection pads (Pad), and the debug is also a link that is not negligible in the integrated circuit testing, and conventionally, if the debug is performed on a specific circuit, for example, if there is a frequency and design difference between the oscillating frequency of a Phase Lock Loop (PLL) in an integrated circuit, and it is necessary to observe the frequency, in the prior art, a frequency signal generated by the oscillation of the PLL enters a frequency divider and is output through a connection Pad and then observed by a user to perform the debug, and thus, if the debug is performed on a plurality of specific circuits, a large number of connection pads will be consumed, resulting in an increase in production cost.

Disclosure of Invention

One objective of the present disclosure is to provide a circuit fault-clearing method and a circuit fault-clearing system executed by a scan chain of scan tests.

According to an embodiment of the present disclosure, a method for debugging a circuit is disclosed, wherein the method comprises: utilizing a fault-clearing circuit to judge an operation state of a specific circuit and generate a judgment result; storing the determination result through a register on a scan chain (scan chain) path, wherein the scan chain path is used for executing a scan test (scan test); and outputting the determination result through an output connection Pad (Pad) on the scan chain path, wherein the determination result is observed to debug the specific circuit.

According to an embodiment of the present disclosure, a circuit debug system is disclosed, wherein the system comprises: a specific circuit, an error-aligning circuit, a register and an output pad. The debugging circuit is used for judging an operation state of the specific circuit and generating a judgment result; the register is used for storing the judgment result, wherein the register is positioned on a Scan chain (Scan chain) path used for executing a Scan test (Scan test); the pad (pad) is used to output the determination result, wherein the pad is included in the scan test and the determination result is observed to debug the specific circuit.

Drawings

Fig. 1 is a schematic diagram of a scan test area according to the prior art.

FIG. 2 is a schematic diagram of a circuit debug system according to an embodiment of the present disclosure.

FIG. 3 is a schematic diagram of a circuit debug system according to another embodiment of the present disclosure.

FIG. 4 is a schematic diagram of a test environment employing a circuit debug system according to an embodiment of the present disclosure.

FIG. 5 is a schematic diagram of a test environment employing a circuit debug system, according to another embodiment of the present disclosure.

Description of reference numerals:

111. 112, 113 combined circuit

121. 122, 123 multiplexer

131. 132, 304 register

N1, N2 end points

100. 210, 310, 511, 512 scanning the test area

CS control signal

201. 301, 401, 501, 503 specific circuits

202. 302, 402, 502, 504 debugging circuit

203. 303 debugging multiplexer

DR judged result

DRS debugging control signal

200. 300 circuit debugging system

400. 500 test environment

410. 510 scan test system

420. 520 output connection pad

430. 530 test apparatus

Detailed Description

Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. The present specification and claims do not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Furthermore, the term "coupled" is used herein to encompass any direct or indirect electrical connection, such that if a first device is coupled to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

Fig. 1 is a schematic diagram of a scan test (scan test) area 100 according to the prior art, as shown in fig. 1, a conventional scan test area 100 includes

combinational circuits

111, 112, and 113,

multiplexers

121, 122, and 123, and

registers

131 and 132, the

combination circuits

111, 112 and 113 are not limited to any kind of digital or analog circuits, and the

registers

131 and 132 are not limited to any kind of circuits, and may be D-type Flip-flops (D Flip flops) or T-type Flip-flops, each arrow shown in fig. 1 does not represent only one signal, but may be one or more signals, such as combining circuit 111 outputting two output signals to multiplexer 121, those skilled in the art of scan testing will readily understand these circuit implementations, and the present disclosure will focus on debug methods, details regarding the circuitry in the scan test area 100 will be omitted here for brevity. Conventionally, the control signal CS controls the

multiplexers

121, 122 and 123 to operate in shift-in, capture and shift-out modes, when the

multiplexers

121, 122 and 123 operate in the shift-in mode, the

multiplexers

121, 122 and 123 and the

registers

131 and 132 form a scan chain (scan chain) path, it should be noted that the scan test area 100 does not represent the entire scan test system, but may only represent a part of the scan test system, i.e., the combining circuit 111 may be coupled to the output node N1 of another scan test area before, and the multiplexer 123 may be coupled to the input node N2 of another scan test area after.

FIG. 2 is a schematic diagram of a circuit debug system 200 according to an embodiment of the present disclosure, as shown in FIG. 2, the circuit debug system 200 includes a scan test area 210, a specific circuit 201 to be debugged, and a debug circuit 202, wherein the scan test area 210 includes a debug multiplexer 203 in addition to the components of the scan test area 100 shown in FIG. 1; the specific circuit 201 is a Phase Lock Loop (PLL) circuit, however, in other embodiments, the specific circuit 201 may be a Static Random Access Memory (SRAM), a Low Dropout Linear Regulator (LDO), or a flash Memory (flash Memory), i.e., the circuit architecture of the specific circuit 201 is not a limitation of the present disclosure. The debug circuit 202 is configured to detect an operation state OS of the specific circuit 201 and generate a determination result DR, for example, when the specific circuit 201 is a phase-locked loop, the operation state OS may be a frequency generated by oscillation of the specific circuit 201, and the debug circuit 202 receives the frequency to determine whether the frequency matches the design, and generates the determination result DR, where the determination result DR is a logic value, and if the determination result DR is a logic value 1, it indicates that the frequency is correct, and if the determination result DR is a logic value 0, it indicates that the frequency is incorrect; for another example, the operation state OS may be Jitter (Jitter) of the phase-locked loop, and the debug circuit 202 determines whether the resolution of the Jitter is greater than a predetermined value after receiving the Jitter information, if so, the determination result DR is generated as logic value 1, otherwise, the determination result DR is generated as logic value 0; it should be noted that the determination result DR generated by the debug circuit 202 is not limited to a single-bit logic value, but may be a plurality of-bit logic values, for example, the determination result DR may be 00, 01, 10 and 11, and various logic values represent different operation states of the specific circuit 201, for example, 00 is a duty cycle error, 01 is a frequency error, and so on, and these design changes are within the scope of the present disclosure. The debug multiplexer 203 is configured to receive the determination result DR, and control the debug multiplexer 203 to operate in a debug mode through a debug control signal DRs, when operating in the debug mode, the debug multiplexer 203 stores the determination result DR in the register 132, and then, when operating in the shift-out mode, the

multiplexers

121, 122, and 123 transmit the determination result DR from the register 132 to a rear output connection Pad (Pad) (not shown in fig. 2), so that a user can directly observe the determination result DR on a test machine for debugging. It should be noted that when debug multiplexer 203 is not operating in the debug mode, it will operate in synchronization with

multiplexers

121, 122, and 123, i.e., the debug multiplexer does not affect the normal scan test operation, and when

multiplexers

121, 122, and 123 are operating in the move-in mode, debug multiplexer 203 also sends the output signal of multiplexer 122 to register 132.

FIG. 3 is a schematic diagram of a circuit debug system 300 according to another embodiment of the present disclosure, as shown in FIG. 3, the circuit debug system 300 includes a scan test area 310, specific circuits 301, and debug circuits 302, wherein the scan test area 310 includes debug multiplexers 303 and a register 304 in addition to the components of the scan test area 100 shown in FIG. 1, and the purpose and function of the specific circuits 301, debug circuits 302, and debug multiplexers 303 are the same as those described in the embodiment of FIG. 2, and the details thereof are omitted here, but the embodiment of FIG. 3 differs from the embodiment of FIG. 2 in that the debug multiplexers 303 and the register 304 are used to store the determination result DR on the path of the scan chain of the embodiment of FIG. 3, wherein the debug multiplexers 303 and the register 304 are not part of the original scan test system, that is, the debug multiplexers 303 and the register 304 do not affect any combinational circuits, it is only used for storing and transmitting the determination result DR, unlike a register on the shared scan chain path in the embodiment of fig. 2. After reading the above embodiments, those skilled in the art can easily understand the detailed operation of the embodiment shown in fig. 3, and thus the detailed description is omitted here.

Fig. 4 is a schematic diagram of a test environment of an application circuit debug system 400 according to an embodiment of the present disclosure, as shown in fig. 4, a scan test system 410 may include a plurality of scan test areas (shown by dotted lines), such as the

scan test areas

210 or 310, and after determining an operation state DR of a specific circuit 401, a debug circuit 402 transmits a determination result DR to a debug multiplexer (not shown in fig. 4) included in the scan test area. It should be noted that a scan test system is not only capable of performing debugging by observing the operation status of a single specific circuit, but fig. 5 is a schematic diagram of a test environment of an application circuit debugging system 500 according to an embodiment of the present disclosure, and as shown in fig. 5, a scan test system 510 can observe the operation statuses of a plurality of specific circuits (in this embodiment, specific circuits 501 and 503), then transmit the respective determination results DR1 and DR2 to scan

test areas

511 and 512 via the corresponding debugging circuits (in this embodiment, specific circuits 502 and 504), and output the determination results DR1 and DR2 to an output pad 520 by the operation of the above embodiment, wherein the output pad 520 is coupled to a test equipment 530, and then a user can observe the determination results DR1 and DR2 via the test equipment 530 to debug the

specific circuits

501 and 503.

Briefly summarized, the present disclosure provides a circuit debug system and method, which outputs the operation status of a specific circuit through a scan chain in a scan path to perform debug, thereby saving a large number of output pads and manufacturing cost.

The above description is only a preferred embodiment of the present disclosure, and all equivalent changes and modifications made in the claims of the present disclosure should be covered by the present disclosure.

Claims

1. A method for debugging a circuit, comprising:

utilizing a fault-clearing circuit to judge an operation state of a specific circuit and generate a judgment result;

controlling a debug multiplexer to enter a debug mode to store the determination result into a register on a scan chain path, wherein an input of the debug multiplexer is coupled to the debug circuit, an output of the debug multiplexer is connected to the register, and the debug multiplexer is connected to a multiplexer, wherein the scan chain path is used for executing a scan test; and

outputting the determination result through an output pad, wherein the determination result is observed to debug the specific circuit;

when the debug multiplexer is not operated in the debug mode, the output signal of the multiplexer on the scan chain path is transmitted to the register.

2. The method of claim 1, wherein the specific circuit is a phase locked loop.

3. The circuit debug method as claimed in claim 2, wherein the operation status of the specific circuit is a frequency generated by the phase-locked loop, and the debug circuit generates the determination result according to the frequency to determine whether the phase-locked loop is operating normally.

4. The circuit debugging method of claim 2, wherein the operating status of the specific circuit is jitter generated by the phase-locked loop, and the debugging circuit generates the determination result according to the jitter to determine whether the phase-locked loop is operating normally.

5. The method of claim 1, wherein the specific circuit is a static random access memory, a low dropout regulator (LDO), or a flash memory.

6. A circuit debug system, comprising:

a specific circuit;

a fault-clearing circuit for judging an operation state of the specific circuit and generating a judgment result;

a scan test area, wherein the scan test area comprises:

a register for storing the judgment result, wherein the register is located on a scanning chain path for executing a scanning test;

a multiplexer, and

an input of the debug multiplexer is coupled to the debug circuit, an output of the debug multiplexer is connected to the register, and the debug multiplexer is connected to the multiplexer; controlling the debug multiplexer to enter a debug mode through a control signal to store the determination result in the register; when the debugging multiplexer is not operated in a debugging mode, the output signal of the multiplexer is transmitted to the register; and

an output pad for outputting the determination result, wherein the determination result is observed to debug the specific circuit.

7. The circuit debug system as claimed in claim 6, wherein the specific circuit is a phase locked loop.

8. The circuit debug system as claimed in claim 7, wherein the operation status of the specific circuit is a frequency generated by the phase-locked loop, and the debug circuit generates the determination result according to the frequency to determine whether the phase-locked loop is operating normally.