CN101420417B - Digital content scanning circuit and scanning method thereof - Google Patents
Digital content scanning circuit and scanning method thereof Download PDFInfo
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- CN101420417B CN101420417B CN200710180299A CN200710180299A CN101420417B CN 101420417 B CN101420417 B CN 101420417B CN 200710180299 A CN200710180299 A CN 200710180299A CN 200710180299 A CN200710180299 A CN 200710180299A CN 101420417 B CN101420417 B CN 101420417B
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Abstract
The present invention relates to a circuit for scanning data content and a method thereof, wherein a storing circuit stores a plurality of label data, and furthermore each label data is corresponding to a sub-regulation. The storing circuit is used for receiving a first input data and outputting a first bit in first label data to an operation circuit, and receiving a second input data and outputting a second bit of second label data to the operation circuit. The operation circuit executes logic operation to the first bit and the second bit and outputs an operation result. A determining circuit receives the operation result and determines whether the input data accord with a preset regulation according to the operation result. Thereby the complexity of the circuit can be saved, and furthermore the cost is saved and the scanning efficiency is increased.
Description
Technical field
The present invention is relevant for a kind of data content scanning circuit, and it especially refers to a kind of scanning circuit and scan method of network data content.
Background technology
The technology of computer technology is more and more flourishing now, and transmission rate and transmitting bandwidth also improve along with the progress of science and technology, and therefore transmissible data traffic is also just big more.Because various factors, therefore the data in transmission may carry virus or advertisement webpage etc. secretly, and then drag the processing speed of slow system even system is poisoned and can't normal operation.Therefore; In many application of system, similarly be network management interchanger (Web Switch), load balancer (Load balancer) and virus defense or the like now, can check one by one the content of data; To avoid taking place the problems referred to above, this is content scanning (contentscanning).
See also Fig. 1, be the scanning circuit of the data content of known technology.As shown in the figure; Scanning circuit 10 ' comprises many comparators 20 ', these a plurality of comparators 20 ' since the content of uncertain the bag data that will search in which position, scan one by one so must wrap all the elements of data to this; To guarantee not have the situation generation that scanning is omitted; As shown in Figure 1, after first byte to the, five bytes of having compared these bag data, then must compare second byte to the, six bytes; Therefore must second byte to the, five bytes be deposited earlier usually, with as the usefulness of comparing next time.Again; Because the scanning circuit range of application is wider; And the foundation of every kind of application class is all different, so the length of each rule (rules) also can be different, for example working as needs the rule of scanning to have 10; But what wherein the length of rule was the shortest possibly only have two or three bytes (Bytes), but the longest rule has tens bytes.Now for solving each above-mentioned regular length different problems; The size that can set each rule is certain, if will set short rule, a mask 22 ' (mask) is set then; Use again comparator 20 ' comparison with confirm whether to meet the data that will scan; So not only waste the extra space of depositing with as than than usefulness, do also comparatively complicatedly in that circuit is real simultaneously, and the bigger space of depositing need be arranged for the rule of length.
Therefore the present invention is directed to the problems referred to above and propose a kind of scanning circuit and method of data content, can save circuit area, can dynamically set the length of scanning rule again, increasing the flexibility of scanning, and can shorten sweep time.
Summary of the invention
One of the object of the invention is to provide a kind of scanning circuit and method of data, scans input section data data and whether meets scanning rule, to reach the complexity of saving circuit, to save cost and the purpose that improves scan efficiency.
One of the object of the invention is to provide a kind of scanning circuit and method of data, and it can dynamically set the length of scanning rule, to increase the flexibility of scanning.
One of the object of the invention is to provide a kind of scanning circuit and method of data, and it can learn the position of data in these a plurality of input data that meets scanning rule.
The scanning circuit of data of the present invention and method; It comprises a memory circuit, a computing circuit and a decision circuitry, a plurality of label datas of memory circuitry stores, and each label data corresponds to a sub-rule; When one first input data are sent to memory circuit and the first position of exporting these a plurality of label datas; And being sent to computing circuit, one second input data are sent to memory circuit and the second portion position of exporting these a plurality of label datas, and are sent to computing circuit; Computing circuit logical operation first position and second portion position produce an operation result, and decision circuitry receives operation result and judges whether the input data meet predetermined rule.
Description of drawings
Fig. 1 is the data scanning circuit of known technology;
Fig. 2 is the calcspar of a preferred embodiment of the present invention;
Fig. 3 is the circuit diagram of a preferred embodiment of the present invention: and
Fig. 4 is the calcspar of another preferred embodiment of the present invention.
The main element symbol description
10 ' scanning circuit
20 ' comparator
22 ' mask
10 physical layer devices
20 memory circuits
22 first memory circuits
24 second memory circuits
26 sequence units
30 computing circuits
32 triggers
34 logical blocks
36 isolated locations
40 decision circuitry
50 treatment circuits
60 counting units
70 medium access controllers
80 data scanning circuit
Embodiment
For the effect that makes architectural feature of the present invention and reached has further understanding and understanding, with preferred embodiment and cooperate detailed explanation, explain as the back:
Please consult Fig. 2 and Fig. 3 in the lump, it is the calcspar and the circuit diagram of a preferred embodiment of the present invention.As shown in the figure, this embodiment is applied to the bag data of world-wide web with scan for networks, similarly is network management interchanger (Web Switch) or load balancer (Load balancer), but the present invention does not limit to and is applied to world-wide web.This embodiment comprise a physical layer device 10 (Physical, PHY) with a medium access controller 70 (Media Access Control, MAC); This medium access controller 70 comprises a data scanning circuit 80 and a treatment circuit 50; Data scanning circuit 80 also comprises a memory circuit 20, a computing circuit 30 and a decision circuitry 40.Physical layer device 10 receives the input data, and the input data comprise multidata, because this embodiment is for being applied in the world-wide web, so the input data are bag data of world-wide web.
Accept above-mentioned; Many batches of label datas of memory circuit 20 storages, every batch of label data is corresponding to a sub-rule (for example: character A, symbol ... Deng), every batch of label data comprises the N bit data; Each data is distributed in different memory circuits 20 addresses; And the N-1 of label data position corresponds to same logical value, and each label data is a programmable label data again, supplies the user to set.One by way of example of memory circuit 20 storage bit number certificates, with sub-rule corresponding to the memory address of memory circuit 20 and set numerical value.
Below illustrate,, promptly comprise five sub-rules of ABCDE if will search the scanning rule that whether comprises ABCDE in these a plurality of input data; ASCII(American Standard Code for information interchange) (the America Standard Code for Information Interchange Code that first sub-rule A is corresponding; ASCII Code) be 65, so in memory circuit 20, the memory address 65 of storing first label data is set at 1; The position of remaining address (being address 0-64 and 66-255) all is set at 0; And second sub-rule B corresponds to ASCII Code 66, and promptly in memory circuit 20, the memory address 66 of storing second label data is set at 1; The position of remaining address (being address 0-65 and 67-255) all is made as 0, and the rest may be inferred for remaining scan-data CDE.If the then corresponding position of the outer unheeding data of scanning rule then all is made as 1, the data X shown in figure three, it is the 6th data, so the 6th part position of all memory addresss all is made as 1.Because the scan method of this embodiment is the unit with the byte; Add that a byte has 256 kinds of combinations, so the degree of depth of the memory circuit 20 of this embodiment is 256, promptly has 256 addresses; Width is then looked the demand of scanning rule and is set, and promptly the bank bit of each address is looked the scanning demand and set.
In addition; The a plurality of input data of this that physical layer device 10 received can be sent to memory circuit 20 and as reading the address; So memory circuit 20 promptly can read corresponding label data according to these a plurality of input data; That is to say that the input data can input to the address port (address port) of memory circuit 20 respectively, make memory circuit 20 distinguish the part position in the output label data according to the input data.With Fig. 3 is example; When if first data of the input data that memory circuit 20 is received are A; Because A is corresponding to the memory address 65 of memory circuit; So memory circuit 20 promptly can be according to the first position in the first data output label data, the memory address 65 of memory circuit 20 data of being stored just, memory circuit 20 can output 10000 in this embodiment.If second data of input data are B, memory circuit 20 is exported the data that memory address 66 is stored with comprehending correspondence, and obtains 01000.Wherein, a preferred embodiment of memory circuit 20 can be a static RAM.
Below just be that ABCDE is elaborated with the scan-data, after memory circuit 20 received the input data, if comprise ABCDE in these input data, then 20 of memory circuits can be exported operational data 10000,01000,00100,00010,00001 in regular turn.The trigger 32 that is to say computing circuit 20 can receive first data 10000 respectively; And the data that can be received according to clock signal clk displacement output to logical block 34 that next stage was connected in series; This moment, logical block 34 also can receive the next group data, and carried out logical operation, the trigger 32 that is connected in series to export to; This moment, data that second trigger 32 received were 1 in this embodiment; And will export the logical block 34 that next stage is connected in series to according to next clock signal clk displacement, but if second data of input data are not for B is C, second batch of operational data that this moment, memory circuit 20 was exported can be 00100; The data that this moment, second trigger 32 in the computing circuit 30 received can be 0, and expression input data do not meet scanning rule.That is to say that when if the operational data that receives in regular turn of computing circuit 30 meets scanning rule, the function of computing circuit 30 just down is shifted 1 of first operational data as understanding as the shift register.
The rest may be inferred; When the input data comprise ABCDE; In first the operational data 1 will be after the displacement through five clock signal clks, and can be 1 at the operation result of the 5th trigger 32 outputs, representes that also the partial data in this batch input data meets scanning rule ABCDE.Hence one can see that, if the 5th operation result that trigger 32 is exported is 0, then represents in the input data, not have to meet these regular data of ABCDE.Above-mentioned clock signal can be provided by external circuit or internal circuit, and this is well known for knowing this art, so no longer add to praise to state.
The present invention is a foundation with the scanning rule, lets each data of scanning rule correspond to the label data of memory circuit 20, just memory address respectively; And storage corresponding label section data position; And let memory circuit 20 according to the corresponding data of input data output, produce operation result through computing circuit 30 according to the data of memory circuit 20 outputs again, after judge operation results through judging unit 40 again; Can learn in the input data and whether comprise the data that meet scanning rule; The complexity that mode like this can be saved circuit, and then save cost, and can improve scan efficiency.In addition, decision circuitry 40 can set arbitrarily be will be with the output of which trigger 32 as logical data to judge, so the present invention has flexibility, the convenient use.
In addition; Decision circuitry 40 also comprises a counting unit 60; To be used for counting clock signal CLK; Decision circuitry 40 then can be learnt the position of data in the input data that meets scanning rule according to the count results of counting unit 60, to make things convenient for subsequent treatment when learning input section data data fit scanning rule.Counting unit 60 is arranged at decision circuitry 40 and is merely one embodiment of the invention, does not limit to counting unit 60 and only must be arranged at decision circuitry 40.
Consult Fig. 3 again; Because all triggers 32 of the computing circuit 30 among this embodiment are serially connected each other; So computing circuit 30 must separate when logical operation different scanning rule, influences the result of next scanning rule with the result who avoids a last scanning rule.The present invention also comprises many isolated locations 36, and isolated location 36 can be or lock in this embodiment.Isolated location 36 is between two triggers 32 and be coupled to the trigger 32 of prime and the logical block 34 between two triggers 32; Be used to receive a district at a distance from signal; To distinguish at a distance from next this scanning rule, wherein the district can or can be sent by outside other circuit by judging unit 40 at a distance from signal.If first scanning rule includes five scan-datas; Promptly must must isolate at the 5th trigger 32 and the 6th trigger 32; This moment, decision circuitry 40 was the sending area at a distance from signal to the isolated location of being located between the 5th trigger 32 and the 6th trigger 32 36; The district of this embodiment is 1 at a distance from signal, and so regardless of the output 1 or 0 of the 5th trigger 32, the output of isolated location 36 all is 1; The output of the logical block 34 between the 5th trigger 32 and the 6th trigger 32 then determines according to first data of next scanning rule; Promptly be that the data that the 6th trigger 32 is received are the data of next scanning rule, thus the 5th trigger 32 and the 6th trigger 32 can be isolated, with effective isolation scanning rule.
Connect saidly, decision circuitry 40 can freely be set isolated location 36 according to scanning rule size, so can dynamically set the length of scanning rule, with the flexibility of increase use.Present embodiment can be considered the saving cost, and computing circuit 30 can be set isolated location 36 according to fixed intervals, similarly be isolated location 36 to be set with 4 multiple or 6 multiple, with the complexity of simplifying circuit with save cost.Moreover; When if many scan-datas of scanning rule are less than the quantity that fixed intervals set; Unnecessary position then is unheeding data, promptly is set at 1, similarly is when with 6 multiple isolated location 36 being set; If during discontented 6 of many scan-datas of scanning rule, then can be unnecessary be set at 1 (don ' t care).
Please consult Fig. 4 in the lump, it is the calcspar of another preferred embodiment of the present invention.As shown in the figure; This embodiment only has a memory circuit 20 with different being in Fig. 2 of embodiment of Fig. 2; And this embodiment has one first memory circuit 22 and one second memory circuit 24; Wherein the memory capacity of first memory circuit 22 and second memory circuit 24 all less than the memory capacity of memory circuit 20, can reduce the capacity of memory circuit 20 through this configuration, and then reduces area occupied.This reason is that if a byte (8) is torn open be two 4; The scan-data of a byte like this just only need to launch 2^4 * 2=32 position; That is to say that only needing first memory circuit 22 and second memory circuit 24 of two degree of depth 16 is the memory circuit 20 of instead Fig. 2 embodiment; The capacity of two memory circuits 22,24 like this and the capacity of originally memory circuit 20 are compared following lacked many, so can save the shared area of memory circuit.
Moreover the scanning circuit of this embodiment also comprises a sequence units 26, and the input of sequence units 26 couples first memory circuit 22 and second memory circuit 24 respectively.When physical layer device 10 reception input data, can separate the input data and transfer to corresponding first memory circuit 22 and second memory circuit 24 respectively, to export corresponding data respectively.After again by the processing of sequence units 26, after the data that first memory circuit 22 and second memory circuit 24 are exported are gone here and there mutually, and then be sent to computing circuit 30, to be same as the subsequent treatment of Fig. 2 embodiment.
In sum; The scanning circuit of data of the present invention and method; It is by a plurality of label datas of memory circuitry stores; And each label data is corresponding to a sub-rule, and memory circuit is exported a first position and the second portion position in each label data respectively according to first data and second data; One computing circuit logical operation first position and second portion position, and produce an operation result; Whether one decision circuitry meets scanning rule according to this operation result with these input data of judgement.Can saving the complexity of circuit, and then save cost, and can improve scan efficiency and scanning flexibility.
Though the present invention with preferred embodiment openly as above, so it is not in order to limit the present invention.Those of ordinary skill under any in the technical field under the situation that does not break away from the spirit and scope of the present invention, can carry out various changes and modification.Therefore, protection scope of the present invention is as the criterion with the scope of the claim that proposed.
Claims (13)
1. a data scanning circuit is used for scanning input data and whether meets a rule, and these input data comprise one first data and one second data, and this data scanning circuit comprises:
One memory circuit; In order to store many batches of label datas; And each batch label data corresponds to a sub-rule; Wherein, this memory circuit reads address corresponding label data as a first position to export in every batch of label data with this as reading the address with these first data, and reads address corresponding label data as a second portion position to export in every batch of label data with this as reading the address with these second data;
One computing circuit is coupled to this memory circuit, in order to logical operation is carried out in this first position and this second portion position, to produce an operation result; And
One decision circuitry is coupled to this computing circuit, in order to according to this operation result judging whether these input data meet this rule,
Wherein this computing circuit comprises:
A plurality of triggers; And
A plurality of logical blocks are respectively coupled between these a plurality of triggers;
Wherein, These a plurality of triggers are exported this first position to these a plurality of logical blocks according to clock signal displacement; These a plurality of logical blocks carried out logical operation to this first position of being exported by this a plurality of trigger with this this second portion position of being exported by this memory circuit; To produce this operation result
Wherein each in the every batch of label data is distributed in this different memory circuit addresses, and
Wherein every batch of label data is the N position; And the N-1 of every batch of label data position corresponds to same logical value, and wherein in the N bit address of every batch of label data of storage of memory circuit, the corresponding memory address of the ASCII(American Standard Code for information interchange) corresponding with sub-rule is set at 1; All the other N-1 positions are set at 0
Wherein first data and second data are 1 byte, and N is 256.
2. data scanning circuit as claimed in claim 1, wherein these first data and this second data input to the address port of this memory circuit.
3. data scanning circuit as claimed in claim 1, wherein every batch of label data is a programmable label data.
4. data scanning circuit as claimed in claim 1, wherein these a plurality of logical blocks are and door.
5. data scanning circuit as claimed in claim 1 also comprises:
One counting unit meets the position that these regular data are arranged in these input data in order to count this clock signal to learn.
6. data scanning circuit as claimed in claim 1, wherein this sub-rule is represented a character.
7. data scanning circuit as claimed in claim 1, wherein this memory circuit is a static RAM.
8. data scanning circuit as claimed in claim 1 is arranged in the medium access controller.
9. a data scanning method is used for scanning input data and whether meets a rule, and these input data comprise one first data and one second data, and this data scanning method comprises:
Store many batches of label datas in a memory circuit, each batch label data corresponds to a sub-rule;
Read address corresponding label data as a first position to export in every batch of label data with this as reading the address with these first data;
Read address corresponding label data as a second portion position to export in every batch of label data with this as reading the address with these second data;
Logical operation is carried out to produce an operation result in this first position and this second portion position; And
Whether meet this rule according to this operation result with these input data of judgement,
Wherein in the step of logical operation, also comprise:
According to this first position of clock signal displacement, and carry out logical operation with this second portion position, producing this operation result,
Wherein each in the every batch of label data is distributed in the different storage addresss, and
Wherein every batch of label data is the N position; And the N-1 of this first label data position corresponds to same logical value; Wherein in the N bit address of every batch of label data of storage of memory circuit; The corresponding memory address of the ASCII(American Standard Code for information interchange) corresponding with sub-rule is set at 1, and all the other N-1 positions are set at 0
Wherein first data and second data are 1 byte, and N is 256.
10. data scanning method as claimed in claim 9, wherein these first data and this second data input to the address port of this memory circuit.
11. data scanning method as claimed in claim 9, wherein every batch of label data is a programmable label data.
12. scan method as claimed in claim 9 also comprises:
Count this clock signal and meet the position that these regular data are arranged in these input data to learn.
13. scan method as claimed in claim 9 is applied to a network management interchanger or a load balancer.
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| CN200710180299A CN101420417B (en) | 2007-10-26 | 2007-10-26 | Digital content scanning circuit and scanning method thereof |
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| CN200710180299A CN101420417B (en) | 2007-10-26 | 2007-10-26 | Digital content scanning circuit and scanning method thereof |
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| CN101420417B true CN101420417B (en) | 2012-08-29 |
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| TWI625534B (en) * | 2015-12-21 | 2018-06-01 | 瑞昱半導體股份有限公司 | Debug method executed via scan chain for scan test and related circuitry system |
| CN111652644A (en) * | 2020-06-01 | 2020-09-11 | 湖南快乐阳光互动娱乐传媒有限公司 | Advertisement strategy configuration method and system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004008701A1 (en) * | 2002-07-11 | 2004-01-22 | Taral Networks | Method and system for controlling messages in a communication network |
| US7076650B1 (en) * | 1999-12-24 | 2006-07-11 | Mcafee, Inc. | System and method for selective communication scanning at a firewall and a network node |
| CN1863211A (en) * | 2006-03-23 | 2006-11-15 | 华为技术有限公司 | Content filtering system and method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7076650B1 (en) * | 1999-12-24 | 2006-07-11 | Mcafee, Inc. | System and method for selective communication scanning at a firewall and a network node |
| WO2004008701A1 (en) * | 2002-07-11 | 2004-01-22 | Taral Networks | Method and system for controlling messages in a communication network |
| CN1863211A (en) * | 2006-03-23 | 2006-11-15 | 华为技术有限公司 | Content filtering system and method thereof |
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