JP2013088400A - Method for inspecting semiconductor integrated circuit, and the semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inspect random logic of a semiconductor integrated circuit by dynamically changing an inner clock of the semiconductor integrated circuit while supplying only a clock of a fixed frequency to the clock of the semiconductor integrated circuit.SOLUTION: An inspection method of a semiconductor integrated circuit including a plurality of combination circuits and a plurality of scan flip-flops composing a scan chain for performing scan tests of the plurality of combination circuits includes: an input step for inputting a first clock of a fixed frequency from a clock generation device to the semiconductor integrated circuit; a frequency division step for generating a second clock by dividing the frequency of the first clock by a frequency divider included in the semiconductor integrated circuit; and an inspection step for inspecting the semiconductor integrated circuit while dynamically switching a clock to be inputted to the plurality of scan flip-flops between the first clock and the second clock.

Description

  The present technology relates to a semiconductor integrated circuit inspection method and a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit inspection method including a logic circuit and a scan flip-flop that performs a scan test of the plurality of logic circuits, and the semiconductor integrated circuit. .

  In recent years, the circuit scale of a system LSI (Large Scale Integration) has been steadily increasing, and the test time of the system LSI has also increased with the increase in circuit scale. Therefore, various ideas such as DFT (Design For Testability) have been made to shorten the test time. DFT is a design method that facilitates testing of a system LSI, and one of them is a scan test that uses random logic as a test target.

  However, the system LSI often has a plurality of clock domains having a plurality of different operating frequencies, and in the scan test, it is desirable to perform a test at an operating frequency that matches the operating frequency of each clock domain of the LSI. Thus, for example, Patent Document 1 discloses a technique in which a tester for testing a system LSI is provided with a plurality of delay test circuits so that clocks having different operating frequencies can be selectively input.

JP2011-89914A

  However, some types of testers cannot switch and output a plurality of clocks, and even in the tester described in Patent Document 1 described above, a clock input to a specific scan FF is constant. The clock input to a specific scan FF was not dynamically changed.

  The present technology has been made in view of the above-described problems. The random logic of the semiconductor integrated circuit is changed by dynamically changing the internal clock of the semiconductor integrated circuit while supplying only a clock having a constant frequency to the clock of the semiconductor integrated circuit. It aims at providing the inspection method which can be inspected.

  In order to solve the above problems, a method for inspecting a semiconductor integrated circuit according to the present technology includes a plurality of combinational circuits, a plurality of scan flip-flops constituting a scan chain for performing a scan test of the plurality of combinational circuits, And an input step of inputting a first clock having a constant frequency from a clock generator to the semiconductor integrated circuit, and a frequency divider built in the semiconductor integrated circuit includes the first clock. Frequency dividing step of generating a second clock by dividing the clock and a clock input to the plurality of scan flip-flops while dynamically switching between the first clock and the second clock, the semiconductor integrated circuit And an inspection process for inspecting.

  The semiconductor integrated circuit inspection method described above is implemented as part of another method, realized as a semiconductor integrated circuit inspection apparatus having means corresponding to each process, or a semiconductor integrated circuit inspected by the inspection method described above. Various aspects such as being realized as a circuit are included. The present technology can also be realized as an inspection system including the inspection apparatus and a semiconductor integrated circuit, a program that causes a computer to realize functions corresponding to the configuration of the method described above, a computer-readable recording medium that records the program, and the like. Is possible.

  According to the present technology, it is possible to inspect the random logic of the semiconductor integrated circuit by dynamically changing the internal clock of the semiconductor integrated circuit while supplying only the clock of the constant frequency to the clock of the semiconductor integrated circuit.

It is a figure explaining the semiconductor integrated circuit which can perform a scan test. It is a block diagram which shows schematic structure of a scan flip-flop. FIG. 3 is a main part circuit diagram showing a configuration of an LSI to be tested in the first embodiment. 3 is a timing chart for explaining the operation of the LSI according to the first embodiment. 3 is a timing chart for explaining the operation of the LSI according to the first embodiment. It is a principal part circuit diagram which shows the structure of LSI used as the test object in 2nd Example. 6 is a timing chart for explaining the operation of an LSI according to a second embodiment. 6 is a timing chart for explaining the operation of an LSI according to a second embodiment.

Hereinafter, embodiments of the present technology will be described in the following order.
(1) Configuration of the present embodiment:
(2) First embodiment of test method for semiconductor integrated circuit:
(3) Second embodiment of test method for semiconductor integrated circuit:
(4) Summary:

(1) Configuration of the present embodiment:
FIG. 1 is a diagram for explaining a semiconductor integrated circuit (LSI) capable of executing a scan test. The LSI 100 shown in the figure includes input terminals In1 to In3, output terminals Out1 to Out3, an operation switching signal input terminal In4, a scan-in terminal In5, a scan-out terminal Out4, an internal circuit 10, and a scan chain 20. It is equipped with.

  An LSI is an example of a semiconductor integrated circuit. The configuration of the LSI 100 shown in FIG. 1 is an example, and the number of various terminals, the number of combinational circuits included in the internal circuit 10, the number of flip-flops, the number of scan chains described later, and the like can be changed as appropriate. is there.

  The internal circuit 10 is constructed by various logic circuits, performs a predetermined calculation based on input data input from the input terminals In1 to In3 of the LSI 100, and outputs the output data as the calculation result to the output terminals Out1 to Out3. To do.

  In the present embodiment, the logic circuit of the internal circuit 10 includes a plurality of flip-flops (hereinafter abbreviated as FF) and a plurality of combinational circuits. A combinational circuit is a circuit in which the output reacts immediately to the input. The output of such a circuit is independent of the order in which the inputs are added, and is not related to the state of the circuit before the inputs are added. Unrelated.

  Here, at least some of the plurality of FFs are configured as scan flip-flops (hereinafter abbreviated as scan FFs). For example, when testing an LSI by the partial scan method, a part of the plurality of FFs is a scan FF, and when testing the LSI by the full scan method, all of the plurality of FFs are scan FFs. The scan FF is an FF in which a multiplexer is added to an internal (core logic) data line, and has a multiplexer function. Note that the FFs 20a to 20f shown in FIG. 1 are all configured as scan FFs.

  The FFs 20 a to 20 f shown in FIG. 1 are serially connected, and a series of serially connected FFs constitutes a scan chain 20. The scan chain 20 connects the scan-in terminal In5 and the scan-out terminal Out4.

  A clock signal is supplied to the FFs 20a to 20f constituting the scan chain 20, and functions as a shift register that operates in synchronization with the clock. That is, the FFs 20a to 20f sequentially shift the data Scan_in input to the scan-in terminal In5 in the connection order of the scan chain 20, and output the data Scan_out from the scan-out terminal Out4. Note that the supply of the clock signal to the FF will be described in detail in a first embodiment and a second embodiment to be described later, and the description is omitted here.

  The plurality of combinational circuits included in the internal circuit 10 can be grouped into, for example, three combinational circuit groups 10a, 10b, and 10c with the scan chain 20 as a reference. In the present embodiment, a plurality of combinations surrounded by the scan chain 20 is referred to as a combination circuit group 10b, and a plurality of combinations located closer to the input terminals In1 to In3 than the scan chain 20 is referred to as a combination circuit group 10a. A plurality of combinations located closer to the output terminals Out1 to Out3 than the scan chain 20 will be referred to as a combinational circuit group 10c. That is, the combinational circuit group 10b is an inspection target using the scan chain 20 in the present embodiment.

  In other words, among the FFs 20a to 20f constituting the scan chain 20, the FFs 20a to 20c are arranged on the input side of the combinational circuit group 10b, and are FFs that input data to the combinational circuit group 10b. On the other hand, the FFs 20d to 20f are arranged on the output side of the combinational circuit group 10b, and are FFs to which data is input from the combinational circuit group 10b. Therefore, when the data set in the FFs 20a to 20c is input to the combinational circuit group 10b, the combinational circuit group 10b executes an operation based on the data and outputs the result data, and the result data is stored in the FFs 20d to 20f. It will be.

Here, an example of the configuration of the scan FF will be described.
FIG. 2 is a block diagram showing a schematic configuration of the scan FF. The scan FF has a configuration similar to that of a so-called normal FF and a selector therein, and inputs two data input terminals and a signal for instructing the selector to switch the data input terminals. An operation switching terminal, a clock terminal for inputting a clock signal, and one data output terminal are provided. In the scan FF shown in the figure, the D terminal T1 and the SI terminal T2 constitute an input terminal, the TEN terminal T3 constitutes an operation switching terminal, the Q terminal T4 constitutes a data output terminal, and the CK terminal T5 constitutes a clock terminal. Configure.

  The D terminal T1 is connected to the combinational circuit group 10a when the scan FFs are the FFs 20a to 20c in FIG. 1, and is connected to the combinational circuit group 10b when the scan FFs are the FFs 20d to 20f in FIG. That is, operation result data output from the combinational circuit group is input to the D terminal T1. When the selector in the scan FF is switched to the D terminal T1, the scan FF outputs data corresponding to the input from the combinational circuit group 10a to the D terminal from the Q terminal T4.

  The Q terminal T4 is a data output terminal of the scan FF, and is connected to the scan FF arranged in the next stage of the scan FF in the scan chain 20 and further connected to the combinational circuit. In the configuration example of FIG. 1, the Q terminals T4 of the FFs 20a to 20c arranged on the input side of the combinational circuit group 10b are connected to the combinational circuit group 10b and arranged on the output side of the combinational circuit group 10b. The 20f Q terminal T4 is connected to the combinational circuit group 10c.

  The SI terminal T2 is connected to the Q terminal T4 of the scan FF arranged in the preceding stage in the scan chain 20 when the scan FF is the FFs 20a to 20f in FIG. However, in the scan FF arranged at the start end of the scan chain 20, the SI terminal T2 is connected to the scan-in terminal In5.

  When the selector inside the scan FF is switched so as to select the SI terminal T2, the scan FF functions as a shift register and is output from the Q terminal T4 of the scan FF arranged in the preceding stage of the scan FF in the scan chain 20. The latched data is latched and the data latched inside is output from the Q terminal T4. As a result, the data output from the Q terminal T4 is input to the SI terminal of the scan FF arranged in the next stage of the scan FF in the scan chain 20.

  The TEN terminal T3 is an input terminal for the operation switching signal T_Scan_en, and is connected to the TEN terminal 260 of the tester 200 shown in the first and second embodiments described later. The tester 200 can switch and output a shift signal for instructing a shift operation and a capture signal for instructing a capture operation as an operation switching signal. When the shift signal is input to the TEN terminal T3, the scan FF outputs the data input from the SI terminal T2 to the Q terminal T4 in synchronization with the clock, and when the capture signal is input to the TEN terminal T3, The data inputted from the D terminal T1 is subjected to a predetermined calculation and outputted to the Q terminal T4 in synchronization with the data.

  That is, when a shift signal is input to the TEN terminal T3 of each scan FF constituting the scan chain 20, the scan chain 20 functions as a shift register, and every time the clock signal supplied to the CK terminal T5 rises or falls, The input to the SI terminal T2 is latched, and the data latched so far is output to the scan FF arranged in the next stage of the scan FF in the scan chain 20. As a result, data is sequentially shifted in the scan chain 20 in synchronization with the clock input to the CK terminal T5.

  On the other hand, when a capture signal is input to the TEN terminal T3 of each scan FF constituting the scan chain 20, the scan chain 20 performs a predetermined operation as a part of the internal circuit 10. That is, when the scan FF does not function as a shift register, data output from the Q terminal T4 is input to the combinational circuit group 10b or the combinational circuit group 10c.

  Next, the timing relationship with the clock in the operation test (so-called scan test) of the LSI 100 will be described while appropriately explaining the clock signal supplied to each part of the LSI 100.

(2) First embodiment of test method for semiconductor integrated circuit:
FIG. 3 is a principal circuit diagram showing the configuration of the LSI to be tested in the first embodiment, and FIGS. 4 and 5 are timing charts for explaining the operation of the LSI according to the first embodiment. FIG. 3 also shows a tester for testing the LSI. In FIG. 3, the LSI 300 includes a scan chain 320, a frequency divider 330, a selector circuit 340, a clock mask circuit 350, a CK terminal 360, a TEN terminal 370, a scan-in terminal 380, and a scan-out terminal 390.

  The frequency divider 330, the selector circuit 340, and the clock mask circuit 350 function as a clock control unit that controls switching of the clock supplied to each scan FF constituting the scan chain 320.

  The CK terminal 360, the TEN terminal 370, and the scan-in terminal 380 are input terminals, and the scan-out terminal 390 is an output terminal. In addition, various combinational circuits may be provided, and some combinational circuits are illustrated in FIG.

  As described above, the scan chain 320 is constructed by connecting a series of scan FFs, and performs a predetermined operation on an input signal input from one combinational circuit group and outputs it to the other combinational circuit group. And a function as a shift register that connects between the scan-in terminal 380 and the scan-out terminal 390.

  Data Scan_in is input to the scan-in terminal 380 from the terminal 270 of the tester 200, and data Scan_out output from the scan-out terminal 390 is input to the terminal 280 of the tester 200. The tester 200 can test whether the combinational circuit group to be tested of the scan chain 320 operates correctly by analyzing the data Scan_out output based on the data Scan_in output from the terminal 270.

  The CK terminal 360 is a terminal for inputting a constant speed clock signal CLK_in to the LSI 300. In the present embodiment, the CK terminal 360 receives a single clock signal (hereinafter also referred to as an input clock CLK_in) from the terminal 250 of the tester 200. The input clock CLK_in input to the CK terminal 360 is input to the frequency divider 330 and the selector circuit 340.

  Here, the input clock CLK_in is desirably the highest frequency (maximum clock) among the operating frequencies of the circuits included in the LSI 300. When a clock with the maximum maximum frequency is input, the input clock CLK_in is divided in the LSI 300, thereby generating clock signals of all frequencies required in the LSI 300 within the LSI 300, and a single frequency input clock. Based on CLK_in, a clock suitable for each internal circuit can be selectively used.

  For example, the frequency divider 330 appropriately divides the input clock CLK_in, supplies a high-speed clock signal to an internal circuit premised on high-speed operation, and operates at a high speed on an internal circuit premised on low-speed operation. It is possible to selectively use clocks by supplying a clock signal and operating at a low speed.

  However, depending on the performance of the tester 200, it may not be possible to output more than the highest frequency among the operating frequencies of the circuits included in the LSI 300. In such a case, the input clock CLK_in is an upper limit frequency that can be input to the LSI 300 by comprehensively considering the highest frequency that the tester 200 can output and the highest frequency among the operating frequencies of the circuits included in the LSI 300. Select.

  This is because if the input clock CLK_in having the highest possible frequency is supplied, the frequency range that can be generated when the input clock CLK_in is divided in the LSI 300 can be as wide as possible. Accordingly, clock signals having almost all the frequencies required in the LSI 300 can be generated inside the LSI 300.

  That is, the frequency divider 330 appropriately divides the input clock CLK_in, supplies a high-speed clock signal to the internal circuit premised on the high-speed operation, and operates the high-speed operation on the internal circuit premised on the low-speed operation. It is possible to selectively use clocks by supplying a clock signal and operating at a low speed.

  The frequency divider 330 is configured by a counter circuit using, for example, an FF, and can generate a clock signal slower than the input clock CLK_in by down-counting based on the input clock CLK_in input to the CK terminal 360. The generated clock signal is input to the selector circuit 340.

  In the present embodiment, the case where the frequency divider 330 outputs a clock signal obtained by dividing the input clock CLK_in by 2 will be described as an example. However, the frequency divider 330 of course has an appropriate frequency divided clock of 3 or more divided. It can be configured to output. Hereinafter, a clock signal generated and output by the frequency divider 330 based on the input clock CLK_in will be referred to as a frequency-divided clock CLK_div.

  As described above, the input clock CLK_in is appropriately divided on the LSI 300 side while a single frequency is input, and the divided clock CLK_div is generated and used for the test of the LSI 300. Therefore, the operating frequency of the scan chain 320 is limited. Thus, the external clock frequency can be increased.

  Also, since the internal clock is generated not by the PLL that requires a stable waiting time but by the frequency divider 330 that does not require a stable waiting time, the tester occupation time can be shortened and the test cost can be reduced.

  In addition, since the clock frequency can be properly used for the capture operation and shift operation, each operation can be executed at a more appropriate clock frequency, and the capture operation can be speeded up or circuits with different capture operation frequencies can be tested simultaneously. become able to. As a result, the delay fault detection rate is improved.

  The TEN terminal 370 is a terminal for inputting an operation switching signal T_Scan_en that controls switching between the shift operation and the capture operation in the scan chain 320. In the present embodiment, the tester 200 inputs an operation switching signal T_Scan_en from the TEN terminal 260 to the TEN terminal 370.

  The operation switching signal T_Scan_en input to the TEN terminal 370 is wired to be input to the TEN terminal of each scan FF constituting the scan chain 320. Therefore, the tester 200 can switch and control the operation of each scan FF constituting the scan chain 320 between the shift operation and the capture operation. The TEN terminal 370 constitutes a clock switching control terminal in the first embodiment, and the operation switching signal T_Scan_en is an example of a clock switching control signal.

  In the present embodiment, the scan chain 320 performs a shift operation when the operation switching signal T_Scan_en is High (1), and performs a capture operation when the operation switching signal T_Scan_en is Low (0).

  Here, the shift operation refers to a state in which the scan chain 320 functions as a shift register. That is, in the shift operation, an arbitrary value is set to a desired scan FF by sequentially inputting predetermined data from the scan-in terminal 380, or data input to the scan FF from the internal circuit (combination circuit) is sequentially shifted. Thus, the data can be sequentially output from the scan-out terminal 390.

  On the other hand, the capture operation refers to a state in which each scan FF constituting the scan chain 320 executes a predetermined operation in the internal circuit. In the capture operation, among the scan FFs constituting the scan chain 320, the value set in the scan FF arranged on the input side of the predetermined combination circuit constituting the internal circuit is input to the predetermined combination circuit for processing. The result data is received and held by the scan FF arranged on the output side of the predetermined combinational circuit.

  That is, when the capture operation is performed, the result data output from the combinational circuit group to be inspected with respect to predetermined data input can be acquired. By analyzing the result data, it is possible to determine whether the operation of the combinational circuit group is normal or abnormal.

  As described above, the selector circuit 340 receives the input clock CLK_in, the divided clock CLK_div, and the clock selection signal CLK_sel, and selectively outputs any one of the clock signals specified by the clock selection signal CLK_sel. .

  The selector circuit 340 uses the operation switching signal T_Scan_en described above as the clock selection signal CLK_sel, and the clock selection signal CLK_sel is also switched in response to the switching of the operation switching signal T_Scan_en.

  In the example shown in FIG. 4, when the operation switching signal T_Scan_en instructs a shift operation (High (1)), the divided clock CLK_div is output, and when the operation switching signal T_Scan_en instructs a capture operation. (Low (0)), the input clock CLK_in is output.

  As a result, the selector circuit 340 outputs the composite clock CLK_pls in which an edge is generated at the period of the divided clock CLK_div during the shift operation and an edge is generated at the period of the input clock CLK_in during the capture operation.

  In the example shown in FIG. 5, when the operation switching signal T_Scan_en instructs a shift operation (High (1)), the input clock CLK_in is output, and when the operation switching signal T_Scan_en instructs a capture operation. (Low (0)) outputs the divided clock CLK_div.

  As a result, the selector circuit 340 outputs the composite clock CLK_pls in which an edge is generated at the cycle of the input clock CLK_in during the shift operation and an edge is generated at the cycle of the divided clock CLK_div during the capture operation. Note that the synthesized clock CLK_pls is a transient clock signal and is not shown in FIGS.

  The clock mask circuit 350 generates a clock mask signal CLK_msk and superimposes the clock mask signal CLK_msk on the combined clock signal CLK_pls. The clock mask signal CLK_msk is a signal for masking a predetermined portion of the synthesized clock signal CLK_pls when switching between the shift operation and the capture operation.

  The clock mask circuit 350 can be composed of, for example, a flip-flop 351, an exclusive OR circuit 352, and an OR circuit 353.

  The flip-flop 351 receives the operation switching signal T_Scan_en, and outputs a delay signal T_Scan_en ′ obtained by delaying the operation switching signal T_Scan_en for a predetermined time.

  The exclusive OR circuit 352 receives the operation switching signal T_Scan_en and the delay signal T_Scan_en ′ and generates a clock mask signal CLK_msk based on these signals.

  The OR circuit 353 receives the combined clock signal CLK_pls and the clock mask signal CLK_msk output from the selector circuit 340, and outputs the scan clock signal CLK_sc obtained by superimposing the clock mask signal CLK_msk on the combined clock signal CLK_pls. .

  The scan clock signal CLK_sc generated in this way is High only for a predetermined period immediately after the shift operation and the capture operation are switched, and becomes a signal for masking the edge of the combined clock signal CLK_pls in this predetermined period.

  The scan clock signal CLK_sc is input to the CK terminal of each scan FF constituting the scan chain 320, and each scan FF operates with the clock of the scan clock signal CLK_sc.

  As a result, the shift register constructed by the scan chain 320 shifts data at the same operating frequency as the divided clock CLK_div when the shift operation is selected, and the input clock CLK_in when the capture operation is selected. Shift data at the same operating frequency. That is, although only a single input clock CLK_in is input from the tester 200, the LSI 300 can be operated at a plurality of operating frequencies.

  Further, since a mask period without an edge in the scan clock is provided for a predetermined period immediately after the shift operation and the capture operation are switched, data is not shifted, and glitches are prevented when the capture operation and the shift operation are switched. be able to.

[When the capture operation is faster than the scan operation]
Next, the relationship between the data input to the scan-in terminal 380 and the clock signal or control signal will be described with reference to FIG. FIG. 4 illustrates a case where the capture operation can be performed with a high-speed clock in the LSI 300 as compared with the scan operation.

  In FIG. 4, when data A is input to the scan-in terminal 380, a shift operation is instructed from the tester 200. That is, a high (1) operation switching signal T_Scan_en is input from the tester 200. At this time, the clock selection signal CLK_sel is also High (1), and an edge is generated in the scan clock CLK_sc in the same cycle as the divided clock CLK_div.

  At this time, a shift operation is performed in which data of the shift chain 320 is shifted in synchronization with the divided clock CLK_div, and data is output from the scan-out terminal 390 in synchronization with the divided clock CLK_div. In this embodiment, since data is output at the rising edge of the clock, in FIG. 4, data is output from the scan-out terminal 390 at the timing of F and G.

  Next, when the input of the data A to the scan-in terminal 380 is completed, the shift operation is switched to the capture operation. That is, the operation switching signal T_Scan_en changes from High (1) to Low (0). At this time, the clock selection signal CLK_sel is also Low (0), and an edge occurs in the scan clock CLK_sc in the same cycle as the input clock CLK_in. This is because the capture operation can be performed at a higher speed than the scan operation.

  Here, immediately after the clock selection signal CLK_sel changes from High (1) to Low (0), the clock mask signal CLK_msk is superimposed on the scan clock CLK_sc. Accordingly, no edge occurs in the scan clock signal CLK_sc during that time, and the FF waits for data output to the combinational circuit group 10b during the mask period, thereby preventing a glitch that occurs when the capture operation and the shift operation are switched. it can. Note that dummy data is input from the tester 200 to the scan-in terminal 380 while the scan clock CLK_sc is masked.

  The clock mask signal CLK_msk is also input to the frequency divider 330 via an input path (not shown in FIG. 3), and the frequency divider 330 has its edge reset by the clock mask signal CLK_msk. That is, the count of the frequency divider 330 is reset at the falling timing of the clock mask signal CLK_msk, and a new count is started.

  Therefore, the frequency-divided clock CLK_div output from the frequency divider 330 does not depend on the logical value of the frequency-divided clock CLK_div that has been output until just before that, and then the frequency-divided clock CLK_div again in the order of High → Low → High →. CLK_div is output.

  Following the dummy data, data B, C, and D are sequentially input to the scan-in terminal 380. However, since the LSI 300 is performing a capture operation at this time, the scan chain 320 is invalid, and the scan-in terminal 380 is also operating as a normal data terminal. Accordingly, the data B, C, and D input to the scan-in terminal 380 are not input to the scan chain 320 but are input to the combinational circuit group 10b, for example.

  At this time, data output from the combinational circuit group 10b by the capture operation is output from the scan-out terminal 390 in synchronization with the input clock CLK_in. In FIG. 4, data is output from the scan-out terminal 390 at the timing of H, I, and J.

  When the input of data B, C, and D is completed, the capture operation is switched to the shift operation. That is, the operation switching signal T_Scan_en changes from Low (0) to High (1). At this time, the clock selection signal CLK_sel also becomes Hihg (1), and an edge is generated in the scan clock CLK_sc in the same cycle as the divided clock CLK_div.

  Immediately after the clock selection signal CLK_sel changes from Low (0) to High (1), the clock mask signal CLK_msk is superimposed on the scan clock CLK_sc. Accordingly, no edge occurs in the scan clock signal CLK_sc during that time, and the FF waits for data output to the combinational circuit group 10b during the mask period, thereby preventing a glitch that occurs when the capture operation and the shift operation are switched. it can. Note that dummy data is input from the tester 200 to the scan-in terminal 380 while the scan clock CLK_sc is masked.

  The clock mask signal CLK_msk is also input to the frequency divider 330 as described above, and the frequency divider 330 has its edge reset by the clock mask signal CLK_msk. That is, the frequency divider 330 starts a new count from the falling timing of the clock mask signal CLK_msk.

  Subsequently to the dummy data, data E is input to the scan-in terminal 380. At this time, the scan chain 320 shifts data in synchronization with the divided clock CLK_div, and executes a shift operation of outputting data from the scan-out terminal 390 in synchronization with the divided clock CLK_div. In FIG. 4, data is output from the scan-out terminal 390 at the timing K.

  As described above, since the scan clock CLK_sc is generated using the input clock CLK_in input from the outside to the LSI 300 and the divided clock CLK_div generated inside the LSI 300, each of the capture operation and the shift operation is performed. It is possible to perform an internal inspection of the LSI 300 using an optimal clock. Further, since the mask signal is superimposed on the scan clock CLK_sc when the capture operation and the shift operation are switched, a glitch that occurs when the capture operation and the shift operation are switched can be prevented. Further, since the divided clock CLK_div generated inside the LSI 300 by the clock mask signal CLK_msk is reset, the generation timing of the divided clock High and Low can be reset when the capture operation and the shift operation are switched.

[When scan operation is faster than capture operation]
Next, another example of the relationship between the data input to the scan-in terminal 380, the clock signal, and the control signal will be described with reference to FIG. FIG. 5 illustrates a case where the scan operation can be performed with a high-speed clock in the LSI 300 as compared with the capture operation.

  In FIG. 5, when data A is input to the scan-in terminal 380, a shift operation is instructed from the tester 200. That is, a high (1) operation switching signal T_Scan_en is input from the tester 200. At this time, the clock selection signal CLK_sel is Low (0), and an edge is generated in the scan clock CLK_sc in the same cycle as the input clock CLK_in.

  At this time, the shift operation of shifting the data of the shift chain 320 in synchronization with the input clock CLK_in and outputting the data from the scan-out terminal 390 in synchronization with the input clock CLK_in is executed. In this embodiment, since data is output at the rising edge of the clock, data is output from the scan-out terminal 390 at the timings of K and L in FIG.

  Next, when the input of the data A to the scan-in terminal 380 is completed, the shift operation is switched to the capture operation. That is, the operation switching signal T_Scan_en changes from High (1) to Low (0). At this time, the clock selection signal CLK_sel changes to Hihg (1), and an edge is generated in the scan clock CLK_sc in the same cycle as the divided clock CLK_div. This is because the capture operation is executed at a lower speed than the scan operation.

  Here, immediately after the clock selection signal CLK_sel changes from Low (0) to High (1), the clock mask signal CLK_msk is superimposed on the scan clock CLK_sc. Accordingly, no edge occurs in the scan clock signal CLK_sc during that time, and the FF waits for data output to the combinational circuit group 10b during the mask period, thereby preventing a glitch that occurs when the capture operation and the shift operation are switched. it can. Note that dummy data is input from the tester 200 to the scan-in terminal 380 while the scan clock CLK_sc is masked.

  Further, since the edge of the frequency divider 330 is reset by the clock mask signal CLK_msk, the count of the frequency divider 330 is reset at the falling timing of the clock mask signal CLK_msk, and a new count is started.

  Following the dummy data, data B and C are sequentially input to the scan-in terminal 380. However, since the LSI 300 is performing a capture operation at this time, the scan chain 320 is invalid, and the scan-in terminal 380 is also operating as a normal data terminal. Therefore, the data B and C input to the scan-in terminal 380 are not input to the scan chain 320 but are input to the combinational circuit group 10b, for example.

  At this time, data output from the combinational circuit group 10b by the capture operation is output from the scan-out terminal 390 in synchronization with the input clock CLK_in. In FIG. 5, data is output from the scan-out terminal 390 at the timing of M and N.

  When the input of data B and C is completed, the capture operation is switched to the shift operation. That is, the operation switching signal T_Scan_en changes from Low (0) to High (1). At this time, the clock selection signal CLK_sel becomes Low (0), and an edge is generated in the scan clock CLK_sc in the same cycle as the input clock CLK_in.

  Immediately after the clock selection signal CLK_sel changes from High (1) to Low (0), the clock mask signal CLK_msk is superimposed on the scan clock CLK_sc. Accordingly, no edge occurs in the scan clock signal CLK_sc during that time, and the FF waits for data output to the combinational circuit group 10b during the mask period, thereby preventing a glitch that occurs when the capture operation and the shift operation are switched. it can. Note that dummy data is input from the tester 200 to the scan-in terminal 380 while the scan clock CLK_sc is masked.

  The clock mask signal CLK_msk is also input to the frequency divider 330 as described above, and the frequency divider 330 has its edge reset by the clock mask signal CLK_msk. That is, the frequency divider 330 starts a new count from the falling timing of the clock mask signal CLK_msk.

  Subsequently to the dummy data, data E is input to the scan-in terminal 380. At this time, the shift chain 320 performs a shift operation of shifting data in synchronization with the input clock CLK_in and outputting data from the scan-out terminal 390 in synchronization with the input clock CLK_in. In FIG. 5, data is output from the scan-out terminal 390 at the timing O.

  As described above, since the scan clock CLK_sc is generated using the input clock CLK_in input from the outside to the LSI 300 and the divided clock CLK_div generated inside the LSI 300, each of the capture operation and the shift operation is performed. It is possible to perform an internal inspection of the LSI using an optimal clock. Further, since the mask signal is superimposed on the scan clock CLK_sc when the capture operation and the shift operation are switched, a glitch that occurs when the capture operation and the shift operation are switched can be prevented. Further, since the divided clock CLK_div generated inside the LSI 300 by the clock mask signal CLK_msk is reset, the generation timing of the divided clock High and Low can be reset when the capture operation and the shift operation are switched.

(3) Second embodiment of test method for semiconductor integrated circuit:
FIG. 6 is a principal circuit diagram showing the configuration of the LSI to be tested in the second embodiment, and FIGS. 7 and 8 are timing charts for explaining the operation of the LSI according to the second embodiment.
In FIG. 6, an LSI 400 includes a scan chain 420, a frequency divider 430, a selector circuit 440, a clock mask circuit 450, a CK terminal 460, a TEN terminal 470, a scan-in terminal 480, a scan-out terminal 490, and a PLL (Phase Locked Loop) circuit. 500.

  The units 420, 430, and 450 to 490 constituting the LSI 400 have the same configuration as the units 320, 330, and 350 to 390 in the LSI 300 of the first embodiment described above. . Further, since the tester 200 is the same as that of the first embodiment described above, the same reference numerals as those of the first embodiment are given and the description thereof is omitted.

  The PLL circuit 500 receives an input clock CLK_in, and oscillates a PLL clock signal CLK_pll having a predetermined frequency based on the input clock CLK_in. However, since the PLL circuit 500 requires several hundred milliseconds for stable oscillation, it cannot be used at the beginning of the test of the semiconductor integrated circuit.

  Therefore, in the second embodiment, by using the selector circuit 440 described later, the test is performed using the input clock CLK_in and the divided clock CLK_div separately at the initial stage of the test, so that the PLL circuit 500 can stably oscillate. Then, the test is performed while switching the clock using the PLL clock CLK_pll.

  The selector circuit 440 receives the input clock CLK_in, the divided clock CLK_div, the PLL clock CLK_pll, and the clock selection signal CLK_sel, and selectively outputs any one clock signal specified by the clock selection signal CLK_sel.

  The clock selection signal CLK_sel input to the selector circuit 440 according to the second embodiment is a signal that rises or falls (hereinafter sometimes referred to as an edge) when the clock is switched.

  The selector circuit 440 includes an edge detection circuit for the clock selection signal CLK_sel and a counter circuit. When the selector circuit 440 detects an edge of the clock selection signal CLK_sel, the selector circuit 440 switches the output clock among the input clock CLK_in, the divided clock CLK_div, and the PLL clock CLK_pll.

  That is, the selector circuit 440 outputs the divided clock CLK_div when detecting the first edge of the clock selection signal CLK_sel, outputs the input clock CLK_in when detecting the second edge, and detects the third edge. Then, the PLL clock CLK_pll is output.

  Thereafter, the clock output every time an edge is detected is output by switching the input clock CLK_in, the divided clock CLK_div, and the PLL clock CLK_pll in order. These three types of clocks can be selected from the outside. In FIG. 6, the PLL clock can be designated by 0, the input clock by 2, and the divided clock by 1.

  In the example shown in FIG. 7, when the operation switching signal T_Scan_en instructs a shift operation (High (1)), the frequency-divided clock CLK_div is output, and when the operation switching signal T_Scan_en instructs a capture operation. (Low (0)), the input clock CLK_in or the PLL clock CLK_pll is output.

  As a result, the selector circuit 440 outputs the composite clock CLK_pls in which an edge is generated at the period of the divided clock CLK_div during the shift operation and an edge is generated at the period of the input clock CLK_in or the PLL clock CLK_pll during the capture operation.

  In the example shown in FIG. 8, when the operation switching signal T_Scan_en instructs the shift operation (Hihg (1)), the input clock CLK_in is output, and the operation switching signal T_Scan_en instructs the capture operation. (Low (0)) outputs the divided clock CLK_div or the PLL clock CLK_pll.

  As a result, the selector circuit 440 outputs a composite clock CLK_pls in which an edge is generated at the cycle of the input clock during the shift operation and an edge is generated at the cycle of the divided clock CLK_div or the PLL clock CLK_pll during the capture operation.

  The synthesized clock CLK_pls is a transient clock signal and is not shown in FIGS. In the second embodiment, the case where the LSI is tested by dynamically changing the clock in the capture operation will be described. Of course, the LSI is tested by dynamically changing the clock in the shift operation. May be.

  The clock mask circuit 450 superimposes the clock mask signal CLK_msk on the synthesized clock signal CLK_pls to generate a scan clock signal CLK_sc. Therefore, the scan clock signal CLK_sc is a signal in which the edge of the combined clock signal CLK_pls is masked in a predetermined period immediately after the shift operation and the capture operation are switched.

  The scan clock signal CLK_sc is input to the CK terminal of each scan FF constituting the scan chain 420, and each scan FF operates with the clock of the scan clock signal CLK_sc.

  As a result, the shift register constructed by the scan chain 420 shifts data at the same operating frequency as the divided clock CLK_div when the shift operation is selected, and the input clock CLK_in or when the capture operation is selected. Data is shifted at the same operating frequency as the PLL clock CLK_pll. That is, although only a single input clock CLK_in is input from the tester 200, the LSI 400 can be operated at a plurality of operating frequencies.

  Further, since a mask period without an edge in the scan clock is provided for a predetermined period immediately after the shift operation and the capture operation are switched, data is not shifted, and glitches are prevented when the capture operation and the shift operation are switched. be able to.

[When the capture operation is faster than the scan operation]
Next, the relationship between the data input to the scan-in terminal 480 and the clock signal or control signal will be described with reference to FIG. FIG. 7 illustrates the case where the capture operation can be performed with a high-speed clock in the LSI 400 as compared with the scan operation.

  In FIG. 7, when data A is input to the scan-in terminal 480, a shift operation is instructed from the tester 200. That is, a high (1) operation switching signal T_Scan_en is input from the tester 200. At this time, the clock selection signal CLK_sel is 1, and an edge is generated in the scan clock CLK_sc in the same cycle as the divided clock CLK_div.

  At this time, the shift operation of shifting the data of the shift chain 420 in synchronization with the divided clock CLK_div and outputting the data from the scan-out terminal 490 in synchronization with the divided clock CLK_div is executed. In this embodiment, since data is output at the rising edge of the clock, data is output from the scan-out terminal 390 at the timing of H and I in FIG.

  Next, when the input of data A to the scan-in terminal 480 is completed, the shift operation is switched to the capture operation. That is, the operation switching signal T_Scan_en changes from High (1) to Low (0). At this time, the clock selection signal CLK_sel changes from 1 to 2, and an edge occurs in the scan clock CLK_sc in the same cycle as the input clock CLK_in. This is because the capture operation can be performed at a higher speed than the scan operation.

  Here, immediately after the clock selection signal CLK_sel changes from 1 to 2, the clock mask signal CLK_msk is superimposed on the scan clock CLK_sc. Accordingly, no edge occurs in the scan clock signal CLK_sc during that time, and the FF waits for data output to the combinational circuit group 10b during the mask period, thereby preventing a glitch that occurs when the capture operation and the shift operation are switched. it can. Note that dummy data is input from the tester 200 to the scan-in terminal 480 while the scan clock CLK_sc is masked.

  The clock mask signal CLK_msk is also input to the frequency divider 430 via an input path (not shown in FIG. 6), and the frequency divider 430 is reset by the clock mask signal CLK_msk. That is, the count of the frequency divider 430 is reset at the falling timing of the clock mask signal CLK_msk, and a new count is started.

  Following the dummy data, data B, C, and D are sequentially input to the scan-in terminal 480. However, since the LSI 400 is performing a capture operation at this time, the scan chain 420 is disabled, and the scan-in terminal 480 is also operating as a normal data terminal. Accordingly, the data B, C, and D input to the scan-in terminal 480 are not input to the scan chain 420 but are input to the combinational circuit group 10b, for example.

  At this time, data output from the combinational circuit group 10b by the capture operation is output from the scan-out terminal 490 in synchronization with the input clock CLK_in. In FIG. 7, data is output from the scan-out terminal 490 at the timing of J, K, and L.

  When the input of data B, C, and D is completed, the PLL clock CLK_pll is changed to be used instead of the input clock CLK_in that has been used in the capture operation so far. That is, the clock selection signal CLK_sel is changed from 2 to 0. As a result, an edge is generated in the scan clock CLK_sc at the same cycle as that of the PLL clock CLK_pll.

  In FIG. 7, for the sake of illustration, the PLL clock CLK_pll has the same clock speed as the input clock CLK_in. Of course, if there is a clock more suitable for the capture operation than the input clock CLK_in, the PLL clock CLK_pll The clock speed can be appropriately set to a speed suitable for the capture operation.

  Thus, immediately after the clock selection signal CLK_sel changes from 2 to 0, the clock mask signal CLK_msk is superimposed on the scan clock CLK_sc. Accordingly, no edge is generated in the scan clock signal CLK_sc during that period, and the FF waits for data output to the combinational circuit group 10b during the mask period, thereby preventing a glitch that occurs when the input clock is switched. Note that dummy data is input from the tester 200 to the scan-in terminal 480 while the scan clock CLK_sc is masked.

  The clock mask signal CLK_msk is also input to the frequency divider 430 as described above, and the frequency divider 430 has its edge reset by the clock mask signal CLK_msk. That is, the frequency divider 430 starts a new count from the falling timing of the clock mask signal CLK_msk.

  Subsequently to the dummy data, data E, F, and G are sequentially input to the scan-in terminal 480. Also at this time, since the LSI 400 is performing the capture operation, the scan chain 420 is invalid, and the scan-in terminal 480 is also operating as a normal data terminal. Accordingly, the data E, F, and G input to the scan-in terminal 480 are not input to the scan chain 420. For example, the data E, F, and G input to the combination circuit 10b and output from the combination circuit 10b by the capture operation are input clocks. The signal is output from the scan-out terminal 490 in synchronization with CLK_pll. In FIG. 7, data is output from the scan-out terminal 490 at the timing of M, N, and O.

  As described above, since the scan clock CLK_sc is generated using the input clock CLK_in input from the outside to the LSI 400 and the divided clock CLK_div and the PLL clock CLK_pll generated inside the LSI 300, the capture operation and the shift are performed. An internal inspection of the LSI can be performed using a clock that is optimal for each operation. Further, since the mask signal is superimposed on the scan clock CLK_sc when the capture operation and the shift operation are switched, a glitch that occurs when the capture operation and the shift operation are switched can be prevented. Further, since the divided clock CLK_div generated inside the LSI 400 by the clock mask signal CLK_msk is reset, the generation timing of the divided clock High and Low can be reset when the capture operation and the shift operation are switched.

[When scan operation is faster than capture operation]
Next, another example of the relationship between data input to the scan-in terminal 480 and a clock signal or control signal will be described with reference to FIG. FIG. 8 illustrates a case where the scan operation can be performed with a high-speed clock in the LSI 400 as compared with the capture operation.

  In FIG. 8, when data A and B are sequentially input to the scan-in terminal 480, a shift operation is instructed from the tester 200. That is, a high (1) operation switching signal T_Scan_en is input from the tester 200. At this time, the clock selection signal CLK_sel is 1, and an edge occurs in the scan clock CLK_sc in the same cycle as the input clock CLK_in.

  Therefore, a shift operation is performed in which data in the shift chain 420 is shifted in synchronization with the input clock CLK_in, and data is output from the scan-out terminal 490 in synchronization with the input clock CLK_in. In this embodiment, since data is output at the rising edge of the clock, in FIG. 8, data is output from the scan-out terminal 490 at the timings E, F, and G.

  Next, when the input of the data A and B to the scan-in terminal 480 is completed, the shift operation is switched to the capture operation. That is, the operation switching signal T_Scan_en changes from High (1) to Low (0). At this time, the clock selection signal CLK_sel changes from 2 to 1, and an edge is generated in the scan clock CLK_sc in the same cycle as the divided clock CLK_div. This is because the capture operation is executed at a lower speed than the scan operation.

  Here, immediately after the clock selection signal CLK_sel changes from 2 to 1, the clock mask signal CLK_msk is superimposed on the scan clock CLK_sc. Accordingly, no edge occurs in the scan clock signal CLK_sc during that time, and the FF waits for data output to the combinational circuit group 10b during the mask period, thereby preventing a glitch that occurs when the capture operation and the shift operation are switched. it can. Note that dummy data is input from the tester 200 to the scan-in terminal 480 while the scan clock CLK_sc is masked.

  Further, since the edge of frequency divider 430 is reset by clock mask signal CLK_msk, the count of frequency divider 430 is reset at the falling timing of clock mask signal CLK_msk, and a new count is started.

  Following the dummy data, data C is input to the scan-in terminal 480. However, since the LSI 400 is performing a capture operation at this time, the scan chain 420 is disabled, and the scan-in terminal 480 is also operating as a normal data terminal. Therefore, the data C input to the scan-in terminal 480 is not input to the scan chain 420 but is input to the combinational circuit group 10b, for example.

  At this time, data output from the combinational circuit group 10b by the capture operation is output from the scan-out terminal 490 in synchronization with the divided clock CLK_div. In FIG. 8, data is output from the scan-out terminal 490 at the H timing.

  When the input of the data C is completed, the PLL clock CLK_pll is changed to be used instead of the divided clock CLK_div used so far in the capture operation. That is, the clock selection signal CLK_sel is changed from 1 to 0. As a result, an edge is generated in the scan clock CLK_sc at the same cycle as that of the PLL clock CLK_pll.

  In FIG. 8, for convenience of illustration, the PLL clock CLK_pll is shown as the same clock speed as the divided clock CLK_div. However, of course, if there is a clock more suitable for the capture operation than the divided clock CLK_div, The clock speed of the PLL clock CLK_pll can be appropriately set to a speed suitable for the capture operation.

  Thus, immediately after the clock selection signal CLK_sel changes from 1 to 0, the clock mask signal CLK_msk is superimposed on the scan clock CLK_sc. Accordingly, no edge occurs in the scan clock signal CLK_sc during that time, and the FF waits for data output to the combinational circuit group 10b during the mask period, thereby preventing a glitch that occurs when the capture operation and the shift operation are switched. it can. Note that dummy data is input from the tester 200 to the scan-in terminal 480 while the scan clock CLK_sc is masked.

  The clock mask signal CLK_msk is also input to the frequency divider 430 as described above, and the frequency divider 430 has its edge reset by the clock mask signal CLK_msk. That is, the frequency divider 430 starts a new count at the falling timing of the clock mask signal CLK_msk.

  Subsequently to the dummy data, data D is input to the scan-in terminal 480. Also at this time, since the LSI 400 is performing the capture operation, the scan chain 420 is invalid, and the scan-in terminal 480 is also operating as a normal data terminal. Accordingly, the data D input to the scan-in terminal 480 is not input to the scan chain 420 but is input to the combinational circuit group 10b, for example. Data output from the combinational circuit group 10b by the capture operation is output from the scan-out terminal 490 in synchronization with the PLL clock CLK_pll. In FIG. 8, data is output from the scan-out terminal 490 at the timing I.

  As described above, since the scan clock CLK_sc is generated using the input clock CLK_in input from the outside to the LSI 400 and the divided clock CLK_div and the PLL clock CLK_pll generated inside the LSI 400, the capture operation and the shift are performed. An internal inspection of the LSI 400 can be performed using a clock that is optimal for each operation. Further, since the mask signal is superimposed on the scan clock CLK_sc when the capture operation and the shift operation are switched, a glitch that occurs when the capture operation and the shift operation are switched can be prevented. Further, since the divided clock CLK_div generated inside the LSI 400 by the clock mask signal CLK_msk is reset, the generation timing of the divided clock High and Low can be reset when the capture operation and the shift operation are switched.

(4) Summary:
From this embodiment described above, at least the following technical ideas can be grasped.

(A) An inspection method of a semiconductor integrated circuit having a plurality of combinational circuits and a plurality of scan flip-flops constituting a scan chain for performing a scan test of the plurality of combinational circuits,
An input step of inputting a first clock having a constant frequency from a clock generator to the semiconductor integrated circuit;
A frequency dividing step in which a frequency divider incorporated in the semiconductor integrated circuit divides the first clock to generate a second clock;
An inspection step of inspecting the semiconductor integrated circuit while dynamically switching a clock input to the plurality of scan flip-flops between the first clock and the second clock;
A method for inspecting a semiconductor integrated circuit comprising:

(B) The semiconductor integrated circuit inspection method according to (a), wherein the frequency divider includes a flip-flop that is not included in the scan chain.

(C) The first clock is the larger of the maximum clock that can be output by the clock generation device or the maximum clock among the operating frequencies of the circuits included in the semiconductor integrated circuit (a) or ( The inspection method of the semiconductor integrated circuit as described in b).

(D) The capture operation in the scan test uses the first clock,
The inspection method for a semiconductor integrated circuit according to any one of (a) to (c), wherein the second clock is used for the shift operation in the scan test.

(E) Immediately after the capture operation and the shift operation are switched, and immediately after the first clock and the second clock are switched, the edges of the clocks input to the plurality of scan flip-flops are masked (d The method for inspecting a semiconductor integrated circuit according to (1).

(F) The semiconductor integrated circuit includes a clock control unit that changes the frequency of the second clock according to control from the outside,
The semiconductor device according to any one of (a) to (e), wherein in the frequency dividing step, the clock control unit controls the frequency of the second clock in accordance with control from the outside of the semiconductor integrated circuit. Integrated circuit inspection method.

(G) The semiconductor integrated circuit includes a PLL (Phase Looped Lock) circuit,
In the dividing step, the frequency divider divides the first clock to generate the second clock until the PLL circuit is stabilized, and after the PLL circuit is stabilized, the PLL circuit is The method for inspecting a semiconductor integrated circuit according to any one of (a) to (f), wherein the second clock is generated from a first clock.

(H) a semiconductor integrated circuit having a plurality of combinational circuits and a plurality of scan flip-flops constituting a scan chain for performing a scan test of the plurality of combinational circuits,
An input terminal for inputting a first clock having a constant frequency from a clock generator to the semiconductor integrated circuit;
A frequency divider that divides the first clock to generate a second clock;
A clock switching control terminal for receiving an input of the clock switching control signal from the outside;
A clock switching control unit that dynamically switches a clock input to the plurality of scan flip-flops between the first clock and the second clock based on the clock switching control signal;
A semiconductor integrated circuit comprising:

(I) A semiconductor integrated circuit inspection device having a plurality of combinational circuits and a plurality of scan flip-flops constituting a scan chain for performing a scan test of the plurality of combinational circuits,
A clock output terminal for inputting a first clock having a constant frequency to an input terminal of the semiconductor integrated circuit;
A clock input to the plurality of scan flip-flops when the semiconductor integrated circuit performs the scan test includes at least the first clock and a frequency divider provided in the semiconductor integrated circuit. A clock switching control signal output terminal for outputting a switching control signal for dynamically switching between a second clock generated based on the clock;
Semiconductor integrated circuit inspection apparatus comprising:

  Note that the scope of the present technology is not limited to the above-described embodiments and modification examples, and the configurations disclosed in the above-described embodiment and modification examples are replaced with each other or the combination is changed, known techniques, and Configurations in which the configurations disclosed in the above-described embodiments and modifications are mutually replaced or combinations thereof are also included. Needless to say, the scope of the present technology extends to the matters described in the claims and equivalents thereof.

DESCRIPTION OF SYMBOLS 10 ... Internal circuit, 10a-10c ... Combination circuit group, 20 ... Scan chain, 20a-20f ... Flip-flop (FF), 100 ... Semiconductor integrated circuit (LSI), In1-In3 ... Input terminal, In5 ... Scan-in Terminal, In4 ... operation switching signal input terminal, Out1 to Out3 ... output terminal, Out4 ... scan-out terminal, T1 ... D terminal, T2 ... SI terminal, T3 ... TEN terminal, T4 ... Q terminal, T5 ... CK terminal, 200 ... Tester, 250 ... terminal, 260 ... TEN terminal, 270 ... terminal, 280 ... terminal, 300 ... LSI, 320 ... scan chain, 330 ... frequency divider, 340 ... selector circuit, 350 ... clock mask circuit, 351 ... flip-flop, 352 ... Exclusive OR circuit, 353 ... OR circuit, 360 ... CK terminal, 370 ... TEN terminal 380 ... Scan-in terminal, 390 ... Scan-out terminal, 400 ... LSI, 420 ... Scan chain, 430 ... Frequency divider, 440 ... Selector circuit, 450 ... Clock mask circuit, 451 ... Flip-flop, 452 ... Exclusive OR Circuit, 453 ... logical sum circuit, 460 ... CK terminal, 470 ... TEN terminal, 480 ... scan-in terminal, 490 ... scan-out terminal, 500 ... PLL circuit,

Claims (9)

A method for inspecting a semiconductor integrated circuit having a plurality of combinational circuits and a plurality of scan flip-flops constituting a scan chain for performing a scan test of the plurality of combinational circuits,
An input step of inputting a first clock having a constant frequency from a clock generator to the semiconductor integrated circuit;
A frequency dividing step in which a frequency divider incorporated in the semiconductor integrated circuit divides the first clock to generate a second clock;
An inspection step of inspecting the semiconductor integrated circuit while dynamically switching a clock input to the plurality of scan flip-flops between the first clock and the second clock;
A method for inspecting a semiconductor integrated circuit comprising:   The semiconductor integrated circuit inspection method according to claim 1, wherein the frequency divider includes a flip-flop that is not included in the scan chain.   2. The semiconductor integrated circuit according to claim 1, wherein the first clock is a larger one of a maximum clock that can be output by the clock generation device or a maximum clock among operating frequencies of circuits included in the semiconductor integrated circuit. Circuit inspection method. The capture operation in the scan test uses the first clock,
The semiconductor integrated circuit inspection method according to claim 1, wherein the second clock is used for the shift operation in the scan test.   5. The edge of a clock input to the plurality of scan flip-flops is masked immediately after switching between the capture operation and the shift operation and immediately after the first clock and the second clock are switched. Inspection method for semiconductor integrated circuit. The semiconductor integrated circuit includes a clock control unit that changes the frequency of the second clock according to control from the outside,
2. The semiconductor integrated circuit inspection method according to claim 1, wherein, in the frequency dividing step, the clock control unit controls the frequency of the second clock in accordance with control from the outside of the semiconductor integrated circuit. The semiconductor integrated circuit includes a PLL (Phase Locked Loop) circuit,
In the dividing step, the frequency divider divides the first clock to generate the second clock until the PLL circuit is stabilized, and after the PLL circuit is stabilized, the PLL circuit is The semiconductor integrated circuit inspection method according to claim 1, wherein the second clock is generated from a first clock. A semiconductor integrated circuit having a plurality of combinational circuits and a plurality of scan flip-flops constituting a scan chain for performing a scan test of the plurality of combinational circuits,
An input terminal for inputting a first clock having a constant frequency from a clock generator to the semiconductor integrated circuit;
A frequency divider that divides the first clock to generate a second clock;
A clock switching control terminal for receiving an input of the clock switching control signal from the outside;
A clock switching control unit that dynamically switches a clock input to the plurality of scan flip-flops between the first clock and the second clock based on the clock switching control signal;
A semiconductor integrated circuit comprising: An inspection apparatus for a semiconductor integrated circuit having a plurality of combinational circuits and a plurality of scan flip-flops constituting a scan chain for performing a scan test of the plurality of combinational circuits,
A clock output terminal for inputting a first clock having a constant frequency to an input terminal of the semiconductor integrated circuit;
A clock input to the plurality of scan flip-flops when the semiconductor integrated circuit performs the scan test includes at least the first clock and a frequency divider provided in the semiconductor integrated circuit. A clock switching control signal output terminal for outputting a switching control signal for dynamically switching between a second clock generated based on the clock;
Semiconductor integrated circuit inspection apparatus comprising:

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