JP4662520B2 - Scan test circuit, scan test method, and semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a scan test circuit and a scan test method, and more particularly to a scan test circuit and a scan test method for testing a semiconductor integrated circuit (LSI) at an actual operation speed.
[0002]
[Background Art and Problems to be Solved by the Invention]
A scan test is known as a method for testing the inside of an LSI. In general, the scan test is performed by synchronizing the internal circuit of the LSI and the external input / output unit with the same clock. Normally, the internal circuit of an LSI can operate at a high speed, whereas the operation speed of the external input / output unit of the LSI is lower. For this reason, the speed of the scan test is limited by the operation speed of the external input / output unit of the LSI. Therefore, in the case of an LSI that operates at a high speed, it is difficult to perform a timing test (for example, a delay fault inspection) that checks whether an internal circuit operates correctly at an actual operation speed by a scan test. On the other hand, when the timing test is performed by a method other than the scan test, the test pattern becomes enormous. In addition, an expensive tester is required.
[0003]
In recent years, several approaches for performing a timing test such as a delay fault inspection by a scan test have been made. For this purpose, not only the test can be performed at a high speed but also a highly accurate cycle time is required.
[0004]
JP-A-2-247586 discloses a technique for speeding up a scan test by providing FIFO memories before and after a scan chain.
[0005]
An object of the present invention is to provide a scan test circuit and a scan test method capable of testing an LSI operating at a high speed at an actual operation speed.
[0006]
[Means for Solving the Problems]
According to one aspect of the present invention, the scan test circuit includes a first scan chain and a selector. The selector selectively supplies test data or output data of the first scan chain to an input of the first scan chain. The first scan chain has a shift mode and a capture mode. In the shift mode, the first scan chain shifts data supplied to the input by the selector in synchronization with the first clock or the second clock. The second clock has a higher frequency than the frequency of the first clock. In the capture mode, the first scan chain captures the output for the test data from the test object in synchronization with the second clock.
[0007]
In the scan test circuit, first, test data is given to the input of the first scan chain by the selector. The first scan chain enters the shift mode, and the test data given to the input by the selector is shifted in synchronization with the first clock. As a result, test data is set in the first scan chain.
[0008]
The selector then provides the output data of the first scan chain to the input of the first scan chain. Thereby, a loop is formed between (output of the first scan chain) − (selector) − (input of the first scan chain). The first scan chain remains in the shift mode, and the set test data is shifted in synchronization with the second clock. Here, since a loop is formed between (output of the first scan chain) − (selector) − (input of the first scan chain), the test data output from the first scan chain passes through the selector. Given to the input of the scan chain. That is, the test data set in the first scan chain circulates on the loop in synchronization with the second clock. While the test data circulates on the loop, the second clock is stabilized.
[0009]
Next, the first scan chain enters the capture mode, and the output (test result) for the test data from the test object is captured in synchronization with the second clock. As a result, the test data stored in the first scan chain is replaced with the test result. Then, the first scan chain again enters the shift mode, and the test result is output to the outside in synchronization with the first clock.
[0010]
As described above, the scan test circuit sets test data in the first scan chain in synchronization with the first clock, and synchronizes with the second clock having a frequency higher than the frequency of the first clock. Thus, the test result can be taken into the first scan chain. Therefore, even if the operation speed of the semiconductor integrated circuit (LSI) to be tested is high, it is possible to perform a timing test (for example, a delay fault inspection) to check whether the internal circuit operates correctly at the actual operation speed. it can.
[0011]
Further, a loop is formed between (output of the first scan chain)-(selector)-(input of the first scan chain), and the test data set in the first scan chain is circulated on this loop. be able to. As a result, a highly accurate timing test can be performed while the second clock is stable.
[0012]
Moreover, since an expensive tester is not required, an increase in test cost can be suppressed.
[0013]
Preferably, the scan test circuit further includes capture signal generation means. The capture signal generating means outputs an active capture signal after the first period has elapsed since the data given to the input of the first scan chain by the selector is switched from the test data to the output data of the first scan chain. Output for the period. The first scan chain enters the capture mode in response to the active capture signal from the capture signal generating means, and enters the shift mode in response to the inactive capture signal.
[0014]
In the scan test circuit, first, test data is given to the input of the first scan chain by the selector. The capture signal generating means outputs an inactive capture signal. In response to the inactive capture signal, the first scan chain enters the shift mode, and the test data given to the input by the selector is shifted in synchronization with the first clock. As a result, test data is set in the first scan chain.
[0015]
The selector then provides the output data of the first scan chain to the input of the first scan chain. Thereby, a loop is formed between (output of the first scan chain) − (selector) − (input of the first scan chain). Subsequently, the capture signal generating means outputs an inactive capture signal. The first scan chain remains in the shift mode, and the set test data is shifted in synchronization with the second clock. That is, the test data set in the first scan chain circulates on the loop in synchronization with the second clock.
[0016]
When the first period elapses after the output data of the first scan chain is supplied to the input of the first scan chain, the capture signal generating means outputs an active capture signal. In response to the active capture signal, the first scan chain enters the capture mode, and the output (test result) for the test data from the test object is captured in synchronization with the second clock. As a result, the test data stored in the first scan chain is replaced with the test result.
[0017]
When the active capture signal is output for the second period, the capture signal generating means outputs an inactive capture signal. In response to the inactive capture signal, the first scan chain again enters the shift mode, and the test result is output to the outside in synchronization with the first clock.
[0018]
In an LSI operating at high speed, it is difficult to control the switching of the scan chain shift mode / capture mode from the outside in response to the actual operating speed of the LSI. However, in the scan test circuit, the shift mode / capture mode of the first scan chain is switched in response to the capture signal from the capture signal generating means. For this reason, it is not necessary to directly control switching of the shift mode / capture mode of the first scan chain from the outside. Therefore, even an LSI that operates at high speed can be easily tested at an actual operation speed.
[0019]
Preferably, the scan test circuit further includes a clock switching unit. The clock switching means selectively supplies the first clock or the second clock to the first scan chain.
[0020]
Preferably, the clock switching means supplies the second clock to the first clock for a predetermined period in response to switching of data applied to the input of the first scan chain by the selector from the test data to the output data of the first scan chain. The first clock is supplied to the first scan chain when the predetermined period elapses.
[0021]
In the scan test circuit, since the clock switching means is provided, it is not necessary to directly control switching of the clock supplied to the first scan chain from the outside. Therefore, even an LSI that operates at high speed can be easily tested at an actual operation speed.
[0022]
Preferably, the scan test circuit further includes hold signal generating means. The hold signal generating means is a period from when the first scan chain changes from the capture mode to the shift mode and immediately after a predetermined period elapses until immediately before the scan-out by the first scan chain. give. The first scan chain continues to hold data without performing a shift operation while receiving an active hold signal from the hold signal generating means.
[0023]
In the scan test circuit, when the first scan chain changes from the capture mode to the shift mode, the test result taken into the first scan chain is (output of the first scan chain) − (selector) − (first Circulates in synchronization with the second clock on the loop formed between the inputs of the scan chain. When a predetermined period elapses after the first scan chain changes from the capture mode to the shift mode, the hold signal generating means gives an active hold signal to the first scan chain. While receiving the active hold signal, the first scan chain continues to hold the test result without shifting. After the hold signal from the hold signal generating means is switched from active to inactive, the first scan chain outputs the held test result serially to the outside in synchronization with the first clock (scanout). To do. The order of the test results scanned out (output to the outside) is the order of the test results stored in the scan chain when the active hold signal is given to the first scan chain. Therefore, by setting the predetermined period (the period from when the first scan chain is changed from the capture mode to the shift mode until the active hold signal is given to the first scan chain) to an appropriate period, the output is performed to the outside. The order of the test results to be performed can be in a desired order.
[0024]
Preferably, the scan test circuit further includes clock counting means. The clock counting means counts the number of second clocks applied to the first scan chain after the first scan chain changes from the capture mode to the shift mode.
[0025]
In the scan test circuit, when the first scan chain changes from the capture mode to the shift mode, the test result taken into the first scan chain is (output of the first scan chain) − (selector) − (first Circulates in synchronization with the second clock on the loop formed between the inputs of the scan chain. When a predetermined period elapses after the first scan chain changes from the capture mode to the shift mode, the first scan chain outputs the held test result serially to the outside in synchronization with the first clock ( Scan out). The order of the test results output to the outside deviates according to the number of second clocks given to the first scan chain during the predetermined period. The number of second clocks given to the first scan chain during the predetermined period is counted by the clock counting means. Accordingly, it is possible to correct a shift in the order of the test results output to the outside.
[0026]
Preferably, the clock counting means includes a second scan chain. The second scan chain is connected in series with the first scan chain. When the second clock is applied to the first scan chain, the second scan chain holds the number of second clocks to be counted. When the first clock is supplied to the first scan chain, the second scan chain shifts the value to be held in synchronization with the first clock.
[0027]
In the scan test circuit, the number of the second clock given to the first scan chain during the predetermined period is held in the second scan chain. The first and second scan chains connected in series are externally synchronized with the first clock by synchronizing the test result and the number of second clocks given to the first scan chain during the predetermined period. Output serially.
[0028]
According to another aspect of the present invention, the scan test method includes steps (a) to (d). In step (a), test data is scanned into the scan chain in synchronization with the first clock. In step (b), a loop is formed by applying the output from the scan chain to the input of the scan chain, and the test data is synchronized with the second clock having a higher frequency than the first clock on the loop. Shift for a predetermined period. In step (c), the output for the test data from the test object, that is, the test result is taken into the scan chain in synchronization with the second clock. In step (d), the test result is scanned out.
[0029]
In the scan test method, the test data is scanned into the scan chain in synchronization with the first clock, and the first scan chain is synchronized with the second clock having a frequency higher than the frequency of the first clock. Capture test results. Therefore, even if the operation speed of the semiconductor integrated circuit (LSI) to be tested is high, it is possible to perform a timing test (for example, a delay fault inspection) to check whether the internal circuit operates correctly at the actual operation speed. it can.
[0030]
Further, a loop is formed by giving the output from the scan chain to the input of the scan chain, and the test data is shifted on the loop for a predetermined period in synchronization with the second clock. As a result, a highly accurate timing test can be performed while the second clock is stable.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.
[0032]
(First embodiment)
<Configuration>
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit device (LSI) according to the first embodiment of the present invention. The LSI 1 shown in FIG. 1 is designed to be scanned, and includes a sequential circuit 100, a selector 201, a test control circuit 202, a scan input terminal 11, a control signal input terminal 12, a clock input terminal 13, and a scan output terminal 14. With.
[0033]
Test data SIN is given to the scan input terminal 11 from the outside. A control signal START is supplied to the control signal input terminal 12 from the outside. A clock CK is supplied to the clock input terminal 13 from the outside. The test result SOUT is output from the scan output terminal 14 to the outside.
[0034]
The test control circuit 202 generates a loop signal LP and a capture signal CAPT based on the control signal START from the control signal input terminal 12. Specifically, the test control circuit 202 outputs an H level loop signal LP when the control signal START is at an H level (logic high level), and is at an L level when the control signal START is at an L level (logic low level). The loop signal LP is output. In addition, the test control circuit 202 has a second period (here, six clock cycles of the clock CK) after the first period (here, six clock cycles of the clock CK) has elapsed since the control signal START changes from the L level to the H level. The clock signal CK is one clock cycle.) The H level capture signal CAPT is output, and otherwise, the L level capture signal CAPT is output.
[0035]
The sequential circuit 100 is a circuit to be subjected to a scan test, and includes a combinational circuit 110 and scan flip-flops ff1 to ff6. The scan flip-flops ff1 to ff6 are obtained by replacing the normal flip-flops included in the sequential circuit 100 so that the scan operation can be performed. By replacing in this way, complete controllability and observability are added to the flip-flops in the sequential circuit 100, and the sequential circuit 100 can be handled as the combinational circuit 110. The scan flip-flops ff1-ff6 are flip-flops that can perform a scan operation. The scan flip-flops ff1 to ff6 are connected in series like a shift register and operate in synchronization with the clock CK from the clock input terminal 13. The scan flip-flops ff1 to ff6 connected in this way are called a scan chain 120. The scan chain 120 functions as a shift register in the shift mode of the scan test, and functions as a mere flip-flop for realizing the function of the sequential circuit 100 in the capture mode and the normal operation. The scan chain 120 enters the shift mode or the capture mode in response to the capture signal CAPT from the test control circuit 202. Specifically, the scan chain 120 enters the capture mode in response to the H level capture signal CAPT, and enters the shift mode in response to the L level capture signal CAPT.
[0036]
In response to the loop signal LP from the test control circuit 202, the selector 201 outputs the test data SIN from the scan input terminal 11 or the output of the scan chain 120 (output of the scan flip-flop ff6) to the input of the scan chain 120 (scan flip-flop). Input to ff1). Specifically, the selector 201 applies test data SIN from the scan input terminal 11 to the input of the scan chain 120 in response to the L level loop signal LP, and responds to the H level loop signal LP in response to the scan chain 120. The output is applied to the input of the scan chain 120.
[0037]
Of the LSI 1 configured as described above, the scan chain 120, the selector 201, and the test control circuit 202 constitute a scan test circuit.
[0038]
<Scan test procedure>
A scan test procedure by the scan test circuit shown in FIG. 1 will be described with reference to FIG.
[0039]
(1) Period from time t0 to time t1
A clock CK having a frequency lower than the actual operation speed of the LSI 1 is applied to the clock input terminal 13. An L level control signal START is applied to the control signal input terminal 12. In response to the L level control signal START, the test control circuit 202 outputs an L level loop signal LP and an L level capture signal CAPT. Test data SIN (D1-D6 in this case) is serially applied to the scan input terminal 11 in synchronization with the clock CK. The selector 201 supplies test data D 1 -D 6 from the scan input terminal 11 to the input of the scan chain 120. The scan chain 120 shifts the test data D1-D6 from the selector 201 in synchronization with the clock CK. As a result, the test data D1-D6 are set in the scan flip-flops ff6-ff1.
[0040]
As described above, in this scan test circuit, the test data SIN (D1-D6) given to the scan input terminal 11 is transferred to the scan chain 120 in synchronization with the clock CK having a frequency lower than the actual operation speed of the LSI 1. Set. Thus, setting the test data SIN given to the scan input terminal 11 in the scan chain 120 in synchronization with the clock CK is called “scan-in”.
[0041]
(2) Period from time t1 to time t2
Clock supply from the outside to the clock input terminal 13 is stopped. This is to prevent malfunction of the LSI 1 at the time of clock switching. Also, during this period, the control signal START applied to the control signal input terminal 12 is switched from the L level to the H level. In response to this, the test control circuit 202 switches the loop signal LP from the L level to the H level. In response to the H level loop signal LP, the selector 201 provides the output of the scan chain 120 to the input of the scan chain 120. As a result, a loop is formed between (output of scan chain 120) − (selector 201) − (input of scan chain 120).
[0042]
(3) Period from time t2 to time t3
A clock CK having a frequency equal to the actual operating speed of the LSI 1 is applied to the clock input terminal 13. Control signal START and loop signal LP are at the H level, and capture signal CAPT is at the L level. The test data D1-D6 stored in the scan flip-flops ff6-ff1 of the scan chain 120 are shifted in synchronization with the clock CK having a frequency equal to the actual operation speed of the LSI 1. Here, since a loop is formed between (output of the scan chain 120) − (selector 201) − (input of the scan chain 120), the data output from the scan flip-flop ff6 is passed through the selector 201 to the scan flip-flop. It is input to ff1. That is, the test data D1-D6 on the scan chain 120 circulates on the above loop in synchronization with the clock CK equal to the actual operating speed of the LSI 1. Here, since the first period is 6 clock cycles, the period from time t2 to time t3 is 6 clock cycles. Accordingly, the test data D1-D6 is set again in the scan flip-flops ff6-ff1 at time t3.
[0043]
While the test data D1-D6 circulates on the above loop, the clock CK having a frequency equal to the actual operation speed of the LSI 1 is stabilized. Thereby, a timing test (for example, a delay fault inspection etc.) can be performed stably and with high accuracy.
[0044]
Although the first period is 6 clock cycles here, this period can be arbitrarily set. For example, when a longer period is required until the clock CK becomes stable, it can be set to 12 clock cycles or 18 clock cycles. Further, the test data stored in the scan flip-flops ff1 to ff6 at time t3 changes according to the first period. For example, when the first period is 7 clock cycles, the test data D2-D6 and D1 are stored in the scan flip-flops ff6-ff1 at time t3. Therefore, the first period can be set according to the test data stored in the scan flip-flops ff1 to ff6, which is necessary for the clock CK to be stable.
[0045]
(4) Period from time t3 to time t4
Subsequently, a clock CK having a frequency equal to the actual operation speed of the LSI 1 is supplied to the clock input terminal 13. Since the first period (6 clock cycles) has elapsed from the time when the control signal START changes from the L level to the H level, the test control circuit 202 performs the second period (here, one clock from time t3 to time t4). Cycle) The H level capture signal CAPT is output. In response to the H level capture signal CAPT, the scan chain 120 enters the capture mode. In the scan chain 120 in the capture mode, the outputs R1-R6 (test results) of the combinational circuit 110 for the test data D1-D6 are taken into the scan flip-flops ff6-ff1. As a result, the test data D1-D6 stored in the scan flip-flops ff6-ff1 are replaced with the test results R1-R6. Thus, capturing the outputs R1-R6 (test results) of the combinational circuit 110 for the test data D1-D6 into the scan flip-flops ff6-ff1 is referred to as “capture”.
[0046]
(5) Period from time t4 to time t5
The test control means 202 outputs an L level capture signal CAPT. The loop signal LP remains at the H level. Therefore, the test results R1-R6 captured in the scan flip-flops ff6-ff1 during the period from time t3 to time t4 are between (output of scan chain 120) − (selector 201) − (input of scan chain 120). The formed loop circulates in synchronization with a clock CK having a frequency equal to the actual operating speed of the LSI 1. Here, the period from time t4 to time t5 is 6 clock cycles. Accordingly, the test results R1-R6 are set again in the scan flip-flops ff6-ff1 at time t5.
[0047]
(6) Period from time t5 to time t6
Clock supply from the outside to the clock input terminal 13 is stopped. This is to prevent malfunction of the LSI 1 at the time of clock switching. Also, during this period, the control signal START applied to the control signal input terminal 12 is switched from the H level to the L level. In response to this, the test control circuit 202 switches the loop signal LP from the H level to the L level.
[0048]
(7) Period from time t6 to time t7
A clock CK having a frequency slower than the actual operation speed of the LSI 1 is applied to the clock input terminal 13. Further, the control signal START, the loop signal LP, and the capture signal CAPT are at the L level. The scan chain 120 shifts the test results R1-R6 stored in the scan flip-flops ff6-ff1 in synchronization with the clock CK. As a result, the test result SOUT (R1-R6) is serially output from the scan output terminal 14 in synchronization with the clock CK.
Thus, outputting the test results R1-R6 stored in the scan flip-flops ff6-ff1 from the scan output terminal 14 to the outside is referred to as “scanout”.
[0049]
<Effect>
The scan test circuit in the LSI 1 according to the first embodiment of the present invention provides the following effects.
[0050]
Scan-in and scan-out are performed in synchronization with a clock having a frequency lower than the actual operation speed of the LSI 1, and capture is performed in synchronization with a clock having a frequency equal to the actual operation speed of the LSI 1. Therefore, even if the operation speed of the LSI 1 is high, it is possible to perform a timing test (for example, a delay fault inspection) that checks whether the internal circuit operates correctly at the actual operation speed.
[0051]
Further, a loop is formed between (output of scan chain 120)-(selector 201)-(input of scan chain 120), and the scanned-in test data D1-D6 are circulated on this loop for a predetermined period. As a result, a highly accurate timing test can be performed while the clock is stable.
[0052]
Moreover, since an expensive tester is not required, an increase in test cost can be suppressed.
[0053]
<Notes>
Here, the scan chain 120 is configured by the six-stage scan flip-flops ff1 to ff6, but the number of scan flip-flops configuring the scan chain is not limited to six.
[0054]
Further, here, one loop is formed between (output of the scan chain 120) − (selector 201) − (input of the scan chain 120) in six clock cycles. Alternatively, the scan chain 120 may be divided into a plurality of scan chains, and a loop may be formed for each of the plurality of scan chains. As a result, the number of clock cycles required to make a round of the loop can be reduced. For example, as shown in FIG. 3, the scan chain 120 (FIG. 1) is divided into a scan chain 301 composed of scan flip-flops ff1-ff3 and a scan chain 302 composed of scan flip-flops ff4-ff6. Further, a selector 203 similar to the selector 201 is provided. Thus, between (output of scan chain 301)-(selector 201)-(input of scan chain 301) and between (output of scan chain 302)-(selector 203)-(input of scan chain 302), 3 A loop that makes a round in a clock cycle is formed.
[0055]
(Second Embodiment)
<Configuration>
FIG. 4 is a block diagram showing a configuration of a semiconductor integrated circuit device (LSI) according to the second embodiment of the present invention. The LSI 4 shown in FIG. 4 includes a loop signal input terminal 15 and a test control circuit 400 in place of the control signal input terminal 12 and the test control circuit 202 shown in FIG. Other configurations are the same as those of the LSI 1 shown in FIG.
[0056]
The loop signal LP is supplied to the loop signal input terminal 15 from the outside. A loop signal LP applied to the loop signal input terminal 15 from the outside is supplied to the selector 201 and the test control circuit 400.
[0057]
Test control circuit 400 includes an internal clock generation circuit 401, a clock switch 402, and a capture signal generation circuit 403. The internal clock generation circuit 401 generates a clock CKb having a frequency equal to the operation speed of the LSI 4. The clock switcher 402 responds to the loop signal LP from the loop signal input terminal 15 and the clock control signal SL from the capture signal generation circuit 403, or the clock CKa from the clock input terminal 13 or the clock from the internal clock generation circuit 401. CKb is output as the clock CK. Specifically, the clock switch 402 outputs the clock CKb from the internal clock generation circuit 401 as the clock CK when both the loop signal LP and the clock control signal SL are at the H level, and otherwise the clock input terminal 13. Is output as the clock CK. The capture signal generation circuit 403 generates a capture signal CAPT and a clock control signal SL based on the loop signal LP from the loop signal input terminal 15 and the clock CK from the clock switch 402. Specifically, the capture signal generation circuit 403 performs the second operation after the first period (here, 6 clock cycles of the clock CK) has elapsed from the time when the loop signal LP changes from the L level to the H level. During this period (here, one clock cycle of the clock CK), the H level capture signal CAPT is output, and otherwise, the L level capture signal CAPT is output. Further, the capture signal generation circuit 403 responds to the change of the loop signal LP from the L level to the H level in the third period (here, 13 clock cycles of the clock CK). The H level clock control signal SL. Otherwise, an L level clock control signal SL is output.
[0058]
Of the LSI 4 configured as described above, the scan chain 120, the selector 201, and the test control circuit 400 constitute a scan test circuit.
[0059]
<Scan test procedure>
The procedure of the scan test by the scan test circuit shown in FIG. 4 will be described with reference to FIG.
[0060]
(1) Period from time t0 to time t1
A clock CKa having a frequency lower than the actual operation speed of the LSI 4 is applied to the clock input terminal 13. Further, the L level loop signal LP is applied to the loop signal input terminal 15. In response to the L level loop signal LP, the clock switch 402 outputs the clock signal CKa from the clock input terminal 13 as the clock CK. The capture signal generation circuit 403 outputs an L level capture signal CAPT. Test data SIN (here, D1-D6) is serially applied to the scan input terminal 11. The selector 201 supplies test data D 1 -D 6 from the scan input terminal 11 to the input of the scan chain 120. The scan chain 120 shifts the test data D1-D6 from the selector 201 in synchronization with the clock CK. As a result, the test data D1-D6 are set in the scan flip-flops ff6-ff1.
[0061]
(2) Period from time t1 to time t2
The supply of the clock CKa to the clock input terminal 13 from the outside is stopped. This is to prevent malfunction of the LSI 4 at the time of clock switching. Note that the supply of the clock CKa from the outside to the clock input terminal 13 is stopped during the period up to the time t6 thereafter. Within a period from time t1 to time t2, the loop signal LP applied to the loop signal input terminal 15 is switched from L level to H level. In response to this, the capture signal generation circuit 403 switches the clock control signal SL from the L level to the H level. The selector 201 gives the output of the scan chain 120 to the input of the scan chain 120. As a result, a loop is formed between (output of scan chain 120) − (selector 201) − (input of scan chain 120).
[0062]
(3) Period from time t2 to time t3
In response to the H level loop signal LP and the H level clock control signal SL, the clock switch 402 outputs the clock CKb from the internal clock generation circuit 401 as the clock CK. Capture signal CAPT from capture signal generation circuit 403 is at L level. The test data D1-D6 stored in the scan chain 120 circulates on the above loop in synchronization with the clock CK equal to the actual operation speed of the LSI 4. Here, since the first period is 6 clock cycles, the period from time t2 to time t3 is 6 clock cycles. Accordingly, the test data D1-D6 is set again in the scan flip-flops ff6-ff1 at time t3.
[0063]
(4) Period from time t3 to time t4
Subsequently, the clock switch 402 outputs the clock CKb from the internal clock generation circuit 401 as the clock CK. Since the first period (six clock cycles) has elapsed since the time when the loop signal LP changed from the L level to the H level, the capture signal generation circuit 403 performs the second period (here, 1 from the time t3 to the time t4). (Clock cycle) An H level capture signal CAPT is output. In response to the H level capture signal CAPT, the scan chain 120 enters the capture mode. In the scan chain 120 in the capture mode, the outputs R1-R6 (test results) of the combinational circuit 110 for the test data D1-D6 are taken into the scan flip-flops ff6-ff1.
[0064]
(5) Period from time t4 to time t5
Subsequently, the clock switch 402 outputs the clock CKb from the internal clock generation circuit 401 as the clock CK. The capture signal generation circuit 403 outputs an L level capture signal CAPT. The loop signal LP remains at the H level. Therefore, the test results R1-R6 fetched into the scan flip-flops ff6-ff1 during the period from the time t3 to the time t4 are circulated on the above loop in synchronization with the clock CK having a frequency equal to the actual operation speed of the LSI 4. To do.
[0065]
When the third period (13 clock cycles of the clock CK) elapses after the loop signal LP changes from the L level to the H level, the capture signal generation circuit 403 switches the clock control signal SL from the H level to the L level. Since the period from time t4 to this point is 6 clock cycles, the test results R1-R6 are set again in the scan flip-flops ff6-ff1.
[0066]
Although the third period is 13 clock cycles here, the third period is not limited to this. For example, when the third period is 14 clock cycles, the period from time t4 to the end of the third period is 7 clock cycles, and when the third period has elapsed, the scan flip-flops ff6-ff1 have the test result R2 -R6 and R1 are stored. As described above, the third period can be set according to the test result to be stored in the scan flip-flops ff1 to ff6 when the third period has elapsed.
[0067]
(6) Period from time t5 to time t6
In response to the L level clock control signal SL, the clock switch 402 outputs the clock CKa from the clock input terminal 13 as the clock CK. However, since the supply of the clock CKa from the outside to the clock input terminal 13 is stopped during this period, the output of the clock CK from the clock switch 402 is also stopped. Further, within this period, the loop signal LP applied to the loop signal input terminal 15 is switched from the H level to the L level.
[0068]
(7) Period from time t6 to time t7
The clock CKa is again supplied to the clock input terminal 13 from the outside. The clock switch 402 outputs the clock CKa from the clock input terminal 13 as the clock CK. The loop signal LP and the capture signal CAPT are at the L level. The scan chain 120 shifts the test results R1-R6 stored in the scan flip-flops ff6-ff1 in synchronization with the clock CK. As a result, the test result SOUT (R1-R6) is serially output from the scan output terminal 14 in synchronization with the clock CK. The test results SOUT serially output from the scan output terminal 14 are in the order of the test results stored in the scan flip-flops ff6-ff1 when the third period has elapsed.
[0069]
<Effect>
In the scan test circuit in the LSI 4 according to the second embodiment of the present invention, the following effects are obtained in addition to the effects described in the first embodiment.
[0070]
In general, in an LSI operating at high speed, it is difficult to control the switching of the scan chain shift mode / capture mode from the outside in response to the actual operating speed of the LSI. However, since the scan signal generation circuit 403 is provided in this scan test circuit, it is not necessary to control the shift mode / capture mode switching of the scan chain 120 from the outside. Therefore, even an LSI that operates at high speed can be easily tested at an actual operation speed.
[0071]
In general, it is difficult to accurately control the timing of switching the internal clock of an LSI from a high-speed clock to a low-speed clock directly from the outside of the LSI. However, in this scan test circuit, the capture signal generation circuit 403 automatically switches the clock control signal SL from the H level to the L level when the third period elapses after the loop signal LP changes from the L level to the H level. In response to this, the clock switch 402 outputs the clock CKa from the clock input terminal 13 as the clock CK. This eliminates the need to directly control the switching of the clock CK (switching from a high-speed clock to a low-speed clock) during the period from time t5 to time t6. Therefore, even an LSI that operates at high speed can be easily tested at an actual operation speed.
[0072]
In addition, by setting the third period to an appropriate period, the order of test results serially output from the scan output terminal 14 to the outside can be changed to a desired order.
[0073]
<Notes>
Here, the supply of the clock CKa from the outside to the clock input terminal 13 is stopped during the period from the time t1 to the time t2 and the period from the time t5 to the time t6, and the clock switching unit 402 clocks the clock CKa from the clock input terminal 13 Output as CK. Thereby, the stop state of the clock CK is realized. Instead, the internal clock generation circuit 401 is configured to stop the generation of the clock CKb in response to the L-level clock control signal SL, and the clock CKb from the internal clock generation circuit 401 is output as the clock CK. This can also be realized by configuring the clock switch 402.
[0074]
(Third embodiment)
<Configuration>
FIG. 6 is a block diagram showing a configuration of a semiconductor integrated circuit device (LSI) according to the third embodiment of the present invention. The LSI 6 shown in FIG. 6 includes a test control circuit 600 and scan flip-flops ff61-ff66 instead of the test control circuit 400 and scan flip-flops ff1-ff6 shown in FIG. Other configurations are the same as those of the LSI 4 shown in FIG.
[0075]
Test control circuit 600 includes an internal clock generation circuit 401, a clock switch 601, and a capture signal and hold signal generation circuit 602. In response to the loop signal LP from the loop signal input terminal 15, the clock switcher 601 outputs the clock CKa from the clock input terminal 13 or the clock CKb from the internal clock generation circuit 401 as the clock CK. Specifically, the clock switch 601 outputs the clock CKb from the internal clock generation circuit 401 as the clock CK when the loop signal LP is at the H level, and from the clock input terminal 13 when the loop signal LP is at the L level. The clock CKa is output as the clock CK. The capture signal and hold signal generation circuit 602 generates the capture signal CAPT and the hold signal HD based on the loop signal LP from the loop signal input terminal 15 and the clock CK from the clock switch 601. Specifically, the capture signal and hold signal generation circuit 602 has passed the first period (here, 6 clock cycles of the clock CK) from the time when the loop signal LP changes from the L level to the H level. Later, in a second period (here, one clock cycle of the clock CK), an H level capture signal CAPT is output, and in other cases, an L level capture signal CAPT is output. The capture signal generation circuit 403 receives the loop signal LP after a third period (here, 13 clock cycles of the clock CK) has elapsed since the loop signal LP changed from the L level to the H level. The H level hold signal HD is output during the period until it changes to the L level, and the L level hold signal HD is output otherwise.
[0076]
The scan flip-flops ff61 to ff66 are obtained by replacing normal flip-flops included in the sequential circuit 100 so that a scan operation can be performed. The scan flip-flops ff61 to ff66 are connected in series like a shift register and operate in synchronization with the clock CK from the clock input terminal 13. The scan flip-flops ff61 to ff66 connected in this way are called a scan chain 120. Scan flip-flops ff61-ff66 perform a shift operation when the capture signal and hold signal HD from hold signal generation circuit 602 are at L level in the shift mode (when capture signal CAPT is at L level), and hold signals in shift mode. When HD is at the H level, the value is continuously held without performing the shift operation. The state in which the scan flip-flops ff61 to ff66 continue to hold values is hereinafter referred to as “hold mode”.
[0077]
Of the LSI 6 configured as described above, a scan test circuit is configured by the scan chain 120, the selector 201, and the test control circuit 600.
[0078]
<Configuration and operation of scan flip-flops ff61-ff66>
FIG. 7 is a block diagram showing an internal configuration of the scan flip-flops ff61 to ff66 shown in FIG. Referring to FIG. 7, scan flip-flops ff61-ff66 include selectors 701, 702, a master latch 703, a slave latch 704, and an inverter 705. The selector 701 outputs the data SD from the preceding scan flip-flop to the selector 702 in response to the L level hold signal HD, and outputs the output Q of the slave latch 704 to the selector 702 in response to the H level hold signal HD. Output. The selector 702 outputs the data from the selector 701 to the master latch 703 in response to the L level capture signal CAPT, and the data D from the combinational circuit 110 (FIG. 6) in response to the H level capture signal CAPT. Output to. The master latch 703 latches the data from the selector 702 in response to the clock CK and outputs the data to the slave latch 704. The inverter 705 inverts the clock CK. The slave latch 704 latches the data from the master latch 703 in response to the clock from the inverter 705 and outputs the data as the output Q.
[0079]
In the scan flip-flops ff61 to ff66 configured as described above, when the hold signal HD is at the L level when the capture signal CAPT is at the L level, the data SD from the previous scan flip-flop is supplied to the master latch 703. Accordingly, the scan flip-flops ff61 to ff66 function as shift registers. On the other hand, when the hold signal HD is at the H level when the capture signal CAPT is at the L level, the output Q of the slave latch 704 is given to the master latch 703. Therefore, the scan flip-flops ff61 to ff66 keep the value one cycle before.
[0080]
<Scan test procedure>
The procedure of the scan test by the scan test circuit shown in FIG. 6 will be described with reference to FIG.
[0081]
(1) Period from time t0 to time t1
A clock CKa having a frequency lower than the actual operation speed of the LSI 6 is applied to the clock input terminal 13. Further, the L level loop signal LP is applied to the loop signal input terminal 15. In response to the L level loop signal LP, the clock switch 601 outputs the clock signal CKa from the clock input terminal 13 as the clock CK. The capture signal and hold signal generation circuit 602 outputs an L level capture signal CAPT. Test data SIN (here, D1-D6) is serially applied to the scan input terminal 11. The selector 201 supplies test data D 1 -D 6 from the scan input terminal 11 to the input of the scan chain 120. The scan chain 120 shifts the test data D1-D6 from the selector 201 in synchronization with the clock CK. As a result, the test data D1-D6 are set in the scan flip-flops ff66-ff61, respectively.
[0082]
(2) Period from time t1 to time t2
The supply of the clock CKa to the clock input terminal 13 from the outside is stopped. This is to prevent malfunction of the LSI 6 when the clock is switched. Note that the supply of the clock CKa from the outside to the clock input terminal 13 is stopped during the period up to the time t6 thereafter. Within a period from time t1 to time t2, the loop signal LP applied to the loop signal input terminal 15 is switched from L level to H level. In response to this, the selector 201 gives the output of the scan chain 120 to the input of the scan chain 120. As a result, a loop is formed between (output of scan chain 120) − (selector 201) − (input of scan chain 120).
[0083]
(3) Period from time t2 to time t3
In response to the H level loop signal LP, the clock switch 601 outputs the clock CKb from the internal clock generation circuit 401 as the clock CK. Capture signal CAPT from capture signal and hold signal generation circuit 602 is at L level. The test data D1-D6 stored in the scan chain 120 circulates on the above loop in synchronization with the clock CK equal to the actual operation speed of the LSI 6. Here, the period from time t2 to time t3 is 6 clock cycles. Therefore, the test data D1-D6 is set again in the scan flip-flops ff66-ff61 at time t3.
[0084]
(4) Period from time t3 to time t4
Subsequently, the clock switch 601 outputs the clock CKb from the internal clock generation circuit 401 as the clock CK. Since the first period (six clock cycles) has elapsed since the time when the loop signal LP changed from the L level to the H level, the capture signal and hold signal generation circuit 602 operates in the second period (here, from time t3 to time t4). 1 clock cycle until) The H level capture signal CAPT is output. In response to the H level capture signal CAPT, the scan chain 120 enters the capture mode. In the scan chain 120 in the capture mode, the outputs R1-R6 (test results) of the combinational circuit 110 for the test data D1-D6 are taken into the scan flip-flops ff66-ff61.
[0085]
(5) Period from time t4 to time t5
Subsequently, the clock switch 601 outputs the clock CKb from the internal clock generation circuit 401 as the clock CK. The capture signal and hold signal generation circuit 602 outputs an L level capture signal CAPT. The loop signal LP remains at the H level. Therefore, the test results R1-R6 captured in the scan flip-flops ff66-ff61 during the period from the time t3 to the time t4 circulate on the above loop in synchronization with the clock CK having a frequency equal to the actual operating speed of the LSI 6. To do.
[0086]
When the third period (13 clock cycles of clock CK) elapses after the loop signal LP changes from L level to H level, the capture signal generation circuit 403 switches the hold signal HD from L level to H level. Since the period from time t4 to this point is 6 clock cycles, the test results R1-R6 are set again in the scan flip-flops ff66-ff61. Thereafter, while the hold signal HD is at the H level, the scan flip-flops ff66 to ff61 continue to hold the test results R1 to R6 without performing the shift operation. A state in which the scan flip-flops ff66 to ff61 continue to hold the test results R1 to R6 without performing the shift operation is referred to as “hold mode”.
[0087]
Here, since the third period is 13 clock cycles of the clock CK, the test results R1-R6 are set in the scan flip-flops ff66-ff61 when the hold signal HD becomes H level. By changing the third period, the test result set in the scan flip-flops ff61 to ff66 at the time when the hold signal HD becomes H level is changed. For example, if the third period is 12 clock cycles of the clock CK, the test results R6, R1-R5 are set in the scan flip-flops ff66-ff61 when the hold signal HD becomes H level. Therefore, by setting the third period appropriately, a desired test result can be set in the scan flip-flops ff61 to ff66 at the time when the hold signal HD becomes H level.
[0088]
(6) Period from time t5 to time t6
Within this period, the loop signal LP applied to the loop signal input terminal 15 is switched from the H level to the L level. In response to this, the capture signal and hold signal generation circuit 602 switches the hold signal HD from the H level to the L level. As a result, the scan flip-flops ff61 to ff66 are not in the hold mode. The clock switch 601 outputs the clock CKa from the clock input terminal 13 as the clock CK. However, since the supply of the clock CKa from the outside to the clock input terminal 13 is stopped during this period, the output of the clock CK from the clock switch 601 is also stopped.
[0089]
(7) Period from time t6 to time t7
The clock CKa is again supplied to the clock input terminal 13 from the outside. The clock switch 601 outputs the clock CKa from the clock input terminal 13 as the clock CK. Further, the loop signal LP, the hold signal HD, and the capture signal CAPT are at the L level. The scan chain 120 shifts the test results R1-R6 stored in the scan flip-flops ff66-ff61 in synchronization with the clock CK. As a result, the test result SOUT (R1-R6) is serially output from the scan output terminal 14 in synchronization with the clock CK. The test results SOUT output serially from the scan output terminal 14 are in the order of the test results stored in the scan flip-flops ff6-ff1 when the hold signal HD becomes H level.
[0090]
<Effect>
In the scan test circuit in the LSI 6 according to the third embodiment of the present invention, the following effects can be obtained in addition to the effects described in the first embodiment.
[0091]
Since the capture signal and hold signal generation circuit 602 is provided, it is not necessary to control the shift mode / capture mode switching of the scan chain 120 from the outside. Therefore, even an LSI that operates at high speed can be easily tested at an actual operation speed.
[0092]
Further, by setting the third period to an appropriate period, the order of the test results serially output from the scan output terminal 14 to the outside can be automatically set to a desired order.
[0093]
Further, since the capture signal and hold signal generation circuit 602 and the scan flip-flops ff61 to ff66 are provided, the order of the test results serially output from the scan output terminal 14 to the outside is set to the length of the period from time t4 to time t5. Regardless of the number of clock cycles, the order can be fixed.
[0094]
(Fourth embodiment)
<Configuration>
FIG. 9 is a block diagram showing a configuration of a semiconductor integrated circuit device (LSI) according to the fourth embodiment of the present invention. The LSI 9 shown in FIG. 9 includes a test control circuit 900 and scan flip-flops ff1-ff4 instead of the test control circuit 400 and scan flip-flops ff1-ff6 shown in FIG. Other configurations are the same as those of the LSI 4 shown in FIG.
[0095]
The test control circuit 900 includes an internal clock generation circuit 401, a clock switch 901, a capture signal generation circuit 902, and a clock counter 910. In response to the loop signal LP from the loop signal input terminal 15, the clock switch 901 outputs the clock CKa from the clock input terminal 13 or the clock CKb from the internal clock generation circuit 401 as the clock CK. The clock switcher 901 outputs a clock mode signal CM corresponding to the output clock CK. Specifically, the clock switch 901 outputs the clock CKb from the internal clock generation circuit 401 as the clock CK when the loop signal LP is at the H level, and from the clock input terminal 13 when the loop signal LP is at the L level. The clock CKa is output as the clock CK. The clock switch 901 outputs an H-level clock mode signal CM when outputting the clock CKb from the internal clock generation circuit 401 as the clock CK, and outputs the clock CKa from the clock input terminal 13 as the clock CK. Outputs an L-level clock mode signal CM. The capture signal generation circuit 902 generates a capture signal CAPT based on the clock mode signal CM and the clock CK from the clock switch 901. Specifically, the capture signal generation circuit 902 performs the first operation after the first period (here, four clock cycles of the clock CK) has elapsed since the clock mode signal CM changed from the L level to the H level. The H level capture signal CAPT is output for a period of 2 (here, one clock cycle of the clock CK). Otherwise, the L level capture signal CAPT is output.
[0096]
The scan flip-flops ff1 to ff4 are obtained by replacing normal flip-flops included in the sequential circuit 100 so that a scan operation can be performed. The scan flip-flops ff1 to ff4 are connected in series like a shift register and operate in synchronization with the clock CK from the clock input terminal 13. The scan flip-flops ff1 to ff4 connected in this way are referred to as a scan chain 120. The scan chain 120 enters the capture mode in response to the H level capture signal CAPT, and enters the shift mode in response to the L level capture signal CAPT.
[0097]
The clock counter 910 includes a register 911. The register 911 includes scan flip-flops ff11 and ff12. The scan flip-flops ff11 and ff12 are flip-flops that can perform a scan operation. The scan flip-flops ff11 and ff12 are connected in series like a shift register to form a scan chain 912. The scan chain 912 is connected between the output of the scan chain 120 and the scan output terminal 14. The scan chain 912 functions as a shift register when the clock mode signal CM from the clock switch 901 is at L level, and functions as a 2-bit register when the clock mode signal CM from the clock switch 901 is at H level. The scan flip-flops ff11 and ff12 reset the held value in synchronization with the clock CK from the clock switch 901 (set it to 0) when the capture signal CAPT from the capture signal generation circuit 902 is at the H level.
[0098]
The clock counter 910 adds 1 to the value stored in the register 911 in response to the rising edge of the clock CK from the clock switch 901 when the clock mode signal CM from the clock switch 901 is at the H level. The result is stored in the register 911. In this way, the clock counter 910 counts the number of clocks CK.
[0099]
Of the LSI 9 configured as described above, the scan chain 120, the selector 201, and the test control circuit 900 constitute a scan test circuit.
[0100]
<Scan test procedure>
A scan test procedure by the scan test circuit shown in FIG. 9 will be described with reference to FIG.
[0101]
(1) Period from time t0 to time t1
A clock CKa having a frequency lower than the actual operating speed of the LSI 9 is applied to the clock input terminal 13. Further, the L level loop signal LP is applied to the loop signal input terminal 15. In response to the L level loop signal LP, the clock switch 901 outputs the clock signal CKa from the clock input terminal 13 as the clock CK and also outputs the L level clock mode signal CM. The capture signal generation circuit 902 outputs an L level capture signal CAPT. The initial value (here, 0, 0) of the register 911 and the test data SIN (here, D1-D4) are serially applied to the scan input terminal 11. The selector 201 gives initial values 0, 0 and test data D1-D4 from the scan input terminal 11 to the input of the scan chain 120. The scan chains 120 and 912 connected in series shift the initial values 0 and 0 and the test data D1 to D4 from the selector 201 in synchronization with the clock CK. As a result, initial values 0 and 0 are set in the scan flip-flops ff12 and ff11, and test data D1 to D4 are set in the scan flip-flops ff4 and ff1.
[0102]
(2) Period from time t1 to time t2
The supply of the clock CKa to the clock input terminal 13 from the outside is stopped. This is to prevent malfunction of the LSI 9 at the time of clock switching. Note that the supply of the clock CKa from the outside to the clock input terminal 13 is stopped during the period up to the time t6 thereafter. Within a period from time t1 to time t2, the loop signal LP applied to the loop signal input terminal 15 is switched from L level to H level. In response to this, the selector 201 gives the output of the scan chain 120 to the input of the scan chain 120. As a result, a loop is formed between (output of scan chain 120) − (selector 201) − (input of scan chain 120). In response to the switching of the loop signal LP from the L level to the H level, the clock switch 901 switches the clock mode signal CM from the L level to the H level.
[0103]
(3) Period from time t2 to time t3
In response to the H level loop signal LP, the clock switch 901 outputs the clock CKb from the internal clock generation circuit 401 as the clock CK. Capture signal CAPT from capture signal generation circuit 902 is at L level. The test data D1-D4 stored in the scan chain 120 circulates on the above loop in synchronization with the clock CK equal to the actual operation speed of the LSI 9. Here, the period from time t2 to time t3 is 4 clock cycles. Accordingly, the test data D1-D4 is set again in the scan flip-flops ff4-ff1 at time t3.
[0104]
The clock counter 910 adds 1 to the value stored in the scan chain 912 in the register 911 every time the clock CK from the clock switch 901 rises, and stores the result in the scan chain 912. Before the time t2, the scan chain 912 stores 0 (decimal display) as an initial value. Therefore, the value CNT stored in the scan chain 912 is 1, 2, 3, 0 (all in decimal notation) every time the clock CK rises.
[0105]
(4) Period from time t3 to time t4
Subsequently, the clock switch 901 outputs the clock CKb from the internal clock generation circuit 401 as the clock CK. Since the first period (four clock cycles) has elapsed since the clock mode signal CM changed from the L level to the H level, the capture signal generation circuit 902 operates in the second period (here, from time t3 to time t4). 1 clock cycle) An H level capture signal CAPT is output. In response to the H level capture signal CAPT, the scan chain 120 enters the capture mode. In the scan chain 120 in the capture mode, the outputs R1-R4 (test results) of the combinational circuit 110 for the test data D1-D4 are taken into the scan flip-flops ff4-ff1. The scan flip-flops ff11 and ff12 reset the held values in synchronization with the clock CK (set to 0).
[0106]
(5) Period from time t4 to time t5
Subsequently, the clock switch 901 outputs the clock CKb from the internal clock generation circuit 401 as the clock CK. The capture signal generation circuit 902 outputs an L level capture signal CAPT. The loop signal LP and the clock mode signal CM remain at the H level. Therefore, the test results R1-R4 taken into the scan flip-flops ff4-ff1 during the period from the time t3 to the time t4 are circulated on the above-described loop in synchronization with the clock CK having a frequency equal to the actual operation speed of the LSI 9. To do. Here, the period from time t4 to time t5 is 5 clock cycles. Therefore, test results R2-R4, R1 are stored in scan flip-flops ff4-ff1 at time t5.
[0107]
At time t4, 0 (decimal display) is stored in the scan chain 912. Therefore, the value CNT stored in the scan chain 912 becomes 1, 2, 3, 0, 1 (all in decimal notation) every time the clock CK rises.
[0108]
(6) Period from time t5 to time t6
Within this period, the loop signal LP applied to the loop signal input terminal 15 is switched from the H level to the L level. In response to this, the clock switch 901 switches the clock mode signal CM from the H level to the L level. The clock switch 901 outputs the clock CKa from the clock input terminal 13 as the clock CK. However, since the supply of the clock CKa from the outside to the clock input terminal 13 is stopped during this period, the output of the clock CK from the clock switch 901 is also stopped.
[0109]
(7) Period from time t6 to time t7
The clock CKa is again supplied to the clock input terminal 13 from the outside. The clock switch 901 outputs the clock CKa from the clock input terminal 13 as the clock CK. The loop signal LP, the clock mode signal CM, and the capture signal CAPT are at L level. The scan chains 912 and 120 connected in series shift the count values C12 and C11 and the test results R2-R4 and R1 stored in the scan flip-flops ff12, ff11, and ff4-ff1 in synchronization with the clock CK. As a result, the count values C12 and C11 and the test results R2-R4 and R1 are serially output from the scan output terminal 14 in synchronization with the clock CK. The 2-bit count value (C12, C11) output here is 1 in decimal. The counted values (C12, C11) indicate that the order of the output test results R2-R4, R1 is shifted by one clock. Therefore, the order of the output test results R2-R4, R1 is corrected to R1-R4. Then, the corrected test results R1-R4 are compared with the expected values.
[0110]
When the actual operation speed of the LSI 9 is high, it is difficult to directly switch the loop signal LP from the H level to the L level from the outside when a desired number of clock cycles have elapsed. Actually, after the loop signal LP is switched from the L level to the H level, the loop signal LP is switched to the L level after waiting for a sufficient time to be captured inside the LSI 9. Therefore, although the period from time t4 to time t5 is 5 clock cycles of the clock CK here, this period may be 3 clock cycles or 100 clock cycles. The order of the test results scanned out is shifted according to the number of clock cycles in the period from time t4 to time t5. For example, when the period from time t4 to time t5 is 3 clock cycles, the scanned out count values (C12, C11) are 3 (decimal notation), and the order of the test results is R4, R1-R3. The count values (C12, C11) indicate that the order of the output test results R4, R1-R3 is shifted by 3 clocks. Therefore, the order of the output test results R4, R1-R3 is corrected to R1-R4. In this way, the misalignment of the test results is corrected using the count values (C12, C11).
[0111]
<Effect>
In the scan test circuit in the LSI 9 according to the fourth embodiment of the present invention, the following effects can be obtained in addition to the effects described in the first embodiment.
[0112]
That is, since the clock counter 910 is provided, it is possible to correct a shift in the order of the test results to be scanned out.
[0113]
<Notes>
Here, although the scan chain 120 is configured by the four-stage scan flip-flops ff1 to ff4, the number of scan flip-flops configuring the scan chain 120 is not limited to four. Further, it is desirable that the number of scan flip-flops constituting the scan chain 912 is appropriately changed according to the number of scan flip-flops constituting the scan chain 120.
[0114]
Although the scan flip-flops ff11 and ff12 are reset using the capture signal CAPT here, the signal for resetting the scan flip-flops ff11 and ff12 is not limited to this. Any signal can be used as long as it can be identified from the outside at what clock. This is because such a signal can correct the count value using the number of clocks.
[0115]
In addition, the number of clock cycles from when the clock CK is switched to the clock CKb from the internal clock generation circuit 401 until capture is determined in advance. Therefore, even if the scan flip-flops ff11 and ff12 are not reset, the count value can be corrected by setting initial values in the scan flip-flops ff11 and ff12 at the time of scan-in.
[0116]
Further, the scan flip-flops ff11 and ff12 are initialized with 0 at the time of scan-in, and the scan flip-flops ff11 and ff12 are shifted to hold the initial value 0 until the capture signal CAPT becomes H level. After the capture signal CAPT becomes H level, the scan flip-flops ff11 and ff12 function as registers that hold the number of clocks CK. At the time of scan-out, the scan flip-flops ff11 and ff12 may be shifted to read out the number of clocks CK.
[0117]
【The invention's effect】
In the scan test circuit according to one aspect of the present invention, the test data is set in the first scan chain in synchronization with the first clock, and the second clock having a frequency higher than the frequency of the first clock. The test result can be taken into the first scan chain in synchronization with the first scan chain. Therefore, even if the operation speed of the semiconductor integrated circuit (LSI) to be tested is high, it is possible to perform a timing test (for example, a delay fault inspection) to check whether the internal circuit operates correctly at the actual operation speed. it can.
[0118]
Further, a loop is formed between (output of the first scan chain)-(selector)-(input of the first scan chain), and the test data set in the first scan chain is circulated on this loop. be able to. As a result, a highly accurate timing test can be performed while the second clock is stable.
[0119]
Moreover, since an expensive tester is not required, an increase in test cost can be suppressed.
[0120]
Further, since the capture signal generating means is provided, it is not necessary to directly control the shift mode / capture mode switching of the first scan chain from the outside. Therefore, even an LSI that operates at high speed can be easily tested at an actual operation speed.
[0121]
Further, since the clock switching means is provided, it is not necessary to directly control the switching of the clock supplied to the first scan chain from the outside. Therefore, even an LSI that operates at high speed can be easily tested at an actual operation speed.
[0122]
Also, hold signal generating means is provided, and the first scan chain keeps holding data without performing a shift operation while receiving an active hold signal, so that the first scan chain changes from the capture mode to the shift mode. By setting the period from when the change occurs until the active hold signal is applied to the first scan chain to an appropriate period, the order of the test results output to the outside can be set to a desired order.
[0123]
Further, since the clock counting means is provided, it is possible to correct a deviation in the order of the test results output to the outside.
[0124]
In the scan test method according to another aspect of the present invention, the test data is scanned into the scan chain in synchronization with the first clock, and the second clock having a frequency higher than the frequency of the first clock is obtained. Synchronously, the test result is taken into the first scan chain. Therefore, even if the operation speed of the semiconductor integrated circuit (LSI) to be tested is high, it is possible to perform a timing test (for example, a delay fault inspection) to check whether the internal circuit operates correctly at the actual operation speed. it can.
[0125]
Further, a loop is formed by giving the output from the scan chain to the input of the scan chain, and the test data is shifted on the loop for a predetermined period in synchronization with the second clock. As a result, a highly accurate timing test can be performed while the second clock is stable.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an LSI according to a first embodiment of the present invention.
FIG. 2 is a timing chart for explaining the operation of the scan test circuit shown in FIG. 1;
FIG. 3 is a diagram showing an example in which the scan chain shown in FIG. 1 is divided to form two loops.
FIG. 4 is a block diagram showing a configuration of an LSI according to a second embodiment of the present invention.
5 is a timing chart for explaining the operation of the scan test circuit shown in FIG. 4;
FIG. 6 is a block diagram showing a configuration of an LSI according to a third embodiment of the present invention.
7 is a block diagram showing an internal configuration of the scan flip-flop shown in FIG. 6. FIG.
8 is a timing chart for explaining the operation of the scan test circuit shown in FIG. 6;
FIG. 9 is a block diagram showing a configuration of an LSI according to a fourth embodiment of the present invention.
10 is a timing chart for explaining the operation of the scan test circuit shown in FIG. 9;
[Explanation of symbols]
120,912 scan chain
201 selector
402,601,901 Clock switch
403, 902 Capture signal generation circuit
602 Capture signal and hold signal generation circuit
910 Clock coefficient unit
ff1-ff6, ff61-ff66, ff11, ff12 Scan flip-flop
CK, CKa, CKb clock
CAPT capture signal
HD hold signal

Claims (15)

A first scan chain comprising a plurality of flip-flops ;
A selector that selectively supplies test data generated from the outside of the scan chain or output data of the first scan chain to an input of the first scan chain;
The first scan chain has a shift mode and a capture mode. In the shift mode, the test data supplied to the input by the selector is shifted in synchronization with the first clock , and then the selector scans the test data . shifts in synchronization with the second clock having a frequency higher than the frequency of the output data of the first clock of the first scan chain applied to input, line in synchronization with the second clock A scan test circuit, wherein, in a capture mode executed following the shift, an output from a combinational circuit to be tested is taken into the plurality of flip-flops in synchronization with the second clock.   2. The scan test circuit according to claim 1, wherein a first period elapses after data given to the input of the first scan chain by the selector is switched from the test data to output data of the first scan chain. Capture signal generating means for outputting an active capture signal for a second period after the first scan chain enters a capture mode in response to an active capture signal from the capture signal generating means, and is inactive A scan test circuit, which is in a shift mode in response to a capture signal.   2. The scan test circuit according to claim 1, further comprising clock switching means for selectively supplying the first clock or the second clock to the first scan chain.   4. The scan test circuit according to claim 3, wherein the clock switching means switches the data applied to the input of the first scan chain by the selector from the test data to the output data of the first scan chain. In response, the second clock is supplied to the first scan chain for a predetermined period, and the first clock is supplied to the first scan chain when the predetermined period elapses. .   2. The scan test circuit according to claim 1, wherein a period from when the first scan chain changes from the capture mode to the shift mode and a predetermined period elapses and immediately before the scanout by the first scan chain is performed. Hold signal generating means for providing an active hold signal to the scan chain of the first scan chain, and the first scan chain performs data shift without performing a shift operation while receiving the active hold signal from the hold signal generating means. A scan test circuit characterized by continuing to hold data.   2. The scan test circuit according to claim 1, further comprising clock counting means for counting the number of the second clocks applied to the first scan chain after the first scan chain changes from the capture mode to the shift mode. A scan test circuit, further comprising:   7. The scan test circuit according to claim 6, wherein the clock counting means is connected in series to the first scan chain, and counts when the second clock is applied to the first scan chain. When the number of the second clock is held and the first clock is given to the first scan chain, a second scan chain that shifts the held value in synchronization with the first clock A scan test circuit comprising: A step (a) of scanning test data into a scan chain composed of a plurality of flip-flops in synchronization with a first clock;
A loop is formed by applying an output from the scan chain to an input of the scan chain, and the test data is synchronized with a second clock having a higher frequency than the first clock for a predetermined period on the loop. Shifting step (b);
(C) capturing the output from the combinational circuit to be tested into the plurality of flip-flops in synchronization with the second clock;
Scanning out the test results (d),
The step (b) is performed following the step (a), the step (c) is performed following the step (b), and the step (d) is performed following the step (c). scan test method, characterized in that that.   A semiconductor integrated circuit having a scan chain,
  The scan chain can perform a first shift operation in which data is input from the outside of the scan chain and a second shift operation in which data is input from the output of the scan chain.
  The first shift operation is performed in synchronization with a first clock;
  The second shift operation is performed in synchronization with a second clock having a frequency higher than the frequency of the first clock following the first shift operation,
  A semiconductor integrated circuit in which a capture operation is performed in synchronization with the second clock following the second shift operation.   A semiconductor integrated circuit having a first scan chain and a second scan chain,
The first scan chain can perform a first shift operation in which data is input from the outside of the scan chain and a second shift operation in which data is input from an output of the first scan chain,
  The second scan chain includes the first shift operation in which data is input from the output of the first scan chain, and the second shift operation in which data is input from the output of the second scan chain. Is possible,
  The first shift operation is performed in synchronization with a first clock;
  The second shift operation is performed in synchronization with a second clock having a frequency higher than the frequency of the first clock following the first shift operation,
A semiconductor integrated circuit in which a capture operation is performed in synchronization with the second clock following the second shift operation.   A semiconductor integrated circuit designed for scan testing,
  In a state in which a feedback loop from the output of the scan chain to the input is not formed, and after a first shift operation is performed in synchronization with the first clock, a feedback loop from the output of the scan chain to the input is formed. A semiconductor integrated circuit capable of continuously performing a second shift operation and a capture operation in synchronization with a second clock having a frequency higher than that of the first clock.   12. The semiconductor integrated circuit according to claim 9, wherein the second shift operation can be executed for two cycles or more of the second clock.   The semiconductor integrated circuit according to claim 9, further comprising a selector that switches between the first shift operation and the second shift operation.   14. The semiconductor integrated circuit according to claim 9, further comprising clock switching means for selectively supplying the first clock and the second clock to the scan chain.   After performing the first shift operation in synchronization with the first clock without forming a feedback loop from the output of the scan chain to the input,
  In a state where a feedback loop from the output of the scan chain to the input is formed, a second shift operation and a capture operation are continuously performed in synchronization with a second clock having a frequency higher than that of the first clock. A scan test method for a semiconductor integrated circuit.

Images