KR970002062B1 - Test data output circuit of boundary-scan architecture - Google Patents

Abstract

The test data output device in a boundary scan structure uses a system clock used in a processor as a test clock(TCK) to previously store a test data output(TDO) and in parallel applies the stored TDO to an integrated circuit to thereby reduce the reading time of the TDO by means of the processor. The test data output device in the boundary scan structure comprises: a control circuit being synchronous to the system clock to selectively output first to fourth loading signals and for outputting the TDO in parallel via a data bus and supplying the information of the number of the inputted TDO; a TCK producing circuit for combining the second to fourth loading signals to form and output the TCK, an inverse TCK and an output enable signal and reset upon application of a reset signal; a storing circuit for applying the TDO inputted via the data bus to the processor; and a comparison circuit for combining the system clock and the first loading signal to count the inverse TCK of the TCK producing circuit and for outputting the reset signal when the count value is equal to the number of TDO applied via the data bus.

Description

Test data output device with boundary scan structure

1 is a block diagram of a conventional boundary scan structure.

2 is a block diagram of a test data output apparatus having a boundary scan structure according to the present invention.

3 is a waveform diagram of an essential part of a test data output device having a boundary scan structure according to the present invention.

* Explanation of symbols for main parts of the drawings

10: control circuit 11: processor

12 decoder 20 TCK forming circuit

30: storage circuit 31: series-parallel shift register

32: buffer 40: comparison circuit

41: buffer 42: binary counter

43: comparator 50: integrated circuit

The present invention relates to a boundary-scan architecture defined by the Institute of Electrical and Electronics Engineers (IEEE), and more particularly to a boundary scan structure capable of selectively applying a TDI to a boundary scan input / output cell. Of the test data output device.

In IEEE, boundary scan structures are needed to monitor whether the components of an integrated circuit perform exactly the required function, or whether each component is correctly connected to each other, or whether each component interacts to perform the required function correctly. Is defined in IEEE 1149.1.

According to this rule, the boundary scan structure is referred to as a test clock (hereinafter referred to as TCK), a test data input (hereinafter referred to as TDI), and a test data output (hereinafter referred to as TDO). ) And a terminal for test mode select (hereinafter, referred to as TMS) signals. Here, TCK is a test clock for logic of an integrated circuit according to the IEEE specification, and TDI means test commands and data for testing the logic of the integrated circuit of the above-described regulation. TDI is applied to logic for sampling and testing at the rising edge of TCK.

In addition, the TDO is a test command and data output in series to test logic from the integrated circuit according to the above-mentioned regulations, and the TDO must change state at the falling edge of the TCK. In addition, the TMS is a signal for setting a mode for testing the logic of the integrated circuit according to the above-described rule, and is sampled on the rising edge of the TCK and output.

A conventional simple structure for boundary scanning an integrated circuit using the signals described above is shown in FIG.

In the drawing, reference numeral 1 denotes an integrated circuit having TCK, TDI, TDO, and TMS as described above, and reference numeral 2 denotes a processor for boundary scanning of the integrated circuit 1. The address decoder 3 connected to the processor 2 is configured to decode an address signal applied from the processor and selectively apply a clock signal to the D flip-flops D1-D4. In this case, the input terminals D of the D flip-flops D1-D3 are connected to the processor 2 through a data bus, and the output terminals Q of the integrated circuits for inputting TCK, TDI, and TMS are respectively provided. It is connected to the terminals I1, I2 and I3 of 1). In addition, an input terminal D of the D flip-flop D4 is connected to a terminal O1 of the integrated circuit 1 that outputs a TDO, and the output terminal Q is connected to the processor 2 through an address bus. It is connected. That is, the processor 2 stores the TDI, TMS, and TDI in the flip-flops D1, D2, and D3 through the address bus, respectively, and the D flip-flops D1, D2, or D3 using the address decoder 3, respectively. By selectively applying a clock signal to the TDI, the TDI or TMS stored in the D flip-flop D1, D2 or D3 is applied to the integrated circuit 1. In addition, the processor 2 selectively inputs the TDO of the integrated circuit 1 by selectively applying a clock signal to the D flip-flop D4 using the address decoder 3.

However, in this boundary scan structure, the TDO must be output from the integrated circuit in series in synchronization with TCK. Therefore, since the processor 2 takes a lot of time to read the TDO from the integrated circuit 1, there is a problem that the occupancy time of the processor for boundary scanning is excessively necessary.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to store a TDO output from a boundary scan structure in advance using a system clock used in a processor as a TCK, and parallel the stored TDO to an integrated circuit. The present invention provides a TDO output device with a boundary scan structure that reduces the time the processor uses to read a TDO.

A feature of the present invention for achieving the above object is, in the apparatus for inputting the TDI into the boundary scan structure, selectively outputting the first, second, third, fourth loading signal in synchronization with the system clock, and parallel through the data bus A control circuit for outputting a TDO and supplying information on the number of input TDOs; A TCK forming circuit which combines second, third and fourth loading signals to form and outputs a TCK and inverted TCK and an output enable signal, and is reset upon application of a reset signal; A storage circuit configured to serially input a TDO from the integrated circuit in synchronization with an inverted TCK, and apply a TDO input through the data bus to the processor according to the output enable signal; A comparison circuit for combining the system clock and the first loading signal to count the inverted TCK of the TCK forming circuit and outputting a reset signal when the counted value is equal to the number of TDOs applied through the data bus; The TDO output circuit has a boundary scan structure.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a TDI input circuit diagram of a boundary scan structure according to the present invention, and as shown, a control circuit 10, a TCK forming circuit 20, a storage circuit 30, a comparison circuit 40, and an integrated circuit 50. It includes. At this time, the integrated circuit 50 is an integrated circuit having a boundary scan structure.

In the TDI input circuit of the above-described configuration, the control circuit 10 is composed of a processor 11 and a decoder 12 as shown. At this time, the processor 11 inputs the TDO in parallel from the parallel shift register 40 via the data bus in synchronization with the system clock SCK of the oscillation circuit 60, while in parallel to the comparison circuit 20. Configure to apply the number of input TDOs. In addition, the processor 11 applies the address signal to the decoder 12 through the address bus AB, and the decoder 12 inputs the address signal when the input / output control terminal I / O of the processor is at a high level. . The decoder 12 is configured to decode the address signal and selectively output the first, second, third and fourth loading signals through the terminals I / O 1 -I / O 4. The decoder 12 is also configured to drive in synchronization with the system clock of the oscillation circuit 60.

The TCK forming circuit 20 connected to the control circuit 10 combines the second and third loading signals of the control circuit 10 at the ora gate O1 as shown, and the combined signal and the oscillation circuit. The system clock SCK of 60 is combined in the AND gate A1. In addition, the TCK forming circuit 20 is configured to combine the third and fourth loading signals of the control circuit 10 with the oragate O2 and apply them to the storage circuit 30 as an output enable signal. In addition, the TCK forming circuit 20 is configured such that the output of the AND gate A1 is applied to the clock terminal CK1 of the D flip-flop D1.

The input terminal D of the D flip-flop D1 is connected to the power supply Vcc, and the AND gate A2 is configured to combine the output of the D flip-flop D1 with the system clock SCK. The TCK generation circuit 20 is configured such that the output of the system clock SCK and the D flip-flop D1 inverted by the inverter 11 are combined at the AND gate A3. As can be seen from the description below, the output of the AND gate A2 is used as the clock of the storage circuit 30 in the present invention, and the output of the AND gate A3 is used as the TCK in the present invention.

The storage circuit 30 connected to the TCK forming circuit 20 is composed of a serial and a parallel shift register 31 and a buffer 32 as shown, and the serial and parallel shift loading signal 31 is an AND gate A2. Inverter TCK is used as a clock to sequentially input the TDOs applied from the integrated circuit 50 and output the input TDOs in parallel.

The buffer 32 for inputting the TDOs in parallel from the serial-parallel shift loading signal 31 outputs the TDOs input through the data bus when an output enable signal is applied from the OR gate O1 of the TCK forming circuit 20. It is configured to.

The comparison circuit 40 is composed of a buffer 41, a binary counter 42 and a comparator 43 as shown, and the buffer 41 is used to determine the number of TDOs applied to the serial-parallel shift register 31. Inputted in synchronization with the first loading signal, the binary counter 42 is configured to count the inverted TCK of the TCK forming circuit 20. The comparator 40 is configured to output a reset signal when the number of TDOs applied through the buffer 41 and the value counted to the counter 42 are the same using the comparator 43. At this time, in the present invention, the D flip-flop D1 and the counter 42 are reset by the reset signal of the comparator 43.

When the input / output control terminal (I / O) terminal of the processor 11 becomes the high level at the time t1 as shown in FIG. 2 in the TDO output circuit having the boundary scan structure configured as described above, the decoder 12 decodes the address signal applied via the address bus AB to output the high level first and second loading signals at time t1, respectively. The reason why the output logic of the input / output control terminal (I / O) is not synchronized with the system clock (SCK) is that, as one of ordinary skill in the art knows, the processor outputs a little later than the stem clock due to the delay time. Because it changes. Therefore, the oragate O1 applies a high level logic to the AND gate A1. At this time, the AND gate A1 is supplied with a system clock SCK at one input terminal thereof, so as to temporarily output high-level logic as shown in FIG. 2, but the D flip-flop D1 is connected to the AND gate A1. The high level logic will be output until it is reset by the high level logic.

The AND gate A2 logically multiplies the output of the D flip-flop D1 by the system clock SCK of the oscillation circuit 60, so that the D flip-flop D1 is a high-level logic as shown in FIG. While outputting the same clock as the system clock (SCK) is output, this clock is referred to herein as the inverted TCK as described above.

In addition, the AND gate A3 combines the output of the system clock SCK and the D flip-flop D1 inverted by the inverter I1, thereby outputting a clock inverted TCK as shown in FIG. This clock is used as a TCK for boundary scanning as described later.

Therefore, since the integrated circuit 50 outputs the TDO in synchronization with the TCK, the serial-parallel shift register 31 sequentially inputs the TDO.

On the other hand, since the inverted TCK is applied to the clock terminal CK of the counter 42, the counter 42 counts the number of inverted TCKs. In this embodiment, eight TDOs are applied to the serial-to-parallel shift register 31. Therefore, since the number of TDOs applied to the buffer 41 is also eight, when the counter 42 counts eight clocks CK1, that is, at the time t2, the D flip-flop is generated by the low level reset signal. (D1) and the counter 42 are reset.

After this process, the processor 11 converts the input / output control terminal I / O into a high level state as described above, and causes the decoder 12 to output the third loading signal through the address bus. The address signal is output, and information on the TDO and its number is output through the data bus DB. Thus, the oragates O1 and O2 output high level logic. At this time, since the output of the OA gate O2 acts as an output enable signal to the buffer 32 as described above, the buffer 32 stores the TDO stored in the serial-parallel shift register 31 in parallel through the data bus. To the processor 11. At this time, since the TCK generation circuit 20 continuously outputs the TCK and the inverted TCK by the above-described process, the integrated circuit 50 continuously applies the TDO to the serial / parallel shift register 31. That is, the TDOs stored in the serial / parallel shift register 31 by the third loading signal of the decoder 12 are applied to the processor 11 through the data bus DB, while the TDOs of the integrated circuit 50 are directly connected. It is applied to the parallel shift register 31 sequentially.

The third loading signal is applied to the parallel shift register 31 until the last TDO of the integrated circuit 50, and the processor 11 stores the TDOs stored in the parallel shift register 31 in the data bus DB. The input / output control terminal (I / O) is converted into a high level state for input through the decoder, and the decoder 12 outputs a third loading signal through the address bus.

Therefore, the TCK forming circuit 20 no longer forms and outputs the TCK and the inverted TCK. However, since the Oa gate O2 outputs a high level output enable signal, the buffer 32 applies the TDOs stored in the serial / parallel shift register 31 to the processor 11 through the data bus DB. will be.

That is, the present invention stores the TDO in series in the serial and parallel shift register 31, and then, by using the comparison circuit 40, causes the TCK forming circuit 20 to synchronize with the system clock SCK and corresponds to the number of TDOs. It is to form inverting TCK and TCK. In addition, the serial / parallel shift register 41 synchronizes the inversion TCK to sequentially input the TDO from the integrated circuit 50, and then outputs a loading signal so that the TDOs input to the serial / parallel shift register 31 are processed in parallel. 11).

Therefore, the present invention can shorten the time required for the processor to input the TDO to the integrated circuit, thereby increasing the efficiency of the processor.

Claims (4)

A device for inputting a TDI into a boundary scan structure, wherein the first, second, third, and fourth loading signals are selectively output in synchronization with the system clock, the TDOs are output in parallel through a data bus, and the number of input TDOs is input. A control circuit for supplying information about the information; A TCK forming circuit which combines second, third and fourth loading signals to form and outputs a TCK and inverted TCK and an output enable signal, and is reset upon application of a reset signal; A storage circuit configured to serially input a TDO from the integrated circuit in synchronization with an inverted TCK, and apply a TDO input through the data bus to the processor according to the output enable signal; A comparison circuit for combining the system clock and the first loading signal to count the inverted TCK of the TCK forming circuit and outputting a reset signal when the counted value is equal to the number of TDOs applied through the data bus; A test data output device having a boundary scan structure. 2. The circuit of claim 1, wherein the TCK forming circuit comprises: a first ora gate for combining the second and third loading signals; A second orifice that combines the third and fourth loading signals to output a combined signal as the output enable signal; A first and gate combining the system clock and the output of the first or gate; A D flip-flop connected to an input terminal of a power supply and using an output of the first and gate as a clock and selectively reset by a reset signal; A second and gate outputting the inverted TCK by combining the output of the D flip-flop and a system clock; And a third end gate configured to output the TCK by combining the inverted signal of the system clock and the output of the D flip-flop. 2. The apparatus of claim 1, wherein the storage circuit comprises: a serial and parallel shift register synchronized with the inversion TCK and outputting TDO in series and outputting in parallel from the integrated circuit; And a buffer for applying a TDO of the serial-to-parallel shift register to the control circuit in response to the input of the output enable signal. 2. The apparatus of claim 1, wherein the comparison circuit comprises: a buffer for inputting information on the number of TDIs applied through a data bus according to the first loading signal; A counter for counting the TCK; And a comparator for outputting a reset signal when the number of TDIs applied through the buffer and the count value of the counter are the same.