KR0145789B1 - Test clock generator of boundary-scan architecture - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a boundary scan structure, and more particularly, to an apparatus for boundary scanning an integrated circuit (1) that inputs and outputs TMS, TDI, and TDO in synchronization with TCK. The present invention relates to a TDI input upon application of a TDI clock. A first storage unit (11) for applying to the integrated circuit (1); A second storage unit 12 receiving the TMS and applying the input TMS to the integrated circuit 1 when the TMS clock is applied; A third storage unit 13 which receives the TDO and outputs the input TDI when the TDO clock is applied; A combination unit 4 for logically combining and outputting clocks for TDI, TMS, and TDO applied to the first, second, and third storage units 11, 12, and 13; And a TCK generation circuit 5 for outputting the TCK by combining the output of the combination section 4 and the system clock of a predetermined period.

Description

Test Clock Generator with Boundary Scan Structure

1 is a block diagram of a conventional boundary scan structure.

2 is a timing diagram of a conventional boundary scan structure.

3 is a block diagram of a test clock generator having a boundary scan structure according to the present invention.

4 is a timing diagram of a test clock generator having a boundary scan structure according to the present invention.

* Explanation of symbols for main parts of the drawings

1: integrated circuit 2: processor

3: address decoder 4: combination part

5: TCK generation circuit

The present invention relates to a boundary-scan architecture defined by the Institute of Electrical and Electronics Engineers (IEEE), and more particularly, to a test clock generator having a boundary scan structure for automatically generating a test clock. .

In IEEE, boundary scan structures are needed to monitor whether the components of an integrated circuit perform exactly the required function, or whether each component is correctly connected to each other, or that each component interacts to perform the required function correctly. Is defined in IEEE 1149.1.

According to this rule, the boundary scan structure has a test clock (hereinafter referred to as TCK), a test data input (hereinafter referred to as TDI), a test data output (hereinafter referred to as TDO), and a test mode. Requires a terminal for select (Test Mode Select) signals. Here, TCK is a test clock for logic of the integrated circuit according to the IEEE specification, and TDI means test commands and data for testing the logic of the integrated circuit of the above-described regulation. TDI is applied to logic for sampling and testing at the rising edge of TCK.

In addition, the TDO is a test command and data output in series for testing logic from the integrated circuit according to the above-mentioned regulations, and the TDO must change state at the falling edge of the TCK. In addition, the TMS is a signal for setting a mode for testing the logic of the integrated circuit according to the above-described rule, and is sampled on the rising edge of the TCK and output.

A conventional simple structure for boundary scanning an integrated circuit using the signals described above is shown in FIG.

In the drawing, reference numeral 1 denotes an integrated circuit for boundary scanning using TCK, TDI, TDO, and TMS as described above, and reference numeral 2 denotes a processor for boundary scanning of integrated circuit 1. The address decoder 3 connected to the processor 2 is configured to decode an address signal applied from the processor and selectively apply a clock signal to the D flip-flops D1-D4.

The input terminals D of the D flip-flops D1-D3 are connected to the processor 2 via a data bus, and the output terminals Q thereof are integrated circuits 1 for inputting TCK, TDI, and TMS, respectively. Are connected to terminals I1, I2, and I3. In addition, the input terminal D of the D flip-flop D4 is connected to the terminal O1 of the integrated circuit 1 which outputs the TDO, and the output terminal Q is connected to the processor 2 via the data bus. It is connected.

That is, the processor 2 stores the TCK, TDI, and TMS in the flip-flops D1, D2, and D3 through the data bus, respectively, and the D flip-flops D1, D2, or D3 using the address decoder 3, respectively. By selectively applying a clock signal, the TDI or the TMS is applied to the integrated circuit 1 in synchronization with the TCK. In addition, the processor 2 selectively inputs the TDO of the integrated circuit 1 which is output in synchronization with the TCK by selectively applying a clock signal to the D flip-flop D4 using the address decoder 3.

However, in this conventional configuration, the processor 2 has a inconvenience in that the TCK must be processed in software in accordance with TMS, TDI, and TDO in order to boundary scan the integrated circuit 1.

That is, since the TDI and TMS are sampled at the rising edge of the TCK and input to the integrated circuit 1, and the TDO is changed and output at the falling edge of the TCK, the processor 2 adjusts the TCK according to the input / output states of the TDI, TMS, and TDO. To change.

This process will be described in detail with reference to the timing diagram of FIG.

Although the example of FIG. 2 shows only the case of TDI, it will be easily understood that the case of TDO and TMS is the same.

In the case where the TDI has a state change as shown, in order to apply this state change to the integrated circuit 1, the TCK must be in the rising edge state at the time points t1, t2, t3, t4 .... Applied to the integrated circuit 1. Therefore, the processor 2 should calculate and output the TCK according to the state change of the TDI.

As described above, in the conventional boundary scanning method, since the processor must generate and output the TCK according to the state change of the TDI, the TDO, and the TMS in software, there is a problem that the speed of the boundary scanning becomes slow due to the slow operation of the processor.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to generate a TCK, a TCC, a TDO, a TDO, and a test clock generator having a boundary scan structure that improves boundary scanning speed by improving the boundary speed. To provide.

A feature of the present invention for achieving the above object relates to an apparatus for boundary scanning of integrated circuits for inputting and outputting TMS, TDI, and TDO synchronized with TCK, and receiving a TDI and applying a TDI input upon application of a TDI clock. A first storage unit for applying to an integrated circuit; A second storage unit which receives the TMS and applies the input TMS to the integrated circuit when the TMS clock is applied; A third storage unit which receives the TDO and outputs the input TDI when the TDO clock is applied; A combination unit for logically outputting the TDI, TMS, and TDO clocks applied to the first, second, and third storage units; And a TCK generation circuit for outputting the TCK by combining the output of the combination unit and the system clock of a predetermined period.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a test clock generator having a boundary scan structure according to the present invention, in which the same reference numerals are used for the same components.

As shown, according to the present invention, the D flip-flop D2 constituting the integrated circuit 1, the processor 2, the address decoder 3, and the storage units 11, 12, and 13 having a boundary scan structure as in the related art is shown. , D3, D4).

The D flip-flops D2 and D3 receive TDI and TMS from the processor via the data bus, respectively, and the D flip-flop D4 receives the TDO from the integrated circuit 2.

In addition, the address decoder 3 decodes an address applied from the processor 2 as in the related art and selectively applies a clock signal to the D flip-flops D2, D3, and D4, and the D flip-flops D2 and D3. Outputs the clock signal through the terminals O1 and O2 when the TDI and the TMS are stored, and outputs the clock signal through the terminal O3 when the D flip-flop D4 outputs the stored TDO. It is configured to output selectively. That is, the address decoder 3 has the same configuration as the conventional one.

However, the clock signal output from the terminal O3 of the address decoder 2 of the present invention is not applied to the D flip-flop D4. That is, the clock signals output from the terminals O1 and O2 of the address decoder 2 are applied to the clock terminals of the D flip-flops D2 and D3 as in the prior art, but the clock signals output from the terminal O3 are D. It is not applied to the flip flop D4. That is, the output of the TCK generation circuit 5 described later is applied to the clock terminal of the D flip-flop D4 in an inverted state by the inverter I1, and the output terminal Q is connected to the above-described address decoder 2. A buffer B1 for controlling the output in accordance with the clock signal of the terminal O3 is connected.

As can be seen from the configuration described above, it can be seen that the D flip-flop for storing the TCK is omitted in the present invention, unlike the conventional art. However, in the present invention, instead of the D flip-flop for the TCK, a combination unit 4 and a TCK generation circuit 5 for generating the TCK in hardware are configured.

Specifically, the combination unit 4 is configured as an OR gate OR1 to logically output the clock signals output from the terminals O1, O2, and O3 of the address decoder 3.

The TCK generation circuit 5 connected to the combining section 4 has a D flip-flop D5 using the output of the combining section 4 as a clock and a D flip-flop using the system clock SCK as a clock signal ( D6, D7). Since the system clock SCK is essentially used for driving the processor, the system clock SCK is not illustrated in FIG. 1. On the other hand, D flip-flop D5 has its input terminal D connected to a power source, its output terminal Q is connected to the input terminal D of D flip-flop D6, and D flip-flop D6. The output terminal Q is connected to the D flip-flop D7 and the terminal I1 of the integrated circuit 1. Here, the terminal I1 of the integrated circuit 1 is a terminal for inputting a TCK as in the prior art.

In addition, the inverted output terminal / Q of the D flip-flop D7 is connected to the AND gate A1, and the AND gate A1 is a low level reset signal and the inverted output terminal of the D flip-flop D7. Configured to selectively reset the D flip-flops D5, D6, and D7 by combining the signal applied from (/ Q).

In the test clock generator having the boundary scan structure configured as described above, the TCK generation circuit 5 automatically outputs the TCK in synchronization with the clock of the address decoder 3, so that the processor does not need to generate the TCK in software.

That is, when the address decoder 3 applies a clock signal to any one of the D flip-flops D2, D3, and D4 through the terminals O1, O2, and O3, the combination unit 4 is shown in FIG. As described above, the same pulse P1 as the clock signal is output. Since the pulse P1 acts as a clock signal to the D flip-flop D5, the D flip-flop D5 outputs the high-level logic P2 at the time point t1 in synchronization with the pulse P1, and thus the D flip-flop. It is applied to (D6). At this time, since the system clock SCK is applied to the clock terminals CK of the D flip-flops D6 and D7, the D flip-flop D6 is synchronized with the rising edge of the system clock SCK to form a high level logic P3. Is applied to the D flip-flop D7 at the time point t2. The D flip-flop D7 is also synchronized with the rising edge of the system clock SCK to output the high level logic P4 to the terminal Q at the time point t3, but the output of the inverting terminal / Q. Is applied to the AND gate A1 to reset the D flip-flops D5, D6, and D7, so that the D flip-flops D5, D6, and D7 are at the low level through the output terminal Q at the time point t4. Output logic P2, P3, P4, respectively. Here, it can be easily seen that the time difference between the time points t3 and t4 is due to the delay time occurring at the D flip-flops D5, D6 and D7 and the AND gate A1.

As shown in FIG. 4, the output P3 of the D flip-flop D6 has a system clock after the output of the D flip-flop D5 is converted to a high level by the output of the combination unit 4. It can be seen that the state is converted to the high level state at the rising edge of SCK, and is converted to the low level at the next rising edge of the system clock SCK. Therefore, the pulse P3 output by the TCK generation circuit 5 is the rising edge of the system clock SCK after the D flip-flops D2 and D3 output the TDI and TMS according to the clock signal of the address decoder 3. TDI and TMS are input to the integrated circuit 1 because they are in the rising edge state in synchronization with.

In addition, the integrated circuit 1 outputs the TDO while the TCK is at the falling edge, but since the pulse P3 inverted by the inverter I1 is used as the clock signal of the D flip-flop D4, the D flip-flop D4 is used. ) Stores the TDO in synchronization with the pulse P3. As such, the TDO stored in the D flip-flop D4 is output through the buffer B1 when the output of the terminal O3 of the address decoder 3 is converted to the low level.

As such, the present invention automatically generates a TCK in synchronization with TDI, TMS, and TDO of an integrated circuit capable of boundary scanning, and applies the integrated circuit to the integrated circuit, thereby eliminating the need for a separate software process for the TCK. As it is automatically generated, the speed of boundary scanning is improved.

Claims (3)

An apparatus for boundary scanning of an integrated circuit (1) for inputting and outputting TMS, TDI, and TDO synchronized to a TCK, the apparatus comprising: receiving the TDI and applying the input TDI to the integrated circuit (1) upon application of a TDI clock; 1 storage section 11; A second storage unit 12 which receives the TMS and applies the input TMS to the integrated circuit 1 when the TMS clock is applied; A third storage unit 13 which receives the TDO and outputs the TDI input when the TDO clock is applied; A combination unit (4) for logically combining and outputting the TDI, TMS, and TDO clocks applied to the first, second, and third storage units (11, 12, 13); And a TCK generation circuit (5) for outputting the TCK by combining the output of the combination section (4) and a system clock of a predetermined period. 2. The inverter according to claim 1, wherein the third storage section (13) comprises: an inverter (I1) for inverting and outputting the output of the TCK generation circuit (5); A first D flip-flop (D4) for inputting and storing the TDO of the integrated circuit (1) using the output of the inverter (I1) as a clock; And a buffer (B1) for outputting a TDO stored in the first D flip-flop (D4) according to the clock for the TDO. 2. The TCK generating circuit (5) according to claim 1, further comprising: a second D flip-flop (D5) using the output of the combining section (4) as a clock signal; A third D flip-flop (D6) using the system clock as a clock and inputting an output of the second D flip-flop (D5); A 4D flip-flop (D7) using the system clock as a clock signal and inputting the output of the 3D flip-flop (D6); Boundary scan structure including an AND gate A1 for selectively resetting the second, third and fourth 4D flip-flops D5, D6, and D7 by combining the fourth 4D flip-flop D7 and a predetermined reset signal. Test clock generator.