JPH06187797A - Memory integrated circuit - Google Patents

Abstract

PURPOSE:To perform a test with a clock having the same repetitive frequency as that of a clock in an actual device even in a test device a low operating frequency. CONSTITUTION:This device is a memory integrated circuit having a memory block for storing data, and when a test mode signal 6 is set at 'H' a clock signal 8 which has repetitive frequency of N (N is a numeral larger than 1) times as much as the repetitive frequency of a clock signal 5 is generated in a clock control circuit 1. In an address control circuit 2, an address is inverted and not inverted synchronously with this generated clock signal 8. This output address is given from a register 3 to a RAM block 4 in accordance with the clock signal 8. Even a test device having a low operating frequency can perform an effective test owing to constitution of increasing repetitive frequency of a clock signal in a chip.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to memory integrated circuits,
In particular, it relates to a clock synchronous memory integrated circuit.

[0002]

2. Description of the Related Art Generally, as shown in FIG. 7, a clock synchronous memory integrated circuit has a register 3 which receives an address signal 7 and a clock signal 5 and latches the address signal 7 with the clock signal 5. , And a RAM block 4 which uses the output of the register 3 as an address signal. Then, data is written in or read from the RAM block 4 in response to the input of the address signal 7 and the clock signal.

[0003]

By the way, the memory integrated circuit is usually tested by a well-known test device such as a memory tester, and then only non-defective products are mounted in the actual device. In the test in the test device, it is necessary to operate the memory integrated circuit with a clock having the same frequency as the actual device.

However, in the above-mentioned conventional memory integrated circuit, since the address signal input to the RAM block 4 is synchronized with the clock signal, the cycle of the address signal is determined by the cycle of the externally input clock signal. Therefore, the clock frequency of the test equipment such as memory tester
There is a drawback that effective test results cannot be obtained when the clock frequency is lower than the actual clock frequency. Further, there are cases where it is desired to test a memory integrated circuit by operating it with a clock having an operation limit frequency with a certain margin taken into consideration. However, even in such a case, an effective test cannot be performed when the clock frequency of the test apparatus is low. was there.

Various techniques have been proposed as a method for efficiently testing a memory device. For example,
Japanese Patent Application Laid-Open No. 62-58499 for testing VRAM, Japanese Patent Application Laid-Open No. 63-74351 for testing RAM, Japanese Patent Application Laid-Open No. 64-6415 for using scan path.
No. 79672, data writing / reading control at the time of test, Japanese Patent Laid-Open No. 2-306500, and Japanese Patent Laid-Open No. 3-59900 propose skew adjustment in a test, but these both operate. It does not change the clock frequency.

Therefore, the present invention solves the above-mentioned conventional drawbacks and provides a memory integrated circuit which can be operated in a test device such as a memory tester with a clock having a frequency of an actual device.

[0007]

To solve the above problems, a memory integrated circuit according to the present invention is a memory integrated circuit having a memory block for storing data, wherein a clock signal input in a test mode is repeated. A clock control circuit for generating a clock signal having a repetition frequency N times the frequency (N is a number greater than 1, hereinafter the same); and an address control circuit for changing an address in synchronization with the generated clock signal, A circuit for applying the output address to the memory block according to the generated clock signal.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 shows a first memory integrated circuit according to the present invention.
8 is a block diagram showing the configuration of the embodiment of FIG. 7, and the same parts as in FIG. In the figure, the memory integrated circuit according to the first embodiment of the present invention has a clock signal having a repetition frequency N times the repetition frequency of the input clock signal 5 in addition to the register 3 and the RAM block 4 in its chip. A clock control circuit 1 for generating 8;
The address control circuit 2 is configured to change the value of the address signal 7 in synchronization with the clock signal 8 and output it.

The clock control circuit 1 sends the clock signal 5 as it is as the clock signal 8 in accordance with the test mode signal 6, or generates a clock signal having a repetition frequency N times that of the clock signal 5 and clocks it. Either the signal 8 is transmitted or the operation is performed. That is, when the test mode signal 6 is "H" (in the test mode), a clock signal having a repetition frequency N times is generated,
Clock signal 5 when test mode signal 6 is "L"
Is transmitted as it is.

An example of the internal structure will be described with reference to FIGS. 4, 5 and 6.

First, FIG. 4 is a block diagram showing a configuration example of a clock control circuit when a PLL circuit is used.
The same parts as are indicated by the same reference numerals. The illustrated clock control circuit includes a PLL including an N divider 15.
A (Phase Locked Loop) circuit 20 and a selector 14 that selectively outputs the output of the PLL circuit 20 and the clock signal 5 in accordance with the test mode signal 6 are configured. The PLL circuit 20 is configured to include a phase comparator 11, a loop filter 12, and a voltage controlled oscillator 13 in addition to the N frequency divider 15, but its operation is well known, and therefore its description is omitted. .

According to the clock control circuit having such a configuration, the operation of whether to output the clock signal 5 as it is according to the test mode signal 6 or to output the clock signal having the repetition frequency N times the clock signal 5 is performed. Done.

Next, FIG. 5 is a block diagram showing a configuration example of a clock control circuit in the case of using a differentiating circuit and a delay circuit. This is an AND circuit 16 and an inverter circuit 17.
The differentiating circuit 51 constituted by means of is to generate a clock signal having a pulse width corresponding to the delay time in the inverter circuit 17 in synchronization with the rising edge of the input clock signal 5. Since a plurality of differentiating circuits are provided and a delay line (DL) 22 having a different delay time is provided for each differentiating circuit 51, 52, ..., The output of each differentiating circuit is input to the OR circuit 18. is there.

With such a configuration, as shown in FIG. 6, signals 510, 5 are output from the differentiating circuits 51, 52 ,.
20 is transmitted, and these are combined in the OR circuit 18 to generate the signal 180. The number of differentiating circuits and the delay time of each delay line may be determined so that the repetition frequency of the signal 180 is N times the repetition frequency of the clock signal 5. Then, the signal 180 may be transmitted as the clock signal 8 instead of the clock signal 5 in the test mode.

However, since the set delay time is fixed in this example, the repetition frequency of the clock signal during the test is fixed. Therefore, instead of providing the delay line, if the clock signals having different phase differences are input from the memory tester side to the differentiating circuits, the repetition frequency of the clock signal can be changed.

The value N in each clock control circuit must be greater than 1 in order to increase the repetition frequency of the clock signal.

Returning to FIG. 1, the operation of the memory integrated circuit of this embodiment having such a configuration will be described.

First, the clock signal 5 and the test mode signal 6 are input to the clock control circuit 1 and the test mode signal 6 becomes "H", so that the clock signal 8 having a repetition frequency N times that of the clock signal. Is output.

A clock signal 8, a test mode signal 6 and an address signal 7 are input to the address control circuit 2.
Accordingly, the address control circuit 2 controls the change of the address signal 7 (for example, inversion / non-inversion of the address signal 7) according to the clock signal 8 and the test mode signal 6, and outputs the address signal 9.

The register 3 latches the address signal 9 at the timing of the clock signal 8 and outputs the address signal 10 to the RAM block 4.

The RAM block 4 performs a write or read operation according to the address signal 10.

Next, the operation of each part of FIG. 1 will be described in detail with reference to the operation waveform diagram of FIG.

When the input test mode signal 6 indicates the test mode ("H" in this embodiment), the clock control circuit 1 is N times (4 times in this embodiment) the input clock signal 5. The clock signal 8 having the repetition frequency of is output. When the test mode signal 6 indicates the normal mode (“L” in the embodiment), the clock signal 8 having the same repetition frequency as the input clock signal 5 is output. Then, the clock signal 8 is input to the address control circuit 2 and the register 3.

The address control circuit 2 uses the test mode signal 6
Indicates a test mode, the address signal 7 to be input is alternately inverted / non-inverted in synchronization with the clock signal 8 (in the present embodiment, operated at the rising edge), and is output as the address signal 9. . As a result, the address signal 7
The cycle of changing the value of becomes short. When the test mode signal indicates the normal mode, the input address signal 7 is directly output as the address signal 9.

The register 3 operates by the clock signal 8 and holds the address signal 9.

Next, the RAM block 4 receives the address signal 10 output from the register 3 at the address input terminal AD and operates the address decoder (not shown) in its own block.

The reason why the address signal 9 is inverted / non-inverted in FIG. 2 is that the value of the address signal input to the RAM block 4 is changed by such processing. Not limited to this, the address signal may be changed in synchronization with the clock signal 8. The address control circuit 2 can be easily configured by those skilled in the art using various flip-flops.

Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram showing the configuration of a second embodiment of the memory integrated circuit according to the present invention, and the same portions as those in FIG. 1 are designated by the same reference numerals. The embodiment shown in the drawing is a case where the address control circuit 2 in FIG. 1 is provided in a memory tester (not shown), and the address signal 7
Are latched in the register 3.

That is, some test devices such as a memory tester have a function equivalent to that of the address control circuit 2 shown in FIG. 1, and in that case, a configuration like that of the second embodiment may be adopted. Good. Therefore, the operation of each unit in FIG. 3 is similar to the operation in FIG.

[0031]

As described above, according to the present invention, in the test mode, the repetition frequency of the clock signal is N within the chip.
By doubling it and changing the address signal, there is an effect that a test apparatus having a low repetition frequency of the operation clock can be tested at the repetition frequency of the actual apparatus.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a memory integrated circuit according to the present invention.

FIG. 2 is a waveform diagram showing the operation of each part of the memory integrated circuit of FIG.

FIG. 3 is a block diagram showing a configuration of a second embodiment of a memory integrated circuit according to the present invention.

4 is a block diagram showing an internal configuration example of a clock control circuit in FIG.

5 is a block diagram showing an internal configuration example of a clock control circuit in FIG. 1. FIG.

6 is a waveform chart showing the operation of each part of the clock control circuit of FIG.

FIG. 7 is a block diagram showing a configuration of a conventional memory integrated circuit.

[Explanation of symbols]

 1 clock control circuit 2 address control circuit 3 register 4 RAM block

Claims (2)

[Claims] 1. A memory integrated circuit having a memory block for storing data, wherein N times the repetition frequency of a clock signal input in a test mode (N is a number greater than 1; the same applies hereinafter). A clock control circuit for generating a clock signal having a frequency, an address control circuit for changing an address in synchronization with the generated clock signal, and an output address for the memory block according to the generated clock signal. And a memory integrated circuit. 2. The memory integrated circuit according to claim 1, wherein the address control circuit controls inversion and non-inversion of the address.