JP3357821B2 - Scan path flip-flop circuit and scan path test system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a scan path flip-flop circuit and a scan path test system suitable for a testable design of a system employing a gated clock system.

[0002]

2. Description of the Related Art There is a design technique called gated clock design for the purpose of saving power consumption of a semiconductor circuit designed synchronously. The gated clock design is a design in which an operation clock of a register in a circuit is supplied only to a register to be operated at that time. As a typical example, FIG. 13 shows a conventional example in which a system clock signal selector circuit 100 is provided to control a system clock signal.

In this conventional example, an inverted clock flip-flop that captures and outputs data in response to a falling edge of a system clock signal is used as a clock control flip-flop 101 in a selector circuit 100 for a system clock signal. Have been. This is because the flip-flop 103 in the system circuit 102 is designed so as to take in and output data in accordance with the rising edge of the system clock signal. 101 is because it is necessary to control the gated clock signal with a phase different from that of the system clock signal so that a hazard does not occur on the gated clock signal.

FIG. 14 is a timing chart of the conventional example shown in FIG. In FIG. 14, clock control data is generated by an output signal of a flip-flop that operates according to a rising edge of a system clock or a signal directly supplied from an external input terminal.
Control signals for selecting a system clock signal are generated by a clock control flip-flop 101, which changes at the falling edge of the system clock signal. As a result, the gated clock signal supplied to the system circuit 102 has a waveform as shown in FIG.

When such a gated clock design technique is used, it becomes difficult to automatically perform testability design on the circuit. This is because almost all full-scan design automation tools do not support the gated clock method, and correct test patterns for circuits that operate on both rising and falling clock signals. AT to generate
This is because it is necessary to consider the clock signal waveform and timing at the time of PG.

[0006]

As described above,
In a conventional circuit designed using the gated clock method, a flip-flop circuit operating in synchronization with a rising edge of a clock signal and a flip-flop circuit operating in synchronization with a falling edge of a clock signal are used. Since both were used, it was difficult to use a full-scan design automation tool that automated design for testability. For this reason, there has been a problem that it takes time and effort to design a test for a circuit that employs the gated clock system, so that the test is easy.

Accordingly, the present invention has been made in view of the above, and an object of the present invention is to enable a test facilitating design using an automated tool for a circuit adopting a gated clock system, and to provide a test facilitating design. It is an object of the present invention to provide a scan-path flip-flop circuit and a scan-path test system that can achieve the simplification of the design and the shortening of the design time.

[0008]

According to a first aspect of the present invention, in a normal operation mode, a potential which is opposite to a potential change direction (one potential change direction) of a gated clock signal is provided. Input data is fetched in synchronization with the clock signal in the change direction (the other potential change direction), data fetched in synchronization with the other potential change direction of the clock signal is output from the data output terminal, and inverted data is output as inverted data. Output in the test system mode, captures input data in synchronization with one potential change direction of the clock signal in the test system mode, and outputs the captured input data from the scan data output terminal. The input scan data is fetched in synchronization with the potential change direction of, and the fetched input scan data is output to the scan data output terminal. Output from the data output terminal and the inverted output data output from the inverted data output terminal are fixed to predetermined logic levels in the test system mode and the test scan mode, respectively. A flip-flop circuit that normally changes with one potential change of the clock signal can be treated as a circuit that is synchronous with the flip-flop circuit that changes with the other potential change during the test, and usually one side of the clock signal. The flip-flop circuit that changes with the potential change of the other can be connected in the scan path composed of the flip-flop circuit that changes with the other potential change, and it is necessary to generate a scan test pattern in consideration of the phase of the data change. Gone
Automation of test pattern generation can be expected.

According to a second aspect of the present invention, an output of the first inversion gate is provided via a first inversion gate which receives and inverts input data and a first transmission gate which is controlled to be conductive based on a clock signal. The second to receive and reverse
Receiving the output of the second inverting gate and inverting the output of the second inverting gate, and applying the inverted output to the input of the second inverting gate via a second transmission gate that is controlled to be conductive based on an inverted clock signal. A third inversion gate;
Conduction based on the output of the fourth inversion gate or the inversion scan enable signal via a fourth inversion gate receiving and inverting the input scan data and a third transmission gate that is controlled in conduction based on the scan enable signal A fifth inversion gate that receives and inverts the output of the first inversion gate via a controlled fourth transmission gate, a fifth transmission gate and an inversion clock whose conduction is controlled based on an inversion test enable signal Via a sixth transmission gate, which is controlled based on a signal, an output of the second inverting gate or a seventh transmission gate, which is controlled based on a test enable signal, and via the sixth transmission gate Receiving the output of the fifth inverting gate; A sixth inverting gate through a sixth inverting gate that inverts the output of the sixth inverting gate and an eighth transmission gate that receives and inverts the output of the sixth inverting gate, and inverts the inverted output based on a clock signal. A seventh inverting gate applied to the input of the second inverting gate, an eighth inverting gate receiving and inverting the output of the seventh inverting gate via a ninth transmission gate controlled to be conductive based on a clock signal, Receiving the output of the eighth inverting gate, inverting the inverted output, applying the inverted output to the input of the eighth inverting gate via a tenth transmission gate whose conduction is controlled based on an inverted clock signal, and outputting the inverted output to an output scan A ninth inverting gate that outputs data, an inverting test enable signal, and a NOT logic that receives the output of the sixth inverting gate and provides output data (NAND) gates and, NOR which receives the output of the test enable signal and the seventh inverting gate providing an inverted output data (NO
R) a flip-flop circuit which is characterized by having a gate and which normally changes with one potential change of the clock signal can be treated as a circuit which is synchronous with the flip-flop circuit which changes with the other potential change during the test. A flip-flop circuit that normally changes with one potential change of a clock can be connected in a scan path composed of a flip-flop circuit that changes with another potential change, and a scan test that considers the phase of data change There is no need to generate a pattern, and automation of test pattern generation can be expected.

According to a third aspect of the present invention, in the normal operation mode, the gated clock signal is synchronized with a clock signal having a potential change direction opposite to the potential change direction (one potential change direction) of the gated clock signal (the other potential change direction). To capture input data,
The data fetched in synchronization with the other potential change direction of the clock signal is output from the data output terminal, and the inverted data is output from the inverted data output terminal. In the test system mode, the data is synchronized with one potential change direction of the clock signal. In the test scan mode, the input data captured in the test system mode is output from the scan data output terminal in synchronization with the scan slave signal, or the input scan data is captured in synchronization with the scan master clock signal And outputting the captured input scan data from the scan data output terminal as output scan data. In the test system mode and the test scan mode, the data output from the data output terminal and the inverted data output from the inverted data output terminal It is characterized in that each flip-flop circuit is fixed to a predetermined logic level, and a flip-flop circuit which normally changes with one potential change of a clock signal is treated as a circuit synchronized with a flip-flop circuit which changes with another potential change during a test. A flip-flop circuit that normally changes with one potential change of the clock can be connected in a scan path composed of the flip-flop circuit that changes with the other potential change, and the phase of the data change is considered. There is no need to generate a scan test pattern, and automation of test pattern generation can be expected.

According to a fourth aspect of the present invention, an output of the first inversion gate is provided through a first inversion gate which receives and inverts input data and a first transmission gate which is controlled to be conductive based on a clock signal. The second to receive and reverse
Receiving the output of the second inverting gate and inverting the output of the second inverting gate, and applying the inverted output to the input of the second inverting gate via a second transmission gate that is controlled to be conductive based on an inverted clock signal. A third inversion gate;
An output of the second inversion gate or a test enable signal via a third transmission gate whose conduction is controlled based on the inverted test enable signal and a fourth transmission gate whose conduction is controlled based on the inverted clock signal. A fourth inversion gate that receives and outputs the output of the first inversion gate via the fifth transmission gate and the fourth transmission gate whose conduction is controlled, and receives an output of the fourth inversion gate. A fifth inverting gate that inverts the inverted output to an input of the fourth inverting gate via a sixth transmission gate that is conductively controlled based on a clock signal; 7
A sixth inverting gate that receives and inverts the output of the fifth inverting gate via the transmission gate, and inverts the output of the sixth inverting gate, and inverts the inverted output based on the inverted scan master clock signal. A seventh inversion gate to be applied to the input of the sixth inversion gate via an eighth transmission gate whose conduction is controlled in accordance with an inversion clock signal and a ninth transmission gate whose conduction is controlled based on an inverted clock signal; An eighth inversion gate which receives and inverts the signal, a tenth transmission gate whose conduction is controlled based on a scan master clock signal, and an eleventh transmission gate whose conduction is controlled based on a scan slave clock signal. The output of the inverting gate of
A ninth inversion gate receiving and inverting an output of the seventh inversion gate via the transmission gate and the eleventh transmission gate, and outputting an inversion output as output scan data; and a ninth inversion gate. A tenth inversion gate for receiving an output, inverting the inverted output, applying an inverted output to an input of the ninth inversion gate via a twelfth transmission gate, which is controlled to be conductive based on an inverted scan slave clock signal; A NAND (NAND) gate that receives a signal and an output of the fourth inverting gate and provides output data, and a NOR that receives a test enable signal and an output of the fifth inverting gate and provides inverted output data ( NOR) gate, and usually changes with one potential change of the clock signal. The flip-flop circuit can be treated as a circuit that is synchronous with the flip-flop circuit that changes during the test with the other potential change, and the flip-flop circuit that normally changes with one potential change of the clock is changed with the other potential change. It can be connected in a scan path composed of a flip-flop circuit that changes, and it is not necessary to generate a scan test pattern in consideration of the phase of data change, and automation of test pattern generation can be expected.

According to a fifth aspect of the present invention, in a normal operation mode, clock control data for selectively controlling a system clock signal is received as input data, and a control signal is output as output data. 4. A plurality of said serially transferred data.
Or a flip-flop circuit for scan path according to 4 above,
Receiving output data and a system clock signal of the corresponding scan path flip-flop circuit, and selectively outputting a gated clock signal based on the output data when the scan path flip-flop circuit is in a normal operation mode. Operating in synchronization with a plurality of gate circuits and a gated clock signal selectively output from the gate circuit, and taking in input data in synchronization with the gated clock signal in one potential change direction in a normal operation mode Output the data taken in synchronism with the gated clock signal in the other potential change direction. At the time of the test, data given from the last flip-flop circuit of the scan path flip-flop circuit is transferred in series and A flip-flop circuit that outputs transfer data from The gated clock signal receiving circuit described above is characterized in that it operates in a gated clock mode during a normal operation, while all flip-flop circuits operate in the same manner for a clock signal during a scan test. Thus, the design for testability can be implemented using an automation tool.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing symbols of a clock control flip-flop circuit capable of performing a common one-phase scan test, which is a flip-flop circuit according to an embodiment of the present invention. FIG. 4 shows an operation timing chart.

In FIG. 1, the flip-flop circuit is
Data input terminal (D) and clock input terminal (CPN)
A scan data input terminal (SI), a test enable input terminal (TE) for receiving a test enable signal for switching between a normal operation mode and a test mode, and a scan enable signal for switching between a test system mode and a test scan mode in the test mode Has a scan enable input terminal (SE), a data output terminal (Q), an inverted data output terminal (QN), and a scan data output terminal (SO). The test mode is further switched between the test system mode and the test scan mode by using the scan enable signal, and as shown in the timing chart of FIG. Time is the clock At the falling edge of the signal, the data at the data input terminal is fetched, the data is output to the data output terminal, and the inverted data is output to the inverted data output terminal. As shown in the timing chart of FIG. In the test system mode in which the scan enable signal is at the low level, the data of the data input terminal is fetched at the rising edge of the clock signal,
The data is output to the scan data output terminal, and in the test scan mode in which the test enable signal and the scan enable signal are at the high level, the data of the scan data input terminal is captured at the rising edge of the clock signal, and the data is output to the scan data output terminal. Output. In the test system mode and the test scan mode, the data output is fixed at a high level and the inverted data output is fixed at a low level.

As described above, in the normal operation mode, the flip-flop circuit, which operates in response to the gated clock signal, changes the potential direction of the gated clock signal (one potential change direction) which takes in data. The input data is fetched in synchronization with the clock signal in the opposite potential change direction (the other potential change direction), and the fetched data is output from the data output terminal in synchronization with the other potential change direction of the clock signal, and the inverted data is output. Is output from the inverted data output terminal, and in the test system mode,
Input data is fetched in synchronization with one of the potential changes of the clock signal, and the fetched input data is output from the scan data output terminal. In test scan mode, input scan is synchronized with one of the potential changes of the clock signal. Captures data and outputs the captured input scan data as scan data from the scan data output terminal. In the test system mode and test scan mode, the output data output from the data output terminal and the inverted data output from the inverted data output terminal It is characterized in that output data is fixed to a predetermined logic level.

FIG. 5 is a diagram showing a configuration of a flip-flop circuit according to an embodiment of the present invention.
FIG. 3 is a diagram showing a specific circuit configuration of the flip-flop circuit shown in FIG.

In FIG. 5, the flip-flop circuit is
A first inversion gate I1 for receiving and inverting input data;
A second inversion gate I2 that receives and inverts an output of the first inversion gate I1 via a first transmission gate T1 that is controlled to be conductive based on a clock signal, and receives an output of the second inversion gate I2. A third inverting gate I3 for inverting the inverted output to an input of a second inverting gate I2 via a second transmission gate T2 whose conduction is controlled based on an inverted clock signal; A fourth inversion gate I4 via a fourth inversion gate I4 and a third transmission gate T3 which is controlled to be conductive based on a scan enable signal
5 which receives the output of the first inversion gate I1 through the fourth transmission gate T4 whose conduction is controlled based on the output of the fourth inversion gate or the inversion scan enable signal and inverts the fifth output.
Gate I5 and a fifth transmission gate T whose conduction is controlled based on an inversion test enable signal
5, and a seventh transmission gate T7 whose conduction is controlled based on the output of the second inversion gate I2 or the test enable signal via the sixth transmission gate T6 whose conduction is controlled based on the inverted clock signal
A sixth inverting gate I6 which receives and inverts the output of the fifth inverting gate I5 via the sixth transmission gate T6; and receives and inverts the output of the sixth inverting gate I6, and inverts the inverted output to a clock signal. Through an eighth transmission gate T8 whose conduction is controlled based on
Inverting gate I7 applied to the input of the inverting gate I6 of
And a seventh inversion gate I via a ninth transmission gate T9 whose conduction is controlled based on a clock signal.
An eighth inversion gate I8 which receives and inverts the output of the seventh inversion gate, and a tenth transmission gate T10 which inverts and receives the output of the eighth inversion gate I8 and conducts the inverted output based on the inverted clock signal. A ninth inverting gate I9 for supplying an inverting output as output scan data to an input of an eighth inverting gate I8 via an inverting test enable signal and an output of the sixth inverting gate I6. NAND gate R1 to be applied
And a NOR (NO) for receiving the test enable signal and the output of the seventh inverting gate I7 to provide inverted output data
R) It comprises a gate R2.

As described above, in the above embodiment, the flip-flop circuit that normally changes at the falling edge of the clock signal can be handled as a circuit that is synchronous with the flip-flop circuit that changes at the rising edge during the test. Thus, a flip-flop circuit that normally changes at the falling edge of the clock can be connected in a scan path including the flip-flop circuit that changes at the rising edge. Further, there is no need to generate a scan test pattern in consideration of the phase of data change, and automation of test pattern generation can be expected.

FIG. 6 is a diagram showing symbols of an independent two-phase scan testable clock control flip-flop circuit which is a flip-flop circuit according to an embodiment of the present invention. FIG. 9 shows an operation timing chart.

In FIG. 6, the flip-flop circuit is
Data input terminal (D) and clock input terminal (CPN)
A scan data input terminal (SI), a test enable input terminal (TE) to which a test enable signal for switching between a normal operation mode and a test mode is input, and a scan master clock signal for capturing data supplied to the scan data input terminal And a scan slave clock input terminal (B) supplied with a clock signal or a scan slave clock signal for outputting data captured and held by the scan master clock signal to a scan data output terminal. ), A data output terminal (Q), an inverted data output terminal (QN), and a scan data output terminal (SO), and switches between a normal operation mode and a test mode using a test enable signal. , Clock signal The test system mode and the test scan mode are switched depending on whether to drive the scan data master clock signal and the scan data slave clock signal, and the normal operation mode in which the test enable signal is at a low level is shown in the timing chart of FIG. As shown, at the falling edge of the clock signal, the data at the data input terminal is fetched, the data is output at the data output terminal, and the inverted data is output at the inverted data output terminal, and the test enable signal is synchronized with the clock signal at the high level. In the test system mode in which the operation is performed as shown in FIG.
In the test scan mode in which the data at the data input terminal is fetched at the rising edge of the clock signal and the test enable signal is at a high level and operates in synchronization with the scan master clock signal and the scan slave clock signal, as shown in the timing chart of FIG. When the scan master clock signal is at the high level, the data of the scan data input terminal is captured, and when the scan slave clock signal is at the high level, the data captured by the clock signal or the scan master clock signal is captured and held last. The output data is output to a scan data output terminal. In the test system mode and the test scan mode, the data output terminal is fixed at a high level and the inverted data output terminal is fixed at a low level.

As described above, in the normal operation mode, the potential change direction (one potential change direction) of the gated clock signal to which the flip-flop circuit which operates upon receiving the gated clock signal takes in data is used. The input data is fetched in synchronization with the clock signal in the opposite potential change direction (the other potential change direction), and the fetched data is output from the data output terminal in synchronization with the other potential change direction of the clock signal, and the inverted data is output. Is output from the inverted data output terminal, and in the test system mode,
Input data is fetched in synchronization with one potential change direction of the clock signal, and in the test scan mode, the input data fetched in the test system mode is output from the scan data output terminal in synchronization with the scan slave signal,
Alternatively, input scan data is captured in synchronization with the scan master clock signal, and the captured input scan data is output as output scan data from the scan data output terminal, and is output from the data output terminal in the test system mode and the test scan mode. The data and the inverted data output from the inverted data output terminal are each fixed to a predetermined logic level.

FIG. 10 is a diagram showing a configuration of a flip-flop circuit according to an embodiment of the present invention, and is a diagram showing a specific circuit configuration of the flip-flop circuit shown in FIG.

In FIG. 10, a flip-flop circuit includes a first inversion gate I1 for receiving and inverting input data.
1 and a second inversion gate I1 that inverts the output of the first inversion gate I11 via the first transmission gate T11 that is controlled to be conductive based on the clock signal.
2 and the output of the second inverting gate I12 for inversion,
A third inversion gate I1 for applying an inversion output to an input of the second inversion gate I12 via a second transmission gate T12 whose conduction is controlled based on an inversion clock signal.
3 and a third transmission gate T13 whose conduction is controlled based on the inversion test enable signal and a fourth transmission gate T14 whose conduction is controlled based on the inverted clock signal.
12 via a fifth transmission gate T15 and a fourth transmission gate T14, the conduction of which is controlled based on the output of T.12 or a test enable signal.
A fourth inversion gate I14 that receives and inverts the output of the inversion gate I11, and a sixth transmission gate that inverts and receives the output of the fourth inversion gate I14, and controls the conduction of the inverted output based on the clock signal. A fifth inverting gate I15 applied to the input of the fourth inverting gate I14 via T16 and an output of the fifth inverting gate I15 via a seventh transmission gate T17 controlled to be conductive based on a clock signal. A sixth inversion gate I16 for inverting the output signal, an eighth transmission gate T18 for inverting the output of the sixth inversion gate I16 in response to the output of the sixth inversion gate I16, and controlling the inverted output based on the inverted scan master clock signal, and an inverted clock signal A sixth inversion gate via a ninth transmission gate T19 controlled to be conductive based on 16 and seventh inverting gate I17 given to the input of the eighth receiving and inverting an input scan data
An inversion gate I18 via an inversion gate I18, an eleventh transmission gate T20 whose conduction is controlled based on a scan master clock signal, and an eleventh transmission gate T21 whose conduction is controlled based on a scan slave clock signal Output or the eighth transmission gate T18 and the eleventh transmission gate
The ninth inversion gate I19 which receives and inverts the output of the seventh inversion gate I17 via the transmission gate T21 of FIG.
And a twelfth transmission gate T2 whose output is inverted based on the output of the ninth inversion gate I19 and whose conduction is controlled based on the inverted scan slave clock signal.
2 to the input of the ninth inverting gate I19 via
0 inverting gate I20, a NAND gate R11 that receives an inverting test enable signal and the output of the fourth inverting gate I14 and provides output data, and a test enable signal and an output of the fifth inverting gate I15. NOR gate R receiving and providing inverted output data
12 is provided.

Even in such an embodiment, the same effect as in the above embodiment can be obtained.

FIG. 11 is a diagram showing a configuration of a scan path test system according to an embodiment of the present invention, and FIG. 12 is a diagram showing a timing chart of the system shown in FIG.

In FIG. 11, this system uses the above-mentioned flip-flop circuit for a circuit on which a gated clock is designed. In a normal operation mode, clock control data for selectively controlling a system clock signal is transmitted. A plurality of clock control flip-flop circuits 1 of the above-described embodiment, which receive input data and output a control signal as output data, and input data or input scan data are serially transferred during a test, and a corresponding flip-flop circuit Selector circuit 3 having a plurality of AND gates 2 for receiving flip-flop circuit 1 and selectively outputting a gated clock signal based on a control signal during normal operation mode And a gate selectively output from AND gate 2 It operates in synchronization with the clock signal. In the normal operation mode, it takes in input data in synchronization with one potential change direction, for example, the rising edge of the gated clock signal, and receives the input data in the other potential change direction, for example, the falling edge of the gated clock signal. Synchronously fetched data is output, and at the time of a test, data supplied from the last flip-flop circuit of the flip-flop circuit 1 is transferred in series, and the scan flip-flop circuit 4 from which the transfer data is output from the last stage is output. It has a system circuit 5 provided.

In the normal operation mode in which the test enable signal is at a low level, the flip-flop circuit 1 is used as a gated clock signal control flip-flop circuit that operates in synchronization with the falling edge of the system clock signal. In the test mode in which the signal is at the high level, the flip-flop circuit operates as a flip-flop circuit which takes in and outputs data at the rising edge of the system clock signal, thereby operating in synchronization with the scanning flip-flop circuit 4 in the system circuit 5. Can be treated as a loop circuit. In the test mode, since the control signal of the clock control flip-flop circuit 1 is fixed at a high level, the gated clock signal changes exactly the same as the system clock signal. As a result, all the flip-flop circuits 4 that operate with the gated clock signal in the system circuit 5
And the flip-flop circuit 1 for clock control operate in synchronization with each other in the test mode.

Flip-flop circuit 1 for clock control
The scan data input terminal (SI) and the scan data output terminal (SO) are sequentially connected to form a scan path. This scan path is the system circuit 5
Are connected to a scan path constituted by the flip-flop circuits 4 in FIG. The first stage of the scan path is connected to the scan data input terminal (SI), and the last stage is connected to the scan data output terminal (SO). In the test scan mode, from the scan data input terminal (SI) to the scan data output terminal (SO) Operates as a system register.

In FIG. 12, when the test enable signal goes high and the system enters the test mode, the control signal of the flip-flop circuit 1 for clock control is fixed at the high level. It will be exactly the same change.

Therefore, in this system, during normal operation, the operation is performed by the gated clock method. On the other hand, at the time of the scan test, all flip-flop circuits operate in the same manner with respect to the clock signal. Testability designs can be implemented using automation tools.

[0032]

As described above, according to the present invention, the semiconductor memory device operates according to the gated clock system in the normal operation, and operates in the same manner as the scan path flip-flop circuit in the test operation. The connection can be made during the scan path, and the design for facilitating the test of the circuit adopting the gated clock method can be implemented by using the design automation tool. As a result, the design for testability can be easily and quickly performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing symbols of a flip-flop circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an operation timing chart of FIG. 1;

FIG. 3 is a diagram showing an operation timing chart of FIG. 1;

FIG. 4 is a diagram showing an operation timing chart of FIG. 1;

FIG. 5 is a diagram showing a configuration of a flip-flop circuit according to an embodiment of the present invention.

FIG. 6 is a diagram showing symbols of a flip-flop circuit according to an embodiment of the present invention.

FIG. 7 is a diagram showing an operation timing chart of FIG. 6;

FIG. 8 is a diagram showing an operation timing chart of FIG. 6;

FIG. 9 is a diagram showing an operation timing chart of FIG. 6;

FIG. 10 is a diagram showing a configuration of a flip-flop circuit according to one embodiment of the present invention.

FIG. 11 is a diagram showing a configuration of a scan path test system according to an embodiment of the present invention.

FIG. 12 is a diagram showing an operation timing chart of FIG. 11;

FIG. 13 is a diagram showing one configuration of a conventional circuit employing a gated clock system.

14 is a diagram showing an operation timing chart of FIG.

[Explanation of symbols]

 Reference Signs List 1 flip-flop circuit for clock control 2 AND gate 3 selector circuit 4 flip-flop circuit for scan 5 system circuit I1 to I9, I11 to I20 inversion gate T1 to T22 transmission gate R1, R2, R11, R12 logic gate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 31/28-31/3187 G06F 11/20 360

Claims (5)

(57) [Claims] In a normal operation mode, input data is taken in synchronization with a clock signal having a potential change direction (the other potential change direction) opposite to the potential change direction of the gated clock signal (one potential change direction). The data fetched in synchronization with the other potential change direction of the clock signal is output from the data output terminal, and the inverted data is output from the inverted data output terminal. In the test system mode, the data is synchronized with one potential change direction of the clock signal. Input test data, and output the input data from the scan data output terminal.In test scan mode, input scan data is input in synchronization with one of the potential changes of the clock signal. The scan data is output from the scan data output terminal as scan data. A flip-flop circuit for a scan path, wherein in a strike scan mode, output data output from the data output terminal and inverted output data output from the inverted data output terminal are fixed to predetermined logic levels, respectively. 2. A first inverting gate receiving and inverting input data, and a first inverting gate receiving and inverting an output of the first inverting gate via a first transmission gate controlled to be conductive based on a clock signal. And an inverting gate receiving the output of the second inverting gate, inverting the inverted output, and inverting the inverted output to an input of the second inverting gate via a second transmission gate controlled to conduct based on an inverted clock signal. A third inverting gate for applying, a fourth inverting gate for receiving and inverting input scan data, and a third inconductivity controlled based on a scan enable signal
Receiving and inverting the output of the first inversion gate via the transmission gate of the fourth inversion gate or the output of the first inversion gate via a fourth transmission gate whose conduction is controlled based on the inversion scan enable signal; An output or test enable of the second inversion gate via an inversion gate, a fifth transmission gate whose conduction is controlled based on an inversion test enable signal, and a sixth transmission gate whose conduction is controlled based on an inversion clock signal A seventh transmission gate whose conduction is controlled based on a signal;
A sixth inversion gate that receives and inverts the output of the fifth inversion gate via the transmission gate, and inverts and receives the output of the sixth inversion gate, and controls the conduction of the inverted output based on a clock signal A seventh inversion gate applied to an input of the sixth inversion gate via an eighth transmission gate, and a seventh inversion gate via a ninth transmission gate controlled to be conductive based on a clock signal An inverting gate that receives and inverts the output of the eighth inverting gate; and an inverting gate that receives and inverts the output of the eighth inverting gate, and inverts the inverted output through a tenth transmission gate whose conduction is controlled based on an inverted clock signal. A ninth inverting gate, which is supplied to an input of an eighth inverting gate and outputs an inverted output as output scan data; NAND with a signal and an output of the sixth inverting gate to provide output data
A flip-flop circuit for a scan path, comprising: a gate; and a NOR gate that receives a test enable signal and an output of the seventh inverting gate and provides inverted output data. 3. In a normal operation mode, input data is fetched in synchronization with a clock signal having a potential change direction (the other potential change direction) opposite to the potential change direction of the gated clock signal (one potential change direction). The data fetched in synchronization with the other potential change direction of the clock signal is output from the data output terminal, and the inverted data is output from the inverted data output terminal. In the test system mode, the data is synchronized with one potential change direction of the clock signal. In the test scan mode, the input data captured in the test system mode is output from the scan data output terminal in synchronization with the scan slave signal, or the input scan data is synchronized in synchronization with the scan master clock signal. Captures and captures the input scan data from the scan data output terminal In the test system mode and the test scan mode, the data output from the data output terminal and the inverted data output from the inverted data output terminal are fixed to predetermined logic levels, respectively. Scan path flip-flop circuit. 4. A first inverting gate for receiving and inverting input data, and a first inverting gate for receiving and inverting an output of the first inverting gate via a first transmission gate controlled to be conductive based on a clock signal. And an inverting gate receiving the output of the second inverting gate, inverting the inverted output, and inverting the inverted output to an input of the second inverting gate via a second transmission gate controlled to conduct based on an inverted clock signal. And a third transmission gate controlled to be conductive based on an inverted test enable signal and a fourth transmission gate controlled to be conductive based on an inverted clock signal. A fifth transmission gate, which is controlled to be conductive based on an output or a test enable signal; A fourth inverting gate that receives and inverts the output of the first inverting gate via a transmission gate, and inverts and receives the output of the fourth inverting gate, and controls the conduction of the inverted output based on a clock signal A fifth inverting gate applied to the input of the fourth inverting gate via a sixth transmission gate, and a fifth inverting gate via a seventh transmission gate which is controlled to be conductive based on a clock signal. A sixth inversion gate for receiving and inverting the output, an eighth transmission gate and an inversion clock for receiving and inverting the output of the sixth inversion gate, and inverting the inversion output based on the inversion scan master clock signal A signal is supplied to the input of the sixth inverting gate via a ninth transmission gate controlled to be conductive based on a signal. A seventh inverting gate, an eighth inverting gate for receiving and inverting input scan data, a tenth transmission gate that is controlled to be conductive based on a scan master clock signal, and a conductive control that is controlled to be performed based on a scan slave clock signal. Eleventh
Receiving the output of the eighth inversion gate via the transmission gate or the output of the seventh inversion gate via the eighth transmission gate and the eleventh transmission gate, and inverting the inverted output. A ninth inverting gate that outputs data as data, and a twelfth transmission gate that receives and inverts the output of the ninth inverting gate and inverts the inverted output based on an inverted scan slave clock signal. A tenth inversion gate applied to the input of the nine inversion gates; and a NAND (NAND) for receiving the inversion test enable signal and the output of the fourth inversion gate and providing output data
A flip-flop circuit for a scan path, comprising: a gate; a NOR gate that receives a test enable signal and an output of the fifth inverting gate and provides inverted output data. 5. In a normal operation mode, clock control data for selectively controlling a system clock signal is received as input data, and a control signal is output as output data. In a test, input data or input scan data is transferred in series. 5. The scan path flip-flop circuit according to claim 1, 2, 3 or 4, wherein the scan path flip-flop circuit receives output data and a system clock signal of the corresponding scan path flip-flop circuit. A plurality of gate circuits that selectively output a gated clock signal based on the output data when in an operation mode; and operate in synchronization with the gated clock signal that is selectively output from the gate circuit. In the operation mode, the gated clock signal in one potential change direction Input data, and outputs the captured data in synchronization with the gated clock signal in the other potential change direction. During a test, data supplied from the last flip-flop circuit of the scan path flip-flop circuit is serially connected. A scan path test system comprising a gated clock signal receiving circuit provided with a flip-flop circuit which is transferred to the memory and outputs transfer data from a final stage.