KR19990036456A - Integrated circuit device - Google Patents

Abstract

The number of variable delay circuits of the DLL circuit is reduced and the circuit scale is reduced.

1. An integrated circuit device having an internal circuit (3) operating at a timing with a predetermined phase relationship with a supplied clock (CLK0), characterized in that the internal circuit (3) comprises a variable delay circuit A divider circuit 4 for dividing the frequency of the clock CLK0 to generate a first reference clock CLK1, and a timing generator for generating a second reference clock CLK2 by synchronizing the first reference clock CLK1 with the timing of the timing signal N4 The phase of the first reference clock CLK1 is compared with the phase of the variable clock N7 delayed by the second reference clock for a predetermined time and the delay control signal N9 Control circuit 8, 9 for giving the phase comparison / control circuit 8, By using the variable delay circuit 2 as a DLL circuit, it is possible to reduce the circuit scale.

Description

Integrated circuit device

The present invention relates to an improvement of a DLL circuit for generating a timing signal in an internal circuit that operates at a predetermined phase timing with respect to an external clock, and an integrated circuit having a DLL circuit capable of reducing the scale of the circuit by omitting the variable delay circuit ≪ / RTI >

In recent years, memory devices have been required to operate at speeds exceeding 100 MHz. A delay, lock loop (DLL) circuit or the like has been provided therein to adjust the phase of the external clock and the data output signal, And the delay and the unbalance of the access time are suppressed. The system side that controls the memory device supplies a clock to the memory device, gives data or an address in synchronization with the clock, and receives the output data in synchronization with the clock.

This DLL circuit is disclosed in Japanese Patent Application No. Hei 8-339988 dated December 19, 1996. 1 is a diagram showing an example of a timing signal generating circuit using the DLL circuit.

FIG. 1 shows an input buffer 1 for inputting an external clock CLK to generate an internal clock N1, a variable delay circuit 2 for delaying the internal clock N1 by a predetermined time to generate a timing signal N4, A variable delay circuit 10 for delaying the first reference clock N2 and a dummy data output buffer 6 and a dummy input buffer 7 A phase comparator 8 for comparing the phase of the variable clock N7 passed through the variable delay circuit 7 with the phase of the first reference clock N2 divided by the frequency divider 4 and a phase comparator 8 responsive to the detection signal N8 of the phase comparator 8, And a delay control circuit 9 for generating a delay control signal N9 for controlling the delay time of the delay circuits 2 and 10 is shown. The data output buffer 3, which is an internal circuit, outputs the data DQ output from the memory in response to the timing signal N4.

The variable delay circuit 10, the dummy circuits 6 and 7, the phase comparator 8 and the delay control circuit 9 constitute a DLL circuit. The delay amount of the variable delay circuit 10 is controlled by the phase comparator 8 and the delay control circuit 9 such that the phases of the first reference clock N2 and the variable clock N7 coincide with each other. As a result, the phase of the external clock CLK and the output N6 of the dummy data output buffer 6 coincide with each other. The delay amount of the variable delay circuit 2 is also controlled by the same delay control signal N9 so that the data output DQ output in response to the timing signal N4 is also synchronized with the phase of the external clock CLK.

The frequency divider 4 shown in Fig. 1 is provided in response to the fact that the phase comparison operation in the phase comparator 8 becomes difficult and the power consumption increases as the frequency of the clock CLK becomes higher. The frequency of the clock CLK is set to Thereby generating a low-frequency reference clock N2.

However, in a memory device or the like, a plurality of data outputs DQ are provided, and accordingly, it is necessary to provide a plurality of circuits shown in Fig. Although it is possible to make the input buffer 1 and the 1 / N frequency divider 4 common, two variable delay circuits of a large-scale circuit configuration must be provided in each group, and the circuit shown in Fig. Dora is against the demand.

Therefore, an object of the present invention is to provide an integrated circuit device in which a timing signal generating circuit using a DLL circuit is simplified.

It is another object of the present invention to provide an integrated circuit device in which a variable delay circuit is omitted in a timing signal generating circuit using a DLL circuit.

In order to achieve the above object, the present invention provides a variable delay circuit in a DLL circuit, wherein the variable delay circuit is omitted, and instead, the phase of the first reference clock generated by the frequency divider is matched to the timing of the timing signal generated from another variable delay circuit And a timing synchronization circuit for generating a second reference clock is provided. Then, the divided first reference clock and the variable clock delayed by the second reference clock are compared by the phase comparator, and the delay amount of the variable delay circuit is controlled so that the phases of both clocks coincide with each other. As a result, it is possible to omit the variable delay circuit by one, and furthermore, the DLL circuit using the divided clock can be constituted.

In order to achieve the above object, the present invention provides an integrated circuit device having an internal circuit operating at a timing of a predetermined phase relationship with a supplied clock,

A variable delay circuit for delaying the clock for a predetermined time to generate a timing signal in the internal circuit,

A frequency divider circuit for dividing a frequency of the clock to generate a first reference clock;

A timing synchronizing circuit for synchronizing the first clock with the timing of the timing signal to generate a second reference clock;

A phase comparison / control circuit that compares the phases of the variable clock obtained by delaying the second reference clock by a predetermined time and the phase of the first reference clock and gives a delay control signal to the variable delay circuit so as to match the phases of the two clocks .

According to the above configuration, the variable delay circuit can be omitted in the circuit configuration of the above-mentioned prior art, and the demand for high integration can be satisfied.

Further, in the above invention, the first reference clock has a pulse width of one cycle of the clock, the second reference clock has an inversion level of the first reference clock, and the phase comparison / The delay amount of the variable delay circuit is controlled so that the phases of the rising or falling section of the first reference clock coincide with the rising or falling section of the variable clock.

According to the present invention, the timing of the operation of the internal circuit can be synchronized with the timing after one cycle of the supplied external clock.

Further, in the above invention, the frequency dividing circuits are commonly provided, and a plurality of sets of the variable delay circuit, the timing synchronizing circuit, and the phase comparing / controlling circuit are provided. Therefore, even when a plurality of DLL circuits are provided in correspondence to the case where a plurality of data output terminals are provided, high integration is not hindered.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing an embodiment of a timing signal generating circuit using a DLL circuit. Fig.

2 is a view showing a first embodiment of the present invention.

3 is a timing chart showing the operation of the first embodiment.

4 is a circuit diagram showing an example of a variable delay circuit;

5 shows a delay control circuit;

6 is a circuit diagram of a phase comparator.

7 is a timing chart showing the operation of Fig.

8 is a circuit diagram for the second embodiment;

9 is an operation timing chart of Fig.

10 is a circuit diagram of a 1/2 phase shift circuit 40. Fig.

11 is a view showing a third embodiment.

12 is an operation timing chart of Fig.

Description of the Related Art

1: Input buffer

2: Variable delay circuit

3: Data output buffer, internal circuit

4: Divider

5: Timing synchronization circuit

6, 7: Dummy circuit

8: Phase comparator

9: delay control circuit

N1, CLK0: Clock

N2, CLK1: first reference clock

N3, N5: Reference clock

N7: Variable Clock

N8: Phase comparison detection signal

N9: Delay control signal

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. However, the examples of such embodiments do not limit the technical scope of the present invention.

2 is a diagram showing an example of the first embodiment of the present invention. In Fig. 2, the same reference numerals are given to portions corresponding to Fig. In Fig. 2, the variable delay circuit 10 in Fig. 1 is omitted, and a timing synchronization circuit 5 is provided instead.

The external clock CLK is supplied to the input buffer 1, and the input buffer 1 detects an external clock to generate an internal clock N1. The internal clock N1 is delayed for a predetermined time by the variable delay circuit 2 to generate the timing signal N4. In response to the timing signal N4, the data output buffer 3 outputs data DATA from a memory or the like as a data output DQ.

The internal clock N1 is frequency divided by 1 / N by a 1 / N divider 4 to generate a first reference clock N2. The first reference clock N2 is supplied to the phase comparator 8. Further, the timing synchronization circuit 5 generates the second reference clock N5 by synchronizing the first reference clock N2 with the timing of the timing signal N4. In the embodiment of the present invention, the variable delay circuit 2 is also used as the delay circuit in the DLL circuit, and the first reference clock divided by the delayed timing is combined to output the second reference clock N5 to the dummy circuits 6 and 7 . As a result, the variable clock N7 of the output of the dummy input buffer 7 is a divided clock, which is a clock having a delay amount of the variable delay circuit 2 and a delay amount of the dummy circuits 6 and 7.

3 is a timing chart showing the operation of the example of the first embodiment of Fig. As described above, the external clock CLK generates an internal clock N1 (CLK0) having a constant delay by the input buffer 1. [ In the example of FIG. 3, the frequency divider 4 divides the internal clock N1 (CLK0) by 1/2 to generate the first reference clock N2. The phases of the first reference clock N2 and the internal clock N1 substantially coincide with each other.

Thus, the variable delay circuit 2 delays the internal clock N1 by a predetermined delay amount to generate the timing signal N4. In the figure, the rising section B0 of the internal clock N1 is delayed in the rising section B1 of the timing signal N4. Then, the timing synchronization circuit 5 generates the second reference clock N5 (CLK2) in which the divided first reference clock N2 (CLK1) coincides with the timing of the timing signal N4. The timing synchronization circuit 5 inputs the first reference clock N2 (CLK1) to the D input terminal, the timing signal N4 to the clock terminal, and the second reference clock N5 to the output terminal D flip-flops. As a result, as shown in Fig. 3, the second reference clock N5 becomes a clock obtained by delaying the divided first reference clock N2 by the delay amount of the variable delay circuit 2.

This second reference clock is supplied to the phase comparator 8 via the dummy data output buffer 6 and the dummy input buffer 7 as the variable clock N7. In the example of Fig. 3, the variable clock N7 is a clock whose second reference clock is delayed and inverted by a delay amount of the dummy circuits 6, 7. Therefore, the interval B2 corresponding to the rising interval B0 of the internal clock N1 in the variable clock N7 is the falling interval.

It is not essential that the variable clock is an inverting clock. However, by using the inverted clock, the phase difference between the falling period A2 of the first reference clock synchronized with the rising period Al after one cycle from the rising period B0 of the internal clock N1 and the falling period B2 of the variable clock N7 corresponding to the rising period A1 Can be controlled to coincide with each other. In the case where it is not an inversion clock, the phase comparator 8 may compare the phase of the falling section A2 of the first reference clock N2 with the phase of the variable clock B2. The phase between the first reference clock N2 and the rising section of the variable clock N7 may be compared.

In the example of FIG. 3, since the frequency divider 4 is half divided, the falling interval A2 can be matched to the phase delayed by one cycle of the internal clock.

As described above, in the first embodiment, the number of variable delay circuits can be reduced to one, and the circuit scale of the timing synchronization circuit provided is much smaller. Therefore, in particular, when a plurality of sets of DLL circuits are provided, . That is, the circuit 20 portion in FIG. 2 is provided in common, and the circuit portion 30 is provided for each data output DQ, but the circuit 30 portion is simplified.

Next, specific circuit examples of the variable delay circuit 2, the delay control circuit 9 and the phase comparator 8 constituting the circuit of Fig. 2 are shown.

4 is a circuit diagram showing an example of a variable delay circuit. The delay time is selected by the delay control signals p1 to p (n) (N9 in Fig. 2). This variable delay circuit delays the clock applied to the input terminal IN by a predetermined time and outputs it to the output terminal OUT. The first stage is composed of NAND 711 and inverter 713 and the second stage is composed of NAND 721 and 722 and inverter 723 and the following equation And the n-th stage is composed of NANDs 761, 762, and 763.

One of the delay control signals p1 to p (n) (N9) is at the H level, and all of them are at the L level. Then, only one corresponding NAND 711, 721, ..., 761 is opened by the delay control signal p having the H level, and the clock applied to the input IN is passed. The other NANDs 711, 721, ..., 761 corresponding to the other L-level delay control signal p are closed. As shown in the figure, when the delay control signal p1 is at the H level, the NAND 711 is opened and the delay from the input terminal IN to the output terminal OUT via the inverter 701, the NAND 711, and the inverter 713, A path is formed. Therefore, the gate has a delay of four stages.

When the delay control signal p2 is at the H level, the NAND 721 is opened. Since the inputs of the gate 762 are all at the H level, the output of the inverter 763 is at the H level, and the outputs of the inverters 753, 743, ... are also at the H level in the same manner. Therefore, the NAND 722 is also in the open state. As a result, a delay path from the input terminal IN to the output terminal OUT via the inverter 701 and the gates 721 to 723, 712, and 713 is formed. Therefore, the gate has a delay of six stages.

Hereinafter, as shown in Fig. 4, every time the H level delay control signal p moves to the left, the number of gates in the delay path increases by two gates. This causes jitter in the variable delay circuit. When the delay control signal p (n) is at the H level, it is a delay path of 2 + 2n stages of gates.

Fig. 5 is a diagram of the delay control circuit 9. Fig. 5, a part of the delay control circuit is shown, and the delay control signals p1 to p6 (N9) of the variable delay circuit are shown for convenience of explanation. The delay control circuit is provided with detection signals A to D (N8 in FIG. 2) as a result of phase comparison from the phase comparator, the delay control signal p of the H level is shifted to the right by the signals A and B, The delay control signal p of the H level is shifted to the left by C, D.

Each stage of the delay control circuit has, for example, a latch circuit composed of a NAND gate 612 and an inverter 613 in the first stage. In addition, transistors 614 and 615 for forcibly inverting the states of the latch circuits 612 and 613 by the detection signals A to D are provided. Transistors 616 and 617 are provided to prevent the latch circuits from being inverted by transistors 614 and 615 when they are outside the object of inversion. The circuit of the second stage to the sixth stage also has the same configuration. All of these transistors are N-channel type.

Suppose now that the output p4 of the fourth stage is at the H level. The other outputs are all at the L level. The states of the latch circuits at each stage are as indicated by H and L in Fig. That is, from the first stage to the third stage, in the latch circuit, the NAND output is at the H level and the inverter output is at the L level, whereas in the fourth to sixth stages, the NAND output is at the L level and the inverter output is at the H level. Therefore, the transistors 617, 627, 637, 647, 646, 656, and 666 connected to the gates are in a conductive state. That is, the transistors 647 and 636 of the fourth-stage circuit on both sides of the boundary of the latch state are in a conductive state, and the latch state is reversible by the detection signal B or C .

Thus, for example, when the detection signal C is applied with the H level, the transistor 645 conducts, and the output of the inverter 643 is forcibly driven from the H level to the L level. Therefore, the output of the NAND gate 642 is also switched from the L level to the H level, and the state is latched. The output p4 of the NOR gate 641 becomes the L level and the output of the NOR gate 651 is changed by the change of the output of the inverter 643 to the L level instead of the output of the NAND gate 642, p5 is switched to the H level. As a result, the H-level delay control signal is shifted from p4 to p5. As described with reference to FIG. 4, the H-level delay control signal p shifts to the left, so that the delay path of the variable delay circuit becomes longer and the delay time becomes longer.

On the other hand, when the H level is applied to the detection signal B, the output of the NAND gate 632 of the third-stage latch circuit is forcibly changed to the L level by the above-described operation, and the output of the inverter 633 Is switched to the H level. As a result, the output p3 becomes H level. As a result, the delay path of the variable delay circuit is shortened and the delay time is controlled to be short.

Further, when the output p5 or p3 becomes the H level, the output of the H level is shifted to the right or left respectively by the detection signal A or D this time. That is, the detection signals A and B shift-control the output of the H level to the right and the detection signals C and D shift-control the output of the H level to the left. The detection signals A and D are subjected to shift control when the odd-numbered outputs p1, p3 and p5 are at the H level, and when the even-numbered outputs p2, p4 and p6 are at the H level, do.

Further, at the start of operation, the delay control circuit 9 causes the delay control signal p1 to be at the H level by the reset signal Reset, and sets the delay amount of the variable delay circuit 2 to the smallest state. Therefore, the delay amount of the feedback loop in the DLL circuit is started from the smallest amount, and the timing Al and the timing A2 after one cycle are controlled so that the timing B2 coincides with each other.

6 is a circuit diagram of the phase comparator 8. Fig. The phase comparator has a phase detector 51 for detecting the relationship between the variable clock Vari CLK and the clock phase of the reference clock Ref CLK. The phase detector 51 has two latch circuits composed of NAND gates 501 and 502 and 503 and 504. When the phase of the variable clock Vari CLK with respect to the reference clock Ref CLK is (1) (2) a phase difference of about a predetermined time, and (3) a case in which a delay is longer than a predetermined time. The above three states are detected by the combination of the detection outputs nl to n4.

The sampling pulse generating section 52 includes a NAND gate 505, a delay circuit 506 and a NOR gate 507. When the two clocks Ref CLK and Vari CLK become H level together, the sampling pulse generating section 52 outputs a sampling signal to a node n9 Output. The sampling latch circuit portion 53 samples the detection outputs nl to n4 by the sampling gates 508 to 511 by the sampling signal N9 and latches the sampled signals by the latch circuit composed of the NANDs 512 and 513 and 514 and 515. Therefore, the detection outputs n1 to n4 at the time of sampling are latched in the nodes n5 to n8, respectively.

The ½ frequency divider circuit 54 has a JK flip flop configuration. The NAND gate 520 detects when both of the clocks Vari CLK and Ref CLK are at the H level, divides the detection pulse nl0 by 1/2, Generate n11 and n12. The decode unit 55 decodes the signals of the sampling latched nodes n5 to n8 to set the output of the diode 536 to the H level when the variable clock Vari CLK is ahead of the reference clock Ref CLK, The outputs of the diodes 536 and 540 are set to the L level. When the variable clock Vari CLK is delayed from the reference clock Ref CLK, the output of the diode 540 is set to the H level. The output circuit section 56 outputs the detection signals A to D in response to the reversed phase pulse signals nl1 and n12 in accordance with the output of the decoding section 55. [ The detection signals A to D control the state of the delay control circuit as described above.

7 is a timing chart showing the operation of Fig. In this figure, a state in which the variable clock Vari CLK is ahead of the reference clock Ref CLK, a state in which the phases of both clocks coincide with each other, and a state in which the variable clock Vari CLK is delayed from the reference clock Ref CLK are sequentially shown. That is, since the variable clock Vari CLK is in progress when the sampling pulse n9 is Sl and S2, it is detected, the detection signal C is output to the H level in response to the pulse n12, and the detection signal D H level. When the sampling pulse is S3, the phases coincide with each other, and all the detection signals A to D are at the L level. Furthermore, since the variable clock Vari CLK is delayed in the sampling pulses S4, S5, and S6, it is detected, and in response to the pulse n11, the detection signal A becomes the H level in response to the detection signal B or the pulse nl2.

The above-described operation will be described below in order.

Sampling pulse S1

In this period, since the variable clock Vari CLK is in progress, the variable clock Vari CLK is first brought to the H level first when both of the clocks Vari CLK and Ref CLK are at the L level, the node n2 is latched at the L level, Is latched at the H level. The NAND and inverter 500 are delay circuits that delay the variable clock Vari CLK by a predetermined time. The nodes n3 = H level and the node n4 = H level are similarly latched in the NANDs 503 and 504 as well. Thus, the sampling generator 52 generates a sampling pulse n9 having a width corresponding to the delay time of the delay circuit 506 at the timing at which both the clocks Vari CLK and Ref CLK coincide with the H level, The latch state in the latch unit 51 is sampled, and the latch state is latched in the latch unit 53. [ That is, the states of the nodes n1 to n4 are transferred to the nodes n5 to n8.

Then, the pulse nl0 is generated at the timing when both of the clocks Vari CLK and Ref CLK coincide with the H level. The frequency divider circuit portion 54 is connected to the latch circuits of the NANDs 524 and 525 and the latch circuits of the NANDs 528 and 529 at the gates 526 and 527 and the gates 530 and 531, , And is opened in the non-inverting pulse. Therefore, the pulse n10 is divided by ½.

In the decoder unit 55, the output of the inverter 536 is at the H level and the output of the inverter 540 is at the L level depending on the states of the H, L, H, and L levels of the nodes n5 to n8. Therefore, in response to the pulse n12, the H level of the inverter 536 is set to the H level through the NAND 543 and the inverter 544. Due to the H level of the detection signal C, the H level output of the shift register shifts to the left, and the delay path of the variable delay circuit becomes longer. As a result, the variable clock VariCLK is controlled in the delayed direction.

Sampling pulse S2

As described above, the phase comparator 51 detects that the variable clock Vari CLK is in progress, and the detection signal D becomes H level in response to the pulse n11. Thus, the H level output, which is the delay control signal of the delay control circuit, is shifted to the left in the same manner, and the delay path of the variable delay circuit becomes longer.

Sampling pulse S3

In the timing at which the sampling pulse S3 is output, most of the clocks Vari CLK and Ref CLK are in phase. In the case of having a phase shift within the delay time in the delay circuit 505, when the variable clock Vari CLK is slightly advanced

n1 = H, n2 = L, n3 = L, n4 = H

n5 = H, n6 = L, n7 = L, n8 = H

. This state is shown in Fig. Further, in the case of having a phase shift within the delay time in the delay circuit 505, and when the variable clock Vari CLK is slightly delayed

n1 = L, n2 = H, n3 = H, n4 = L

n5 = L, n6 = H, n7 = H, n8 = L

.

In either case, the decoder unit 55 decodes the output of both the inverters 536 and 540 to the L level, and the detection outputs A to D are all at the L level. As a result, the state of the delay control circuit does not change, and the delay time of the variable delay circuit does not change.

Sampling pulses S4, S5, S6

In this case, the variable clock Vari CLK is delayed. Therefore, the latch state of the phase comparator 51 is

n1 = L, n2 = H, n3 = L, n4 = H

As a result, even in the sampled latch portion 53

n5 = L, n6 = H, n7 = L, n8 = H

. This state is decoded by the decoder unit 55, and the inverter 536 becomes an L level output and the inverter 540 becomes an H level output. Therefore, in response to the pulses n11 and n12, the detection signals B and A become H levels, respectively. As a result, the delay control signal p of the delay control circuit shifts to the right, shortening the delay path of the variable delay circuit to shorten the delay time. Therefore, the variable clock Vari CLK is controlled to proceed.

Second Embodiment

8 is a circuit diagram showing the second embodiment. 9 is an operation timing chart of Fig. Also in the second embodiment, as in the first embodiment, the variable delay circuit in the DLL circuit is omitted, and the frequency division clock of the feedback loop is generated using the delay amount of the variable delay circuit 2 that generates the timing signal N4.

In the second embodiment, the 1 / N divider 4 divides the internal clock N2 with a dividing ratio that is one cycle of the internal clock N1 and has a pulse width that is higher than 1/2. Thereby, the phase comparator 8 can perform phase comparison operation with sufficient margin. Accordingly, as shown in Fig. 9, the divided first reference clock N2 rising at the rising section B0 of the internal clock N1 and falling at the next rising section Al is generated. Therefore, the phase of the falling section A2 is used in the phase comparator 8. [

Then, the 1/2 phase shift circuit 40 shifts the phase of the first reference clock N2 (CLK1) 180 degrees to generate the second reference clock N3 (CLK2). As shown in Fig. 9, the second reference clock N3 is at the H level on both sides of the falling period A2 of the first reference clock N2.

The second reference clock N3 is supplied to the timing synchronization circuit 5. [ In the second embodiment, this timing synchronization circuit 5 is constituted by a D flip-flop circuit. That is, the second reference clock is supplied to the D input terminal, and the timing signal N4 is supplied to the clock terminal. Then, a third reference clock N5 (CLK3) matching the timing of the timing signal N4 with the second reference clock is generated. According to the operation of the D flip-flop, the inverted signal of the level of the second reference clock N3 supplied from the D input terminal in the rising section of the timing signal N4 is output as the inverted output / Q. Therefore, the third reference clock N5 is as shown in Fig.

The third reference clock N5 is supplied to the phase comparator 8 via the dummy data output buffer 6 and the dummy input buffer 7 with the variable clock N7 having a predetermined delay. The phase comparator 8 and the phase control circuit 9 control the phases of the falling period A2 of the first reference clock N2 and the falling period B2 of the variable clock N7 in the same manner as in the first embodiment, The delay control signal N9 is generated.

9, if the interval of the timing signal N4 corresponding to the interval B0 is B3, the third reference clock N5 is generated as indicated by the dotted line, and the falling interval B4 of the variable clock N7 is divided into the interval A2 The delay amount of the variable delay circuit 2 is controlled to be smaller. However, in the process of moving the falling period B2 of the variable clock N7 from the left side to the right side in Fig. 9, the DLL circuit is normally in the locked state, and the period B2 is in the period A2.

In the second embodiment, the 1/2 phase shift circuit 40 generates a second reference clock N3 having a predetermined pulse width before and after the falling period A2 of the first reference clock N2. As described above, when the DLL circuit operation is started, the delay control circuit 9 is reset to set the delay amount of the variable delay circuit 2 to the minimum. Therefore, as a result of the subsequent phase comparison operation, when the phase B2 corresponding to the rising section B0 of the internal clock coincides with the phase of the section A2 of the first reference clock corresponding to the rising section A1 after one clock period from the section B0, The DLL circuit is in the locked state. Thus, in the second embodiment, the third reference clock N5 having the falling period B1 to be matched with the interval A2 of the first reference clock N2 is generated from the second reference clock N3 and the timing signal N4.

Therefore, the 1/2 shift circuit 40 does not need to make the shift amount as rigid as that. When the pulse width of the second reference clock N3 is secured to a certain extent on both sides of the section A2, the operation of the DLL circuit is not affected.

In the second embodiment, the timing synchronization circuit 5 is composed of a D-type flip-flop circuit. By using the D-type flip-flop circuit, it is possible to easily generate the time-reversal clock N5 whose phases are synchronized with the timing signal N4. Furthermore, the D-type flip-flop is a circuit simpler than the circuit of the variable delay circuit 2. [ Therefore, even if the circuit portion 30 is provided with a plurality of data outputs in the drawing, the circuit scale is not so large.

Fig. 10 is a circuit diagram of the 1/2 phase shift circuit 40. Fig. The phase comparator 14, the delay control circuit 15, and the variable delay circuits 11 and 12 are the same as those described in Figs. 6, 5 and 4. Fig. An example of the 1/2 phase shift circuit 40 is a circuit for delaying the first reference clock N2 (CLK1) by the two variable delay circuits 11 and 12 and outputting the first reference clock N2 (CLK1) And a DLL circuit for controlling the phases to coincide with each other. 2, the phase comparator 14 compares the phase of the first reference clock N2 (CLK1) with the phase of the variable clock N12 to give the test signal N14 to the delay control circuit 15 , The delay amounts of the two variable delay circuits 11 and 12 are controlled so that the phases of both clocks coincide with each other by the delay control signal N15.

Further, the delay control circuits 11 and 12 have the same delay amount, and the DLL operation is started after the delay amount is minimized by the reset signal as described in Fig. Therefore, the 1/2 shift clock N3 (CLK2), which is the output of the variable delay circuit 11, necessarily becomes a clock shifted by 180 degrees from the first reference clock N2 (CLK1).

Third Embodiment

11 is a view showing a third embodiment. 12 is an operation timing chart of Fig. The third embodiment differs from the second embodiment shown in Fig. 8 in that the 1/2 phase shift circuit 40 is composed of a D-type flip-flop circuit. The first reference clock CLK1 is supplied to the D input terminal of the D flip-flop 40, and the inverted clock / CLK0 of the internal clock N1 is supplied to the clock input terminal CLK. Then, the second reference clock N3 is generated from the non-inverted output terminal Q. The other structure is the same as that of the second embodiment.

As shown in Fig. 12, the inversion clock / CLK0 of the internal clock N1 (CLK0) is a clock whose phase is delayed by 180 degrees with respect to the internal clock N1 (CLK0). Therefore, the D-type flip-flop 40 sets the phase of the first reference clock N2 (CLK1) at the timing of the inverted clock / CLK0 delayed by 180 degrees to shift the first reference clock N2 (CLK1) The second reference clock N3 (CLK2) generated at the output Q can be generated.

The other operations are the same as in the second embodiment. In the third embodiment, since the 1/2 phase shift circuit is composed of the D-type flip-flop 40, the circuit configuration can be realized with a smaller circuit configuration than the DLL circuit shown in Fig. 10 of the second embodiment.

As described above, according to the present invention, since the timing synchronization circuit is provided in place of the variable delay circuit in the circuit for generating the timing signal using the DLL circuit, the number of variable delay circuits having a large circuit scale can be reduced, The entire circuit scale can be reduced.

Claims (7)

1. An integrated circuit device having an internal circuit that operates at a timing of a predetermined phase relationship with a clock to be supplied, A variable delay circuit for delaying the clock for a predetermined time to generate a timing signal in the internal circuit, A frequency divider circuit for dividing a frequency of the clock to generate a first reference clock; A timing synchronizing circuit for synchronizing the first reference clock with the timing of the timing signal to generate a second reference clock; And a phase comparison / control circuit that compares the phase of the first reference clock with the variable clock obtained by delaying the second reference clock by a predetermined time and gives a delay control signal to the variable delay circuit so as to match the phases of both clocks Wherein the integrated circuit device comprises: The phase comparison and control circuit according to claim 1, wherein the first reference clock has a pulse width of one cycle of the clock, the second reference clock has an inversion level of the first reference clock, And controls the delay amount of the variable delay circuit so that the phase of the rising clock or the falling clock of the reference clock coincides with the phase of the rising clock or the falling clock of the variable clock. The integrated circuit device according to claim 1 or 2, wherein the frequency divider circuit is provided in common, and a plurality of sets of the variable delay circuit, the timing synchronization circuit, and the phase comparison / control circuit are provided. 1. An integrated circuit device having an internal circuit that operates at a timing of a predetermined phase relationship with a clock to be supplied, A variable delay circuit for delaying the clock for a predetermined time to generate a timing signal in the internal circuit, A frequency divider circuit for dividing a frequency of the clock to generate a first reference clock having a pulse width corresponding to one cycle of the supplied clock; A phase shift circuit for generating a second reference clock in which the phase of the first reference clock is shifted by approximately a half cycle; A timing synchronizing circuit for synchronizing the second reference clock with the timing of the timing signal to generate a third reference clock, A phase comparison / control circuit that compares the phases of the variable clock obtained by delaying the third reference clock by a predetermined time and the phase of the first reference clock to give a delay control signal to the variable delay circuit so as to match the phases of the two clocks Wherein the integrated circuit device comprises: 5. The flip-flop circuit according to claim 4, wherein the timing synchronization circuit includes: a first D-type flip-flop for inputting the second reference clock to a D input terminal and the timing signal to a clock terminal, Circuit. ≪ / RTI > 5. The phase locked loop circuit according to claim 4, wherein the phase shift circuit inputs the first reference clock to the D input terminal, the inverted clock of the supplied clock to the clock terminal, and the second reference clock from the output terminal Type flip-flop circuit. The liquid crystal display device according to any one of claims 4 to 6, characterized in that a plurality of sets of the variable delay circuit, the timing synchronization circuit, and the phase comparison / control circuit are provided in common to the frequency division circuit and the phase shift circuit .