KR970000260B1 - Parallel inputable boudary-scan architecture - Google Patents

Abstract

at least one parallel input-series output shift register which inputs TDIs in parallel according to TDI loading signal and which outputs in series TDIs inputted by synchronized to TCK; a clock generator which the outputs parallel input signal as selection clock by delaying for predetermined time; a selection circuit which successively inputs the TDI loading signal to the parallel input-series output shift register by arranging the counted value and the parallel signal by counting the register selection clock; a TCK generating circuit respectively inputs the TCK to the parallel input-parallel output shift register and the integrated circuit by forming TCK by arranging TCK generating signal and system clock; a TCK generation control part which outputs TCK generating signal by counting as much as TKI number to be inputted to integrated circuit by receiving TCK from the TCK generation circuit.

Description

Boundary scan structure with parallel input processing

1 is a block diagram of a conventional boundary scan structure.

2 is a block diagram of a boundary scan structure capable of parallel input processing according to the present invention.

3 is a circuit diagram of a clock generation unit configured in a boundary scan structure capable of parallel input processing according to the present invention.

4 is a selection circuit diagram configured in a boundary scan structure capable of parallel input processing according to the present invention.

5 is a waveform diagram of a main portion of a clock generator and a selection circuit configured in a boundary scan structure capable of parallel input processing according to the present invention.

6 is a TCK generation circuit diagram configured in a boundary scan structure capable of parallel input processing according to the present invention.

7 is a waveform diagram of a main portion of a TCK generation control unit and a TCK generation circuit formed in a boundary scan structure capable of parallel input processing according to the present invention.

* Explanation of symbols for main parts of the drawings

1: integrated circuit 2: processor

3: address decoder 10: clock generator

20: selection circuit 30: TCK generation control unit

40: TCK generating circuit 50: TCK generating circuit

The present invention relates to a boundary-scan architecture defined by the Institute of Electrical and Electronic Engineers (IEEE). More particularly, the present invention processes a test data input signal in parallel and inputs it to an integrated circuit. A boundary scan structure capable of parallel input processing is possible.

In IEEE, boundary scan structures are needed to monitor whether the components of an integrated circuit perform exactly what is required, or whether each component is correctly connected to each other, or whether each component interacts to perform exactly the required function. Is defined in IEEE 1149.1.

According to this regulation, the boundary scan structure has a test clock (Test Clock: hereinafter, TCK), test data input (Test Data Input: hereinafter, TDI), test data output (Test Data Output: hereinafter, TDO), and test. Test mode select (hereinafter referred to as TMS) signals are required. Here, TCK is a test clock for logic of an integrated circuit according to the IEEE standard, and TDI means test commands and data for testing the logic of the integrated circuit of the above-mentioned standard. TDI is applied to logic for sampling and testing at the rising edge of TCK.

In addition, the TDO is a test command and data output in series to test logic from the integrated circuit according to the above-mentioned regulations, and the TDO must change state at the falling edge of the TCK. In addition, the TMS is a signal for setting a mode for testing the logic of the integrated circuit according to the above-mentioned regulations, and is sampled at the top edge of the TCK and output. A conventional simple structure for boundary scanning an integrated circuit using the signals described above is shown in FIG.

In the drawing, reference numeral 1 denotes an integrated circuit for boundary scanning using TCK, TDI, TDO, and TMS as described above, and reference symbol 2 denotes a processor for boundary scanning of integrated circuit 1. The address decoder 3 connected to the processor 2 is configured to decode an address signal applied from the processor and selectively apply a clock signal to the D flip-flops D1-D4. At this time, the input terminals D of the D flip-flops D1-D3 are connected to the processor 2 through a data bus, and the output terminals Q are integrated circuits for inputting TCK, TDI, and TMS, respectively. It is connected to the terminals I1, I2 and I3 of 1). In addition, an input terminal D of the D flip-flops D1-D3 is connected to a terminal O1 of the integrated circuit 1 that outputs a TDO, and the output terminal Q is connected to the processor 2 through an address bus. )

That is, the processor 2 stores the TCK, TDI, and TMS in the flip-flops D1, D2, and D3 through the address bus, respectively, and the D-flop flops D1, D2, or D3 using the address decoder 3, respectively. By selectively applying a clock signal to the TCK, the TDI or the TMS is applied to the integrated circuit 1 in synchronization with the TCK. In addition, the processor 2 selectively inputs the TDO of the integrated circuit 1 output in synchronization with the TCK by selectively applying a clock signal to the D flip-flop D4 using the address decoder 3.

However, in this boundary scan structure, TDI must be applied to the integrated circuit in series in synchronization with TCK. Therefore, since the processor 2 takes a long time to input the TDI to the integrated circuit 1, there is a problem that excessive time for boundary scanning is required.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to store boundary TDI in advance, and apply boundary TDI to an integrated circuit by applying a stored TDI to an integrated circuit using a system clock for a processor as a TCK. To provide a boundary scan structure capable of parallel input processing that can be performed in a short time.

A feature of the present invention for achieving this object is a TDI input device for boundary scanning of an integrated circuit, at least one bottle for inputting the TDIs in parallel according to the loading signal and outputting the serially input TDIs in synchronization with the TCK Serial shift registers; A clock generator which receives the parallel input signal and delays the predetermined time and outputs the same as a register selection clock; A selection circuit for sequentially applying the loading signal to the parallel input-serial output shift registers by combining the counted value of the register selection clock and the parallel input signal; A TCK generation circuit that combines a TCK generation signal and a system clock to form a TCK, and applies the TCK to the parallel input-serial output shift register and the integrated circuit, respectively; A boundary scan structure capable of parallel input processing including a TCK generation control unit which receives a TCK from the TCK generation circuit and counts the number of TDIs to be applied to the integrated circuit and outputs a TCK generation signal.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of a boundary scan structure capable of parallel input processing according to the present invention. In addition to the same integrated circuit 1 and processor 2 as in the related art, a plurality of parallel shift registers R1, R2, R3, and R4 and a clock are shown. The generation unit 10, the selection circuit 20, the TCK generation control unit 30, and the TCK generation circuit 40 are further configured. In such a configuration, the clock generator 10 and the selection circuit 20 input and store the TDIs to be applied to the integrated circuit 1 in parallel to the parallel input-serial output shift registers R1, R2, R3, and R4. The TCK generation control unit 30 and the TCK generation circuit 40 are for serially applying the TDIs stored in the parallel shift registers R1, R2, R3, and R4 to the integrated circuit 1 in series.

Specifically, the address decoder 3 decodes an address signal applied from the processor 2 via the address bus AB to output a loading signal, a parallel input signal, a clear signal, and a set signal, which will be described later. It is composed.

The clock generator 10 receiving the parallel input signal from the address decoder 3 is composed of D flip-flops D11, D12, and D13 as shown in FIG. 3, and these flip-flops D11, D12, and D13. ) Are configured to be selectively reset by the output of the AND gate A11. At this time, the AND gate A11 is configured to combine and output the low level reset signal and the output of the inverting terminal / Q of the flip-flop D13.

Meanwhile, the flip-flop D11 uses the parallel input signal as a clock, and the flip-flops D12 and D13 use the system clock SCK as the clock. Therefore, when the address decoder 3 outputs the high level parallel input signal as shown in FIG. 5, the flip-flop D11 outputs the high level logic DFF11 in synchronization with the parallel input signal and flips it. The flop D12 outputs the high level logic DFF12 at the rising edge of the next system clock SCK. At this time, the flip-flop D13 also outputs the high-level logic DFF13 at the next rising edge of the system clock SCK, but the flip-flop D11, D12, and D13 by the low-level logic of the inverting terminal Q /. ) Are reset.

In the present invention, the above-described output of the flip-flop D12 is referred to as a register selection clock signal.

The selection circuit 20 which receives the clear signal and the parallel input signal from the address decoder 3 and receives the register selection clock signal from the clock generator 10 is a binary counter 21 as shown in FIG. ), A demultiplexer 22 and a plurality of end gates A21, A22, A23, and A24.

Specifically, the counter 21 is cleared by the clear signal of the address decoder 3 inverted by the inverter 121 as shown in FIG. 5 and uses the register selection clock signal as a clock. And outputs the number of input clocks through the terminals DM1-DM4. At this time, the demultiplexer 22 is configured to output the logic of the high level to the AND gates A21-A24 sequentially by combining the outputs of the counter 21. Therefore, while the counter 21 is cleared by the reset signal, the demultiplexer 22 outputs a high level logic through the terminal DM1 as shown, but the register selection clock signal DFF12 outputs the counter ( 21, the counter 21 increases the count value by one, so the demultiplexer 22 outputs a high level logic through the terminal DM2. That is, whenever the clock signal DFF12 is input to the counter 21, the demultiplexer 22 sequentially outputs high-level logic through the terminals DM1 -DM4.

At this time, the AND gates A21-A24 output the outputs of the demultiplexer 22 terminals DM1-DM4 by performing a logical multiplication on the parallel input signals, and the AND gates A21-A24 are clocked for the register selection clock signal DFF12. Whenever it is applied from the generator 10, it outputs the logic of the high level sequentially. In this specification, the high level logic outputted by the AND gates A21-A24 is referred to as a TDI loading signal.

The parallel shift registers R1-R4 for inputting a loading signal from the above-described selection circuit 20 are connected to the processor 2 through a data bus and each time a TDI loading signal is applied to the terminal LD, data is transmitted. It is configured to input TDIs in parallel via the bus. At this time, since the TDI loading signals are sequentially applied to the registers R1-R4 by the AND gates A21-A24, the registers R1-R4 sequentially input the TDIs in parallel.

The registers R1-R4 output TDIs serially synchronized with a clock input through a clock terminal. The TCK generation controller 30 and the TCK generation circuit 40 include the registers R1-R4 and Circuits for providing a TCK to the integrated circuit 1.

Specifically, the TCK generation control unit 30 includes a down counter 31 and an oragate OR31 as shown in FIG. 1.

The down counter 31 loads the data value applied from the processor 2 via the data bus when the counting loading signal is applied from the address decoder 3, and the TCK applied from the TCK generation circuit 40 to the clock terminal. Down counting to output the counted value through terminals O1-On. At this time, the data applied from the address decoder 3 to the counter 31 becomes information on the total number of TDIs to be applied to the integrated circuit 1.

When the down counter 31 is counted down to 0 from the loaded data value, the down counter 31 outputs low level logic to the terminals O1-On, so that the ORA gate OR31 has a counted value of the down counter 31 at 0. At this time, low-level logic is output.

Therefore, when the high level counting loading signal is applied from the processor 2 to the counter 31 as shown in FIG. 7, the total number of TDIs to be applied to the integrated circuit 1 by the ORA gate OR31. The TCK corresponding to the counter 31 counts down and outputs high level logic until it becomes zero. In the present specification, the logic of the high level output from the OR gate OR31 is called a TCK generation signal.

The TCK generation circuit 40 receiving the TCK generation signal from the TCK generation control unit 30 includes two D flip-flops D41 and D42 and two AND gates A41 and A42 as shown in FIG. do.

In this case, the D flip-flop D41 is set by the set signal of the address decoder 3 inverted by the inverter 122, and the D flip-flop D42 is the address decoder 3 inverted by the inverter 121. Is set by the clear signal. The D flip-flops D41 and D42 are configured to be reset by a low level TCK generation signal applied from the TCK generation control unit 30, respectively.

Therefore, as shown in FIG. 7 from the address decoder 3, when the high level count load signal is applied to the down counter 31, the down counter 31 is in a high level state. At this time, when a clear signal is applied from the address decoder 3 to the flip-flop D42, the flip-flop D42 is set and outputs the logic DFF42.

When the set signal is output from the address decoder 3 in this state, the flip-flop D41 is set to output the high level logic DFF41, so the AND gate A41 is synchronized with the high level output of the flip-flop D41. The high level logic is applied to the AND gate A42. At this time, since the system clock SCK is applied to one end of the AND gate A42, the AND gate A42 outputs a signal synchronized with the system clock SCK. In the present invention, the signal of the AND gate A42 is used as the TCK, and the TCK is applied to the clock terminal of the down counter 31 as described above. In addition, the output of the AND gate A41 is used as an interrupt signal of the processor, so that the processor can repeat the above-described process. That is, the processor 2 is configured to recognize the interrupt signal of the low-level logic applied to the terminal INT.

At this time, the TCK generation control unit 30 outputs a low level logic after the down counter 31 down counts the number of TCKs corresponding to the data input from the processor 2 to the D flip-flops D41 and D42. By resetting them, the TCK generation circuit 40 outputs only the number of TCKs corresponding to the data of the processor 2.

In this way, the TCK output from the TCK generation circuit 40 is the clock terminal of the parallel shift registers R1-R4 and the integrated circuit 1 can input the TDIs of the registers R1-R4 in synchronization with TCK. At this time, the TCKs provided to the registers R1-R4 are reduced by the inverter 113 because the TDIs must be applied to the integrated circuit 1 at the rising edge of the TCK.

As can be seen from the above description, the present invention uses the system clock as the TCK after inputting and storing the TDIs in the registers R1-R4 in parallel, and serially converts the TDIs stored in the registers R1-R4 in series. It can be seen that the structure is entered in 1).

In general, since the frequency of the system clock is very high, it can be seen that the boundary scanning speed is faster than the conventional method in which the processor generates TCK in synchronization with the input of the TDI.

As described above, the present invention has an effect of improving boundary scanning speed by inputting and storing TDI in parallel and applying the system clock to the integrated circuit using the TCK.

Claims (5)

A TDI input device for boundary scanning of an integrated circuit, comprising: at least one parallel input-serial output shift register for inputting TDIs in parallel according to a TDI loading signal and outputting serially input TDIs in synchronization with the TCK; A clock generator which receives the parallel input signal and delays the predetermined time and outputs the same as a register selection clock; A selection circuit for sequentially applying the TDI loading signal to the parallel input-serial output shift registers by combining the counted value of the register selection clock and the parallel input signal; A TCK generation circuit that combines a TCK generation signal and a system clock to form a TCK, and applies the TCK to the parallel input-serial output shift register and the direct rotation, respectively; And a TCK generation control unit configured to receive a TCK from the TCK generation circuit and count the number of TDIs to be applied to an integrated circuit and output a TCK generation signal. 2. The apparatus of claim 1, wherein the clock generator comprises: a first D flip-flop that uses a parallel input signal as a clock; A second D flip-flop that receives the output of the first D flip-flop as an input and outputs a register selection clock signal using a system clock as a clock; A third 3D flip-flop using the system clock as a clock as a register selection clock of the 2D flip-flop; And a first end gate configured to logically multiply the inverted output of the 3D flip-flop and the reset signal to selectively reset the first, 2, and 3D flip-flops. 2. The apparatus of claim 1, wherein the selection circuit comprises: a binary counter cleared by the clear signal and configured to output a binary count of the register selection clock signal; A demultiplexer for combining and outputting the counter outputs; Parallel input processing includes the same number of AND gates as the parallel input-serial output shift register which combines the output of the demultiplexer and the parallel input signal to apply a TDI loading signal to each of the parallel input-serial output shift registers. Possible boundary scan structure. The TCK generation circuit of claim 1, further comprising: a 4D flip-flop selectively set according to a set signal and selectively reset in accordance with the TCK generation signal; A 5D flip flop selectively set according to a clear signal and selectively reset according to the TCK generation signal; A second and gate combining the outputs of the fourth and 5D flip flops; A boundary scan structure capable of parallel input processing including a third end gate that combines the output of the second end gate and a system clock to output as a TCK. The apparatus of claim 1, wherein the TCK generation control unit comprises: a down counter for down counting a number of TCKs corresponding to input data; A boundary scan structure capable of parallel input processing including an orifice for combining the output of the counter and outputting the TCK generation signal until the down counter downcounts the number of TCKs corresponding to the input data.