KR960011634A - Boundary scan structure with parallel input processing - Google Patents

Abstract

The present invention relates to a boundary-scan architecture defined by the Institute of Electrical and Electronics Engineers (IEEE), wherein a clock generator receives a parallel input signal from an address decoder for decoding an address of a processor and delays the predetermined time. Outputs as a register selection clock, and the selection circuit counts the register selection clock and combines the counted value with the parallel input signal to sequentially apply the TDI loading signal to the parallel input-serial output shift registers to perform parallel input-serial. The output shift registers cause the TDIs to be input in parallel according to the loading signal for the TDI. The TCK generation control unit receives the TCK from the TCK generation circuit, counts the number of TDIs to be applied to the integrated circuit, and outputs the TCK generation signal. The TCK generation circuit forms a TCK by combining the TCK generation signal of the address decoder and the system clock. The TCK is applied to the parallel input-serial output shift register and the integrated circuit, respectively, to apply the TDI in which the parallel input-serial output registers are stored to the integrated circuit in synchronization with the TCK. Therefore, the present invention has an effect of improving the input speed of boundary scanning because the system clock is applied to the integrated circuit using the system clock as the TCK after inputting and storing the TDI in parallel.

Description

Boundary scan structure with parallel input processing

As this is a public information case, the full text was not included.

2 is a block diagram of a boundary scan structure capable of parallel input processing according to the present invention.

Claims (5)

A TDI input device for boundary scanning of an integrated circuit, comprising: at least one parallel input-serial output shift register for inputting TDIs in parallel according to a TDI loading signal and outputting serially input TDIs in synchronization with the TCK; A clock generator which receives the parallel input signal and delays the predetermined time and outputs the same as a register selection clock; A selection circuit for sequentially applying the TDI loading signal to the parallel input-serial output shift registers by combining the counted value of the register selection clock and the parallel input signal; A TCK generation circuit that combines a TCK generation signal and a system clock to form a TCK, and applies the TCK to the parallel input-serial output shift register and the integrated circuit, respectively; And a TCK generation control unit configured to receive a TCK from the TCK generation circuit and count the number of TDIs to be applied to an integrated circuit and output a TCK generation signal. 2. The apparatus of claim 1, wherein the clock generator comprises: a first D flip-flop that uses a parallel input signal as a clock; A second D flip-flop that receives the output of the first D flip-flop as an input and outputs a register selection clock signal using a system clock as a clock; A third 3D flip-flop using the system clock as a clock as a register selection clock of the 2D flip-flop; And a first end gate configured to logically multiply the inverted output of the 3D flip-flop and the reset signal to selectively reset the first, 2, and 3D flip-flops. 2. The apparatus of claim 1, wherein the selection circuit comprises: a binary counter cleared by the clear signal and configured to output a binary count of the register selection clock signal; A demultiplexer for combining and outputting the counter outputs; Parallel input processing includes the same number of AND gates as the parallel input-serial output shift register which combines the output of the demultiplexer and the parallel input signal to apply a TDI loading signal to each of the parallel input-serial output shift registers. Possible boundary scan structure. The TCK generation circuit of claim 1, further comprising: a 4D flip-flop selectively set according to a set signal and selectively reset in accordance with the TCK generation signal; A 5D flip flop selectively set according to a clear signal and selectively reset according to the TCK generation signal; A second and gate combining the outputs of the fourth and 5D flip flops; A boundary scan structure capable of parallel input processing including a third end gate that combines the output of the second end gate and a system clock to output as a TCK. The apparatus of claim 1, wherein the TCK generation control unit comprises: a down counter for down counting a number of TCKs corresponding to input data; A boundary scan structure capable of parallel input processing including an orifice for combining the output of the counter and outputting the TCK generation signal until the down counter downcounts the number of TCKs corresponding to the input data. ※ Note: The disclosure is based on the initial application.