KR960014956A - Test data input device with boundary scan structure - Google Patents

Test data input device with boundary scan structure Download PDF

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Publication number
KR960014956A
KR960014956A KR1019940027805A KR19940027805A KR960014956A KR 960014956 A KR960014956 A KR 960014956A KR 1019940027805 A KR1019940027805 A KR 1019940027805A KR 19940027805 A KR19940027805 A KR 19940027805A KR 960014956 A KR960014956 A KR 960014956A
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KR
South Korea
Prior art keywords
test data
tck
signal
output
inverted
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KR1019940027805A
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Korean (ko)
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KR970000820B1 (en
Inventor
곽재봉
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박성규
대우통신 주식회사
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Priority to KR1019940027805A priority Critical patent/KR970000820B1/en
Publication of KR960014956A publication Critical patent/KR960014956A/en
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Publication of KR970000820B1 publication Critical patent/KR970000820B1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318566—Comparators; Diagnosing the device under test

Abstract

본 발명은 IEEE(lnstitute of Electrical and Electronics Engineers)에서 규정한 바운더리 스캔 구조(Boundary-Scan Architecture)에 관한 것으로서, 병직렬 시프트 레지스터(30)에 테스트 데이타를 병렬로 저장시긴 후에 비교회로(40)를 이용하여 TCK 형성회로(20)로 하여금 시스템 클럭(SCR)에 동기되며 테스트 데이타의 갯수에 해당하는 반전 TCK 및 TCK를 형성케 하는 것이다. 그리고, 병직렬 시프트 레지스터(40)는 반전 TCK에 동기되어 저장된 테스트 데이타를 집적회로(50)에 인가하게 하므로써, 집적회로(50)는 TCK의 상승에지에 동기되어 테스트 데이타를 직렬로 입력할 수 있는 것이다.The present invention relates to a boundary-scan architecture defined by the Institute of Electrical and Electronics Engineers (IEEE), wherein the comparison circuit 40 is stored in parallel after storing test data in a parallel shift register 30. This allows the TCK forming circuit 20 to form inverted TCKs and TCKs that are synchronized to the system clock SCR and correspond to the number of test data. Then, the parallel shift register 40 applies the test data stored in synchronization with the inverted TCK to the integrated circuit 50 so that the integrated circuit 50 can input the test data in series in synchronization with the rising edge of the TCK. It is.

따라서, 본 발명은 프로세서가 집적회로에 테스트 데이타를 입력하는데 소요되는 시간을 단축할 수 있게되어 프로세서의 효율성을 높일 수 있다는 효과가 있다.Therefore, the present invention can shorten the time required for the processor to input test data to the integrated circuit, thereby increasing the efficiency of the processor.

Description

바운더리 스캔 구조의 테스트 데이타 입력 장치Test data input device with boundary scan structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 바운더리 스캔 구조의 테스트 데이타입력장치의 블럭도,2 is a block diagram of a test data input apparatus having a boundary scan structure according to the present invention;

제3도는 본 발명에 따른 바운더리 스캔 구조의 테스트 데이타입력장치의 주요 부분 파형도.3 is a main partial waveform diagram of a test data input device having a boundary scan structure according to the present invention.

Claims (3)

바운더리 스캔 구조에 테스트 데이타를 입력하는 장치에 있어서, 시스템 클럭에 동기되어 로딩신호를 선택적으로 출력하며 데이타 버스를 통하여 병렬로 테스트 데이타를 출력하고, 출력되는 테스트 데이타의 갯수에 대한 정보를 공급하는 제어회로와; 상기 제어회로로부터 로딩신호가 인가되면 상기 데이타 버스를 통하여 테스트 데이타를 병렬로 입력하고, 반전 TCK에 동기되어 입력된 테스트 데이타를 직렬로 바운더리 스캔구조에 인가하는 병직렬 시프트 레지스터와; 상기 시스템 클럭 및 상기 로딩신호를 조합하여 TCK 및 반전 TCK를 출력하며, 리세트 신호의 인가시에 리세트되는 TCK 형성회로와; 상기 TCK 형성의로의 반전 TCK를 계수하여 계수된 값이 상기 데이타 버스를 통하여 인가되는 테스트 데이타의 갯수와 동일할 때에 리세트신호를 출력하는 비교회로를 구비하는 바운더리 스캔 구조의 테스트 데이타 입력 회로.A device for inputting test data into a boundary scan structure, wherein the control signal outputs a loading signal selectively in synchronization with a system clock, outputs test data in parallel through a data bus, and supplies information about the number of test data output. Circuits; A parallel shift register for inputting test data in parallel through the data bus when a loading signal is applied from the control circuit, and for applying test data input in synchronization with an inverted TCK to a boundary scan structure in series; A TCK forming circuit which combines the system clock and the loading signal to output a TCK and an inverted TCK and is reset upon application of a reset signal; And a comparison circuit for outputting a reset signal when the value calculated by counting the inversion TCK into the TCK formation is equal to the number of test data applied through the data bus. 제1항에 있어서, 상기 TCK 형성회로는, 상기 시스템 클릭과 로딩신호를 조합하는 제1앤드게이트와; 전원에 입력단자가 연결되어 있으며, 상기 제1앤드게이트의 출력을 클럭으로 사용하고 상기 리세트신호에 의하여 선택적으로 리세트되는 D 플립플롭과; 상기 D 플립플롭의 출력과 상기 시스템 클럭을 조합하여 상기 반전 TCK를 출력하는 제2앤드게이트와; 상기 시스템 클럭이 반전된 신호와 상기 D 플립플롭의 출력을 조합하여 상기 TCK를 출력하는 제3앤드게이트를 구비하는 바운더리 스캔 구조의 테스트 데이타 입력 장치.The circuit of claim 1, wherein the TCK forming circuit comprises: a first end gate combining the system click and the loading signal; A D flip-flop connected to an input terminal of a power supply and using an output of the first and gate as a clock and selectively reset by the reset signal; A second and gate outputting the inverted TCK by combining the output of the D flip-flop and the system clock; And a third end gate configured to output the TCK by combining the inverted signal of the system clock and the output of the D flip-flop. 제3항에 있어서, 상기 비교회로는, 상기 로딩신호에 따라 상기 데이타 버스를 통하여 인가되는 테스트 데이타 갯수에 대한 정보를 입력하는 버퍼와; 상기 TCK를 계수하는 계수기와; 상기 버퍼를 통하여 인가되는 상기 테스트 데이타의 갯수와 상기 계수기의 계수값이 동일할 때에 리세트신호를 출력하는 비교기를 구비하는 바운더리 스캔 구조의 테스트 데이타 입력 장치.4. The apparatus of claim 3, wherein the comparison circuit comprises: a buffer for inputting information on the number of test data applied through the data bus according to the loading signal; A counter for counting the TCK; And a comparator for outputting a reset signal when the number of the test data applied through the buffer and the count value of the counter are the same. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940027805A 1994-10-28 1994-10-28 Test data input circuit of boundary-scan architecture KR970000820B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940027805A KR970000820B1 (en) 1994-10-28 1994-10-28 Test data input circuit of boundary-scan architecture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940027805A KR970000820B1 (en) 1994-10-28 1994-10-28 Test data input circuit of boundary-scan architecture

Publications (2)

Publication Number Publication Date
KR960014956A true KR960014956A (en) 1996-05-22
KR970000820B1 KR970000820B1 (en) 1997-01-20

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JP3401523B2 (en) * 1999-01-11 2003-04-28 デュアキシズ株式会社 Communication element and communication device using the same

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