KR0121940B1 - Circuit for outputting two-output data of the boundary-scan - Google Patents

Abstract

a boundary scan circuit outputting a first, a second boundary scan data to a first, a second output line; a control part controlling all the operation of a system by accessing the program in response to a clock and having an address bus, a control bus and a data bus; an input/output address decoder outputting a first, a second and a third address signal for the data input/output of the boundary scan; a first logic part generating an interval signal and a shifting clock; a shift register part shifting and outputting the first, the second boundary scan data according to the shifting clock; a second logic part generating a selection signal to select shift register in the shift register part by latching and counting a third address signal; and an output part outputting by latching the shifted data of the shift register part to a first and a second output terminal in response to the third address signal.

Description

2 output data output circuit of boundary scan

1 is a boundary scan two output data output circuit according to the present invention.

2 is a timing diagram showing an operation relationship of a main part according to FIG.

The present invention relates to boundary scan, an internal state inspection standard of a large scale integrated circuit. In particular, a fast data shifting function and a state of monitoring a selected 2 pin state at the same time with the input / output of the boundary scan circuit having two lines are provided. It relates to a two-output data output circuit of boundary scan.

In general, in a circuit using a VLSI or a microprocessor, in order to monitor an input / output pin of a large-scale integrated circuit (VLSI), change data of a state appearing on the input / output pin is stored in a boundary scan register.

Conventionally, when performing the sample operation of the boundary scan function, dummy data is input to the data input terminal (TDI) for the boundary scan function during such operation, and when the preload function is performed, the data is input for the boundary scan function. The dummy data was output to the data output terminal TDO during this time.

Here, the sample operation and the preload function are operations of reading or loading state data of an external pin or an internal pin without affecting the operation state of the VLSI as some of the basic modes of the boundary scan function. .

Therefore, in the related art, since the data input terminal uses only one TDI and the output terminal uses only one TDO as described above, it is not prescribed to use any one line for both input and output.

In addition, since the processor accesses data for only one pin at the same time, there is a problem in that two or more pins cannot be monitored at the same time.

Accordingly, an object of the present invention is to provide a circuit having a two-output data output circuit function of boundary scan that can improve the conventional input / output efficiency or solve the problem.

It is another object of the present invention to provide two outputs of boundary scan in a circuit using VLSI, which can serve as a quick data shifting function with two lines of input / output and a function of simultaneously monitoring the state of the selected two pins. To provide a data output circuit.

According to the present invention for achieving the above object, the two-output data output circuit of the boundary scan, the boundary scan circuit for outputting the first and second boundary scan data to the first and second output lines; A controller which controls the overall operation of the system by accessing a preset program in response to the clock and has an address bus, a control bus, and a data bus; An input / output which is connected to the control unit and outputs first, second and third address signals for data input / output of a boundary scan by receiving and decoding address signals, read signals and data through the address bus, control bus and data bus. An address decoder; A first logic unit which inputs the first and second address signals of the input / output address decoder to generate a period signal and a shifting clock for determining the number of data to be output; A shift shifting unit comprising a plurality of shift registers operated in accordance with a selection signal applied to each other, and shifting the first and second boundary scan data according to the spinning clock applied from the first logic unit. A register section; A second logic part connected to the first logic part and generating the selection signal for latching and counting the third address signal to select a shift register in the shift register part; And an output unit connected to an end shift register of the shift register unit, respectively, for latching the shifted data of the shift register unit to first and second output terminals in response to the third address signal.

In addition, an oscillator for supplying a clock of the control unit and a clock of each unit, and a reset logic for providing a reset signal are additionally configured.

According to the above configuration, two lines of input / output data can be efficiently utilized outside of a large scale integrated circuit.

Hereinafter, a two-output data output circuit of a boundary scan according to a preferred embodiment of the present invention will be described in detail with reference to the drawings.

In the following description, detailed items for the type of such circuit structure and the like are described to help a more thorough understanding of the present invention.

However, it will be apparent to those skilled in the art that the present invention can be implemented by the above-described technical spirit of the present invention without such details.

In addition, the characteristics and functions of electronic basic devices well known in the art, such as end gates and flip-flops, are not described in detail in order not to obscure the present invention.

First, referring to FIG. 1 showing a block of a circuit according to the present invention, a boundary scan circuit 5, a control unit 2, an input / output address decoder 6, a first logic unit 7, a shift register unit 10, a second logic unit 8, and The output section 11 constitutes two output data output circuits of boundary scan.

In addition, the oscillator 4 for supplying the clock of the controller 2 and the clock of each unit, and the reset logic 3 for providing the reset signal are additionally configured and may be located outside the circuit.

In FIG. 1, the boundary scan integrated circuit 5 includes: first and second boundary scan data D0, D2, and D4 into first and second output lines TDO1 and TDO2; Outputs D1, D3, D5.

For example, Control Unit 2, which can use Intel's 80816 series, controls the overall operation of the system by accessing a pre-set program in response to the clock CLK, and uses the address bus ADD, control bus, CON, / RD, and data bus I / O. Has

The input / output address decoder 6 connected to the controller 2 outputs first, second, and third terminals for data input and output of boundary scan by receiving and decoding address signals, read signals, and data through the address bus, the control bus, and the data bus. It is output as O1,2,3.

The first logic unit 7 inputs the first and second address signals of the input / output address decoder 6 to generate an interval signal and a shifting clock for determining the number of data to be output.

Here, the first logic unit 7 inputs the first address signal to the clock terminal, and outputs a counting clock in response to the shifting clock and eight de-type flip-flops 71 connected to the data bus and the input terminal of the controller 2. A binary counter 72 to compare the output data of the flip-flop 71 and the output data of the binary counter 72 to output a comparison signal, and an AND gate to AND gate the comparison signal and the reset signal. 75, a de-flip-flop 76 having a reset terminal connected to an output of the AND gate 75, a preset terminal connected to an inverted signal of the second address signal, and an input terminal and a clock fixed to a high state, and the second address signal. An AND gate for inverting the AND, and an AND gate for outputting the output of the flip-flop 76 and the clock of the oscillator 4 as the shifting clock. Consists of 77.

The shift register section 10 includes: 8-bit shift registers SR1, 2, 3, 4, 5N of a plurality of serial input parallel outputs operated according to the selection signals S1, 2, N applied; SR11, SR22, SR33, SR44 and SRNN are composed of two groups, and the first and second boundary scan data are shifted and output in accordance with the shifting clock CLK applied from the first logic unit 7.

The second logic part 8 connected to the first logic part 7 latches and counts the third address signal to select the selection signals S0, 1, 2,... To select the shift register in the shift register part. Generates N.

Here, the second logic unit 8 includes three serially connected flip-flops 81, 82 and 83, an AND gate 84, 85, a binary counter 86, and a selector 87 for outputting the selection signal.

The output unit 11 is connected to the end shift register of the shift register unit 10, respectively, and latches the shifted data of the shift register unit 10 to the first and second output terminals O1 and 2 in response to the third address signal. do.

In addition, the oscillator 4 is responsible for supplying the clock of the control unit 2 and the clock of each unit.

The reset logic 3 provides the reset signal RES. The above-described configuration is designed to efficiently utilize two lines of input / output data outside of a large scale integrated circuit.

The output data provided from the first and second output terminals OUT1 and 2 of FIG. 1 are alternately outputted by the odd-numbered input TDI1 and the ordinal number input TDI2 for the data input signal TDI, which are shown as timings in FIG.

In addition, the connection between the first and second buffers in the shift register section 10 and the output section 11 should be connected to the same input and output numbers.

2 is a timing diagram showing an operation relationship of each part according to FIG.

Referring to FIG. 2, when the clock for the boundary scan function becomes as shown by reference numeral 20 shown in FIG. 2, the input / output address decoder 6 receives the first, second, and third address signals 21, 22, and 23, respectively. Will print something like

Here, the first address signal is a signal specifying the number of data to be read at the input, the second address signal is a signal indicating the operation enable signal to actually read the data, the third address signal is the control unit 2 is a command signal for inputting the data read out from the shift register section 10 into the control section.

In FIG. 2, reference numeral 24 denotes an output signal of the comparator 73 of FIG. 1, reference numeral 25 denotes an output signal of the de-flip flop 76, and reference numeral 26 denotes an output signal of the AND gate 77.

Reference numeral 27 denotes an output of the de-flip flop 81, and reference numeral 28 denotes an output signal of the de- flip-flop 82.

Reference numeral 29 is an inverted signal of the inverter 91 as an out enable signal.

Reference numerals 30 and 31 denote first and second selection signals output from the selection section 87 in the second logic section 8.

In FIG. 2, the first address signal is generated in the section T1, the second address signal is provided in the section T2, and the data of the shift register unit 10 are alternately read in the sections T3 and T4 and output to the output terminal. will be.

Accordingly, one serial boundary scan and two serial boundary scans can be selectively performed, and a function for simultaneously monitoring the state of the selected two output lines is provided. To shrink.

Therefore, in order to read the data output signal for the boundary scan function, the control unit can read and process two lines of output through the shift register unit only by specifying the mode value through the output port, thereby increasing the overall efficiency of the system. will be.

According to the present invention as described above, by efficiently utilizing two lines of input and output data outside the large-scale integrated circuit, it is possible to perform a quick data shifting function in the state of two lines, and simultaneously to select the state of the selected two lines It has the advantage of being able to monitor.

Claims (6)

A two-output data output circuit having a boundary scan function, comprising: a boundary scan circuit for outputting first and second boundary scan data to first and second output lines; A controller which controls the overall operation of the system by accessing a preset program in response to the clock and has an address bus, a control bus, and a data bus; An input / output which is connected to the control unit and outputs first, second and third address signals for data input / output of a boundary scan by receiving and decoding address signals, read signals and data through the address bus, control bus and data bus. An address decoder; A first logic unit which inputs the first and second address signals of the input / output address decoder to generate a period signal and a shifting clock for determining the number of data to be output; A shift shifting unit comprising a plurality of shift registers operated in accordance with a selection signal applied to each other, and shifting the first and second boundary scan data according to the shifting clock applied from the first logic unit. A register section; A second logic part connected to the first logic part and generating the selection signal for latching and counting the third address signal to select a shift register in the shift register part; A boundary scan unit connected to an end shift register of the shift register unit, the output unit configured to latch output shifted data of the shift register unit to first and second output terminals in response to the third address signal; 2 output data output circuit. 2. The two-output data output circuit of boundary scan according to claim 1, wherein the first and second boundary scan data are provided through a data output line of a large scale integrated circuit having a boundary scan function. 2. The two-output data output circuit of boundary scan according to claim 1, wherein the shift register is an 8-bit shift register having a function of serial input parallel output. 2. The first logic unit of claim 1, wherein the first logic unit inputs the first address signal to a clock terminal and outputs a counting clock in response to the shifting clock and eight de-type flip-flops connected to a data bus and an input terminal of the controller. A binary counter for comparing the output data of the flip-flop and the output data of the binary counter and outputting a comparison signal, an AND gate for AND-gating the comparison signal and the reset signal, and A flip-flop having a reset terminal connected to an output of the gate, a preset terminal connected to an inverted signal of the second address signal, and an input terminal and a clock fixed at a high state, and an inverter for inverting the second address signal; And an AND gate outputting and outputting the de-flop flop and the clock as the shifting clock. Boundary scan output circuit of the second output data. 5. The two-output data output of the boundary scan of claim 4, wherein the second logic unit comprises three series-connected de-flips, an end gate, a binary counter, and a selection unit for outputting the selection signal. Circuit. 2. The two-output data output circuit of boundary scan according to claim 1, wherein the circuit further comprises an oscillator and a reset logic.