JPH1041789A - Master/slave d-type flip-flop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of a mater/slave D-type flip-flop circuit integrated into an LSI with a high speed operation or the like, and to prevent the operation frequency of the LSI or the like from being deteriorated. SOLUTION: In a master/slave D-type flip-flop circuit integrated in an LSI with a high speed operation or the like, a data comparator circuit 8 is provided at the input side of the clock circuit of the master/slave D-type flip-flop circuit, and a gate for interrupting a system clock inputted to the pertinent master/slave D-type flip-flop circuit when held data are fetched from a master latch circuit 5a and a slave latch circuit 6a, and they match is provided at a clock circuit 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a large-scale logic integrated circuit (hereinafter, a large-scale logic integrated circuit is called an LSI or the like).
Power consumption of the master-slave D-type flip-flop circuit incorporated in
The present invention relates to a master-slave / D-type flip-flop circuit configured so that its operating frequency does not decrease at I or the like.

[0002]

2. Description of the Related Art In recent years, the circuit scale of semiconductor integrated circuits has been increasing with the miniaturization of the manufacturing process. Even if there is no change in the input signal of the master-slave / D-type flip-flop circuit incorporated in an LSI or the like, a system clock is always supplied to the clock circuit, and a measure for reducing power consumption by operating the clock circuit is proposed. Proposed.

Further, in order to facilitate the testing of the internal circuit incorporated in the LSI or the like, in order to improve the controllability and observability of the internal circuit such as the LSI or the like, all the terminals in the circuit are connected from the external terminal of the LSI or the like. A method of adopting a circuit configuration capable of directly accessing a storage device has been proposed.

As a measure for reducing the power consumption of a conventional master-slave D-type flip-flop circuit, for example, Japanese Patent Laid-Open No.
FIG. 8 is a circuit diagram shown in the above document. The above-mentioned master-slave D-type flip-flop circuit outputs the latching signal Vb
Is at a high level (hereinafter referred to as H).
Latch circuit 11 for sampling and latching
And a slave latch circuit 12 that samples and latches an output signal of the master latch circuit 11 when the latching signal Vb is at a low level (hereinafter referred to as L), and an inverter that inverts the latching signal Vb and supplies it to the slave latch circuit. A gate circuit 14 that performs an exclusive OR operation of the output signal Q of the slave latch circuit and the input signal D of the master latch circuit, and performs a NAND operation on the output signal Va of the gate circuit 14 and the clock signal T. A gate circuit 15 that outputs a latching signal Vb.

The operation of FIG. 8 will be described. Since the input signal D and the output signal Q are at the same level unless the level of the input signal D changes, the exclusive OR signal Va is L, the latching signal Vb is fixed at H, and the clock signal is invalid. Become. When the input signal D changes, the exclusive OR signal Va becomes H, and the gate circuit 15 enters a state in which the clock signal T passes. At this time, since the latching signal Vb is H, the master latch circuit 11 samples and latches the input signal D.

Next, when the clock signal T changes from L to H, the latching signal Vb changes to L, the slave latch circuit 12 samples and latches the output signal of the master latch circuit 11, and outputs the output signal of the slave latch circuit 11. Q changes in level. Since the level of the output signal Q changes, the level of the output signal Q becomes the same as the level of the input signal D. Therefore, the exclusive OR signal Va becomes L, the output of the gate circuit 15, that is, the latching signal Vb becomes H, and the clock signal again becomes Is invalid.

As described above, even if the level of the clock signal T constantly changes in a predetermined cycle, the level of the latching signal Vb does not change unless the level of the input signal D changes, so that the latch circuit Vb is consumed by the clock circuit including the gate and the inverter. Power is reduced.

[0008] However, it is incorporated in an LSI or the like.
Since the master-slave / D-type flip-flop circuit which has been reduced in power consumption obtains two inputs of the exclusive OR circuit constituting the gate circuit 14 from its external input / output terminals, it is static. There has been a problem that the operating frequency of an LSI or the like that operates at a high speed decreases due to an increase in the capacitance.

Next, a brief description will be given of a conventionally known scanning method for improving the controllability and observability of a logic circuit in order to facilitate testing of an internal circuit incorporated in an LSI or the like mentioned above. I do.

In order to make a circuit configuration in which all the storage devices in the circuit can be directly accessed from the external terminals of the LSI, all the storage devices (flip-flops) in the circuit are connected in series to form a shift register. Then, a normal operation of the shift register is confirmed by applying a test pattern from the scan-in terminal and observing the test result at the scan-out terminal via all flip-flops.

Further, a test pattern is applied to an internal circuit which can be directly set from an external terminal, a test result of the internal circuit is taken into a shift register, and the result is drawn out to a scan-out terminal using the shift register and the result is observed.

A test pattern is input to the internal circuits that can be set through the flip-flops by using a shift register from a scan-in terminal to the flip-flops, and a test result of the internal circuit for the test pattern is input to another shift register. The combination circuit surrounded by the storage devices can be independently taken out and partially tested by using the shift register to pull out to the scan-out terminal and observing the result. For internal circuits that can be set from the above flip-flops and that have an external output terminal directly, a test pattern is input to those flip-flops from the scan-in terminal using a shift register, and the internal circuit is tested for the test pattern. The results can be observed directly.

In order to construct such an easily testable LSI, a data input side of a master-slave / D-type flip-flop circuit incorporated in the LSI or the like is used at the time of system operation of the logic integrated circuit and at the time of testing the internal circuit of the logic integrated circuit. An input selection circuit for selecting a data input path is provided so that a master-slave / D-type flip-flop circuit can input data during an original system operation of the LSI and test pattern data for testing an internal circuit of the LSI or the like. Has become.

However, the master-slave / D-type flip-flop circuit incorporated in an LSI or the like and configured to facilitate the test of the internal circuit as described above has not taken a measure for reducing power consumption, and therefore has a high speed operation. LSI
In such a case, there is a problem that power consumption of a magnitude that cannot be ignored is generated.

[0015]

SUMMARY OF THE INVENTION As described above, LSI
A conventional master-slave D-type flip-flop circuit which is built in and configured to reduce power consumption,
In the case of a high-speed operation LSI, there is a problem that the operation frequency is reduced. A conventional master-slave / D-type flip-flop circuit incorporated in an LSI or the like and configured to facilitate the test of an internal circuit is a high-speed L-type flip-flop circuit.
In the case of SI, there is a problem that power consumption of a magnitude that cannot be ignored is generated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and is incorporated in a high-speed operation LSI or the like to reduce power consumption and to prevent the operating frequency from being lowered. It is an object of the present invention to obtain a flip-flop circuit. It is another object of the present invention to provide a master-slave D-type flip-flop circuit which is incorporated in a high-speed operation LSI or the like to facilitate testing of internal circuits and reduces power consumption.

[0017]

To achieve the above object, a master-slave D-type flip-flop circuit according to the present invention is a master-slave-D-type flip-flop circuit incorporated in an LSI or the like. A data comparing means is provided on the input side of the clock circuit of the flip-flop circuit, and the held data is taken out from each of the master latch circuit and the slave latch circuit. A gate for shutting off a system clock is provided in the clock circuit.

The master-slave D-type flip-flop circuit according to the present invention is a master-slave D-type flip-flop circuit incorporated in an LSI or the like. Input selection means for selecting a data input path at the time of system operation and at the time of internal circuit test; and data for comparing the output data of the input selection means with the output data of the master-slave D-type flip-flop circuit on the input side of the clock circuit. Comparing means, and a gate for cutting off a system clock input to the master-slave / D-type flip-flop circuit when the two data coincide with each other is provided in the clock circuit.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 shows a master-slave D of the present invention.
FIG. 2 is a circuit diagram showing a first embodiment of a flip-flop circuit; In the figure, 1, 2, 3, and 4 are P-channel MOs.
CMOS consisting of SFET and N-channel MOSFET
When the gate signals T0 = L and T1 = H, the gates 1 and 4 are ON and the gates 2 and 3 are OFF. Conversely, when the gate signals T0 = H and T1 = L, the gates 1,
4 is OFF, and gates 2 and 3 are ON. 5a is a master latch circuit, 6a is a slave latch circuit, 7 is a clock circuit, and 8 is a data comparison circuit.

Here, two inputs of the data comparison circuit 8 composed of exclusive NOR provided on the input side of the clock circuit are:
The data held in the master latch circuit and the slave latch circuit are taken out from each inside. In FIG. 1,
An example is shown in which each held data is extracted from a point A on the output of the master latch circuit and a point B on the output side of the CMOS gate 2 as the input of the slave latch circuit. The point at which the held data is taken out from each of the master latch circuit and the slave latch circuit is not limited to this. Two inverters connected in series between the output side of the input CMOS gate 1 of the master latch circuit and the slave latch circuit in FIG. Alternatively, each held data may be taken out from between and compared.

The operation of FIG. 1 will be described with reference to the timing chart of FIG. First, in the master-slave D-type flip-flop circuit, the gate signal is T0 =
When L and T1 = H, the gates 1 and 4 are ON, and the gates 2 and
Since 3 is OFF, the input data D is taken into the master latch circuit 5a, and the slave latch circuit 6a holds the data in the initial state. Here, the point A is H, and the point B is H as an initial state.

Next, when the input data D changes from L to H and the gate signals become T0 = H and T1 = L, the gates 1 and 4 are turned off and the gates 2 and 3 are turned on. The data held in the latch circuit 5a propagates to the slave latch circuit 6a.

Further, the gate signals are T0 = L, T1 = H
Gates 1 and 4 are ON, and gates 2 and 3 are O
Since it becomes an FF, new input data D is taken into the master latch circuit 5a (in FIG. 2, the input data D has not changed, but the data held in the master latch circuit 5a does not change), and is transmitted to the slave latch circuit 6a. Data is retained.

Thereafter, as long as the input data D does not change, the system clock is cut off by the clock circuit and the gate signals T0 and T1 are fixed by the output of the data comparison circuit 8 comprising an exclusive NOR provided on the input side of the clock circuit. Have been. As long as the input data D does not change, the clock circuit does not operate with the system clock, so that the power consumed by the clock circuit is reduced.

The following will explain that the master-slave / D-type flip-flop circuit configured as described above does not lower the operating frequency of the LSI when incorporated in a high-speed LSI or the like.

For the sake of simplicity, the description will be made using a D-type flip-flop (hereinafter, referred to as a D-FF) shown in FIG. 3 instead of the master-slave D-type flip-flop circuit.

FIG. 4 is a timing chart for explaining the setup time of the D-FF. D-FF
Is a circuit configuration that takes in D input data when the clock T rises, that is, the rising edge of the clock T, like the master-slave / D-type flip-flop circuit, so that some time before the rising edge of the clock T , D input data must not be changed. In order to take in the data b, if the setup time does not satisfy a certain prescribed value, it cannot be guaranteed whether to take in the value of b or the value of a.
The minimum setup time of the FF is specified, and the operation of the circuit is guaranteed.

Next, the relationship between the setup time of the D-FF and the operating frequency of the LSI incorporating the D-FF will be described with reference to FIGS. FIG. 5 is a circuit diagram showing a part of a synchronous circuit incorporated in an LSI. FIG. 6 is a timing chart for explaining the relationship between the setup time of the D-FF and the operating frequency of the LSI in the synchronous circuit of FIG. The same clock signal of the synchronous circuit shown in FIG. 5 is supplied to D-FF1 and D-FF2. As shown in FIG. 6, the factor that determines the operating frequency of the LSI is a combination of (the delay time of the D-FF1 from the current rising of the clock of the D-FF1 until the output of the D-FF1 is determined) + (D-FF1 output). The delay time of the combination circuit until the output of the combination circuit is determined) + (the setup time of the D-FF 2 necessary for the operation of the D-FF 2 in the next stage due to the rise of the next clock). That is,
Even if the delay time of the D-FF does not change, if the delay time of the combinational circuit (for example, the number of stages of the combinational circuit can exceed 30) or the setup time of the D-FF becomes large, the operation of the LSI becomes large. This causes the frequency to decrease.

Next, the relationship between the capacitance of the D input terminal of the D-FF and the operating frequency of the LSI incorporating the D-FF will be described. Although the delay time of the D-FF from the rise of the clock of the D-FF to the determination of the D-FF output does not change much, the capacitance shown in FIG. The load capacity of the logic circuit element at the last stage of the combination circuit increases, so that the delay time of the combination circuit increases, or the setup time of the D-FF 2 needs to be increased. Therefore, when viewed as an LSI, a decrease in operating frequency is inevitable. This is not a problem when the operating frequency is low, but LS for high-speed operation
In I, it is a big problem.

As described above, the master-slave / D-type flip-flop circuit is incorporated in a high-speed operation LSI or the like to reduce power consumption and to reduce power consumption.
It is possible to improve the operation frequency such as SI so as not to decrease.

Embodiment 2 Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 7 is a circuit diagram showing Embodiment 2 of a master-slave D-type flip-flop circuit according to the present invention. In the figure, 9 is an LSI which is easy to test
This is an input selection circuit provided on the D data input side of a master-slave / D-type flip-flop circuit incorporated therein to configure the above. Reference numeral 7 denotes a clock circuit, which is the same as in the first embodiment. Reference numeral 8 denotes a data comparison circuit provided on the input side of the clock circuit for reducing power consumption. The output data C of the input selection circuit 9 and the output data Q of the master-slave / D-type flip-flop circuit are used.

The operation of FIG. 7 will be described. In order to construct an LSI that can be easily tested, an outline of a known scan method in which an external terminal of the LSI directly accesses all the storage devices in the circuit has been described above.

In order to form a shift register by connecting all the storage devices (flip-flops) incorporated in the LSI in series, it is provided on the D data input side of a master-slave D-type flip-flop circuit incorporated therein. In the input selection circuit 9, as shown in FIG. 7, when the input selection signal applied to the SM terminal is set to L, a data input path during system operation of the LSI is provided on the D data input side of the master-slave / D-type flip-flop circuit. Connected
Data during the original system operation of the LSI is input to the master-slave D-type flip-flop circuit.

On the other hand, when the input selection signal applied to the SM terminal is set to H, the data input path at the time of the internal circuit test of the LSI is connected to the D data input side of the master-slave D-type flip-flop circuit. Test pattern data for circuit testing is input to the master-slave D-type flip-flop circuit.

In the data comparison circuit 8 provided on the input side of the clock circuit, the two inputs of the exclusive NOR circuit are connected to the output data C of the input selection means and the output of the master-slave / D-type flip-flop circuit. Data Q is fetched, and when the two data match, a gate for cutting off a system clock input to the master-slave D-type flip-flop circuit is provided in the clock circuit, thereby reducing power consumption of a high-speed operation LSI or the like. be able to.

As described above, by configuring the master-slave / D-type flip-flop circuit, it can be incorporated into a high-speed LSI or the like, thereby facilitating the test of the internal circuit and consuming no more than negligible power. The power can be reduced.

In the first and second embodiments, a large-scale logic integrated circuit is called an LSI or the like, and a master-slave D-type flip-flop circuit incorporated therein has been described. However, the present invention is limited to a so-called LSI. However, in the case of VLSI and ULSI, a greater effect can be obtained especially for a high-speed operation.

[0038]

As described above, according to the first aspect of the present invention, the data comparison means is provided on the input side of the clock circuit of the master-slave D-type flip-flop circuit, and the internal circuits of the master latch circuit and the slave latch circuit are respectively provided. When the held data is extracted from the data and the two data coincide with each other, the clock circuit is provided with a gate for shutting off the system clock input to the master-slave / D-type flip-flop circuit. It is possible to obtain a master-slave D-type flip-flop circuit that reduces power and does not lower the operating frequency of an LSI or the like.

According to the second aspect of the present invention, an input selecting means for selecting a data input path on the data input side of the master-slave / D-type flip-flop circuit at the time of system operation of the logic integrated circuit and at the time of internal circuit test. And data comparison means for comparing the output data of the input selection means with the output data of the master-slave D-type flip-flop circuit on the input side of the clock circuit. By providing a gate for blocking the system clock input to the D-type flip-flop circuit in the clock circuit, a high-speed L
A master-slave D-type flip-flop circuit which is incorporated in an SI or the like and has a configuration which facilitates testing of an internal circuit and which has a power consumption which cannot be ignored can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing Embodiment 1 of a master-slave D-type flip-flop according to the present invention.

FIG. 2 is a timing chart illustrating the operation of FIG.

FIG. 3 is a diagram showing symbols of a D-type flip-flop circuit used in place of a master-slave D-type flip-flop circuit to simplify the description.

FIG. 4 is a timing chart for explaining a setup time of a D-type flip-flop circuit.

FIG. 5 is a circuit diagram showing a part of a synchronization circuit incorporated in an LSI.

6 is a timing chart illustrating a relationship between a setup time of a D-type flip-flop circuit of the synchronous circuit of FIG. 5 and an operating frequency of an LSI.

FIG. 7 is a circuit diagram showing a master-slave D-type flip-flop according to a second embodiment of the present invention;

FIG. 8 is a circuit diagram showing a conventional master-slave D-type flip-flop.

[Explanation of symbols]

1-4 gates (CMOS gates), 5a, 5b master latch circuits, 6a, 6b slave latch circuits, 7
Clock circuit, 8 data comparison circuit, 9 input selection circuit.

Claims (2)

[Claims] In a master-slave D-type flip-flop circuit incorporated in a large-scale logic integrated circuit,
A data comparing means is provided on the input side of the clock circuit of the master-slave / D-type flip-flop circuit, and the held data is taken out from the inside of each of the master-latch circuit and the slave-latch circuit. A master-slave D-type flip-flop circuit, wherein a gate for blocking a system clock input to the flip-flop circuit is provided in the clock circuit. 2. A master-slave D-type flip-flop circuit incorporated in a large-scale logic integrated circuit,
A data input side of the master-slave D-type flip-flop circuit, input selection means for selecting a data input path during system operation of the logic integrated circuit and an internal circuit test, and output data of the input selection means on the input side of the clock circuit And data comparing means for comparing output data of the master-slave D-type flip-flop circuit, and a gate for cutting off a system clock input to the master-slave-D-type flip-flop circuit when the two data match. A master-slave D-type flip-flop circuit provided in the clock circuit.