JP2000180510A - Semiconductor integrated circuit and method for designing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce useless power consumption due to the signal change of wiring at the time of a normal operation in a semiconductor integrated circuit in which a scan chain is constituted. SOLUTION: Switching circuits 21 and 25 are provided in wiring 15 and 16 which are included in signal paths in a shift mode and which are not included in signal paths at the time of a normal operation among the output signal lines of scan flip flops 11 and 12 constituting a scan chain 10. When a scan enable signal SE is '1', NMOS gates 22 and 26 are turned into a conductive state, and the output signals of the scan flip flops 11 and 12 are propagated to each wiring 15a and 16a. On the other hand, when the scan enable signal SE is '0', the NMOS gates 22 and 26 are turned into a non-conductive state, and the potentials of the wiring 15a and 16a are turned into ground potentials by pull-down elements 23 and 27. Thus, while the scan enable signal SE is '0', any signal change can not be generated in the wiring 15a and 16a, and any power consumption due to charging and discharging can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology related to a semiconductor integrated circuit having a scan chain for performing a scan test so that a failure test can be performed efficiently.

[0002]

2. Description of the Related Art FIG. 7 is a diagram showing an example of a conventional semiconductor integrated circuit having a scan chain. The semiconductor integrated circuit of FIG. 7 includes a combinational circuit 2 and scan flip-flops 11 and 12. The scan flip-flops 11 and 12 have the same configuration. When "0" is input to the scan enable input terminal SE, the data of the normal data input terminal D is synchronized with the clock signal input to the clock input terminal CK. On the other hand, when "1" is input to the scan enable input terminal SE, the data at the scan data input terminal SI is input in synchronization with the clock signal input to the clock input terminal CK.

[0003] The semiconductor integrated circuit of FIG. 7 operates as follows. During normal operation, scan flip-flops 11, 1
2 receives a signal from the combinational circuit 2 from the normal data input terminal D and outputs a signal to the combinational circuit 2 from the data output terminal Q.

On the other hand, during the test, when the scan enable signal SE is “1” (shift mode), the scan flip-flops 11 and 12 operate as a scan chain, and are connected to the scan flip-flops 11 and 12 from the scan-in terminal 7. A signal value for testing the circuit 2 can be written. Also, the scan enable signal SE
Is "0" (capture mode), the scan flip-flops 11 and 12 receive the test result signal from the combinational circuit 2 and then set the scan enable signal SE to "1" (shift mode), thereby The test result signal of the combinational circuit 2 taken in 11 and 12 can be observed from the scan-out terminal 8.

[0005]

With the miniaturization of semiconductor integrated circuits, the proportion of power consumption due to signal changes in wiring to the power consumption of the entire circuit has increased. For this reason, in a semiconductor integrated circuit, a technique for suppressing power consumption due to a change in wiring signal is becoming more important.

Incidentally, in a conventional semiconductor integrated circuit, as shown in FIG.
The output terminal of the scan flip-flop is directly connected to the scan-in terminal of the next-stage scan flip-flop.

However, in the semiconductor integrated circuit of FIG. 7, during normal operation, the output signals of scan flip-flops 11 and 12 applied to combinational circuit 2 are transmitted through wirings 15 and 16 not included in the signal path during normal operation. Also cause a signal change. Thereby, the wiring 1
Unnecessary charge / discharge occurs due to a signal change at 5 and 16, resulting in unnecessary power consumption.

In view of the above problems, it is an object of the present invention to suppress wasteful power consumption due to a change in wiring signals during a normal operation as a semiconductor integrated circuit having a scan chain.

[0009]

Means for Solving the Problems In order to solve the above-mentioned problems, a solution taken by the invention of claim 1 is a semiconductor integrated circuit, comprising: a storage element forming a scan chain;
Of the output signal lines of the storage element, the output signal line is provided on a wiring included in the signal path in the shift mode and not included in the signal path in the normal operation, and according to a control signal indicating whether or not the shift mode is set. A switching circuit for switching an output, wherein the switching circuit, when the control signal indicates a shift mode, conducts an output wiring and an output wiring to output an input signal as it is, When the mode is not indicated, a fixed value is output irrespective of the input signal so that power consumption in the output side wiring is suppressed.

According to the first aspect of the present invention, the switching circuit is provided on a line included in the signal path in the shift mode and not included in the signal path in the normal operation among the output signal lines constituting the scan chain. ing. When the control signal does not indicate the shift mode, the switching circuit outputs a fixed value so that power consumption on the output side wiring is suppressed. Therefore, in a mode other than the shift mode, for example, during normal operation, no signal change occurs on the output side wiring of the switching circuit, and no power consumption occurs. Therefore, useless power consumption due to a change in the signal of the wiring is suppressed.

According to a second aspect of the present invention, the storage element and the switching circuit in the semiconductor integrated circuit of the first aspect are designed as a single circuit component when designing the semiconductor integrated circuit.

According to a third aspect of the present invention, the switching circuit in the semiconductor integrated circuit of the first aspect is arranged near the storage element.

According to a fourth aspect of the present invention, the switching circuit in the semiconductor integrated circuit according to the first aspect of the present invention includes a switch gate for controlling switching between conduction and non-conduction between an input wiring and an output wiring in accordance with the control signal. And a potential fixing element for fixing the potential of the output side wiring to a predetermined value when the switch gate is non-conductive.

According to a fifth aspect of the present invention, the switch gate in the semiconductor integrated circuit of the fourth aspect is constituted by an NMOS gate, a PMOS gate or a CMOS gate.

According to a sixth aspect of the present invention, in the semiconductor integrated circuit of the fourth aspect, the potential fixing element is a pull-down element,
It is assumed that it is constituted by a pull-up element or a hold circuit.

According to a seventh aspect of the present invention, in the method for designing a semiconductor integrated circuit according to the first aspect, the storage element and the switching circuit are designed as a single circuit component.

[0017]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention. In FIG. 1, a semiconductor integrated circuit 1 includes first and second scan flip-flops 11 and 12, and a scan chain 10 including a scan-in terminal 7 and a scan-out terminal 8. First and second storage elements constituting scan chain 10
Have the same configuration, D is a normal data input terminal, SI is a scan data input terminal, CK is a clock input terminal, SE is a scan enable input terminal, and Q is a data output terminal. The clock signal CLK applied to the clock terminal 5 is input to the clock input terminal CK, and the scan enable signal SE applied to the scan enable terminal 6 is input to the scan enable input terminal SE.

The output signal line of the first scan flip-flop 11, that is, the wiring connected to the data output terminal Q, is included in the signal path in the shift mode, and
The first switching circuit 21 is provided on the wiring 15 not included in the signal path during normal operation. First switching circuit 2
Reference numeral 1 denotes an NMOS gate 22 serving as a switch gate for controlling the conduction / non-conduction between the input side wiring and the output side wiring in accordance with a scan enable signal SE as a control signal.
And a pull-down element 23 as a potential fixing element for fixing the potential of the output side wiring to the ground potential when the NMOS gate 22 is non-conductive. That is, the first switching circuit 21 outputs the scan enable signal S
When E is “H”, the input signal is output as it is,
When "L", the ground potential is output as a fixed value.

Similarly, a second switching circuit 25 comprising an NMOS gate 26 and a pull-down element 27 is included in the signal path in the shift mode among the output signal lines of the second scan flip-flop 12, and operates normally. It is provided on the wiring 16 not included in the signal path at the time. Similarly to the first switching circuit 21, the second switching circuit 25 outputs the input signal as it is when the scan enable signal SE is "H", and outputs the ground potential as a fixed value when it is "L". .

That is, in the semiconductor integrated circuit of FIG. 1, when the scan enable signal SE is "1" (shift mode), the wirings 15 and 16 are conductive, and when the scan enable signal SE is "0" (normally). During operation and in the capture mode), the wirings 15 and 16 are cut off.

The semiconductor integrated circuit of FIG. 1 operates as follows. During the test, when the scan enable signal SE is “1” (shift mode), the NMOS gates 22 and
26 becomes conductive, and the signal path of the scan chain 10 from the scan-in terminal 7 to the scan-out terminal 8 operates normally. Therefore, a signal value necessary for testing the combinational circuit 2 can be written to the first and second scan flip-flops 11 and 12 via the scan chain 10.

When the scan enable signal SE is “0” (capture mode), the first and second scan flip-flops 11 and 12 receive the test result signal from the combinational circuit 2. In this case, the scan enable signal SE is then set to “1” (shift mode), so that the test result signal of the combinational circuit 2 captured by the first and second scan flip-flops 11 and 12 is output from the scan-out terminal 8. Can be observed.

On the other hand, during normal operation, the scan enable signal SE is fixed at "0". The first and second scan flip-flops 11 and 12 receive a signal from the combinational circuit 2 from the normal data input terminal D, output a signal from the data output terminal Q, and apply the signal to the combinational circuit 2 respectively. At this time, the NOS gates 22 and 26 are cut off, and the outputs of the first and second switching circuits 21 and 22 are set to the ground potential by the pull-down elements 23 and 27. The outputs of the first and second switching circuits 21 and 22 remain at the ground potential during the normal operation of the semiconductor integrated circuit 1.

As described above, according to the semiconductor integrated circuit of FIG. 1, in the mode other than the shift mode, the wiring 15a on the output side of the first switching circuit 21 of the wiring 15 and the second switching circuit 25 of the wiring 16 The signal does not change on the output side wiring 16a. For this reason, since charge and discharge do not occur due to a signal change, power consumption in the wirings 15a and 16a can be suppressed.

In general, as LSI design becomes finer, the ratio of gate power consumption to the total power consumption of a circuit decreases, and conversely, the ratio of wiring power consumption increases. In particular, in a process of 0.25 μm or less, the power consumption due to the operation of one NMOS gate is much smaller than the power consumption due to charging / discharging of one wiring. Further, since the current flowing when the NMOS gate is non-conductive is only the leakage current, the power consumed by this is negligible compared to the power consumed by the wiring.

Therefore, the power consumption of the wirings 15 and 16 reduced by providing the NMOS gates 22 and 26 is much larger than the power consumption increased by providing the NMOS gates 22 and 26. Therefore, the effect of the present embodiment is particularly large in a process of 0.25 μm or less.

(Second Embodiment) In a second embodiment of the present invention, when designing a semiconductor integrated circuit, the switching circuit and the scan flip-flop shown in the first embodiment are integrated into a single circuit component. It is designed as.

FIG. 2 shows a hard macro (hereinafter, “scan macro”) representing a scan flip-flop according to the present embodiment.
FIG. The scan macro as a circuit component shown in FIG. 2 is configured by combining a general scan flip-flop 32 and a switching circuit 33 including an NMOS gate 34 and a pull-down element 35. The switching circuit 33 is provided on a wiring 36 connected to the scan-out terminal SO of the scan macro among the output signal lines of the scan flip-flop 32. The gate of the NMOS gate 34 is connected to the scan enable terminal SE of the scan macro.

The scan macro of FIG. 2 operates as follows. When the input signal of the scan enable input terminal SE is “0”, the data received from the normal data input terminal D is taken into the scan flip-flop 31 in synchronization with the clock signal inputted to the clock input terminal CK, and taken in. The signal is output from the data output terminal Q.
At this time, since the NMOS gate 34 is cut off,
The signal captured by the scan flip-flop 32 is not output to the scan out terminal SO. The signal at the scan-out terminal SO is set to “0” by the pull-down element 35 and does not change during normal operation.

On the other hand, when the input signal of the scan enable input terminal SE is "1", the scan data input terminal S
The data received from I is taken into the scan flip-flop 32 in synchronization with the clock signal inputted to the clock input terminal CK, and the taken signal is outputted from the data output terminal Q. At this time, the NMOS gate 34
Becomes conductive, the scan flip-flop 32
Are also output to the scan-out terminal SO at the same time.

FIG. 3 is a circuit diagram showing a semiconductor integrated circuit according to the present embodiment, which is configured using the scan macro shown in FIG. In FIG. 3, a semiconductor integrated circuit 1A includes first and second scan macros 31A and 31B.
And a scan-in terminal 7 and a scan-out terminal 8
Is provided. The first and second scan macros 31A and 31B are each configured as shown in FIG.

The semiconductor integrated circuit 1A shown in FIG. 3 operates as follows. During the test, the scan enable signal S
When E is "1" (shift mode), the NMOS gates 34 of the first and second scan macros 31A and 31B become conductive, and the signal path of the scan chain 30 from the scan-in terminal 7 to the scan-out terminal 8 Works fine. For this reason, the signal values necessary for testing the combinational circuit 2 are stored in the first and second scan macros 31.
A and 31B can be written via the scan chain 30.

When the scan enable signal SE is "0" (capture mode), the first and second scan macros 31A and 31B receive the test result signal from the combinational circuit 2. In this case, the scan enable signal SE is then set to “1” (shift mode), so that the first and second scan macros 31A, 31A
The test result signal of the combinational circuit 2 taken into 1B can be observed from the scan-out terminal 8.

On the other hand, during normal operation, the scan enable signal SE is fixed at "0". The first and second scan macros 31A and 31B receive a signal from the combinational circuit 2 from the normal data input terminal D, output a signal from the data output terminal Q, and apply the signal to the combinational circuit 2 respectively.
At this time, the first and second scan macros 31A, 31A
The 1B NMOS gate 34 is cut off, and the signal value of the scan-out terminal SO of the first and second scan macros 31A and 31B is always set to "0" by the pull-down element 34. Therefore, the signal values of the wirings 37 and 38 also become “0” and do not change during the normal operation of the semiconductor integrated circuit 1A. Therefore, charging and discharging due to signal changes do not occur in the wirings 37 and 38, so that power consumption can be suppressed.

According to this embodiment, by designing the scan flip-flop and the switching circuit as a single circuit component, the effect of suppressing power consumption can be obtained more remarkably than in the first embodiment.

FIG. 4 is a diagram schematically showing an example of the layout of the semiconductor integrated circuit 1A of FIG. In FIG. 4, FIG.
The same components as those in FIG. 3 are denoted by the same reference numerals as those in FIG.
In the present embodiment, the flip-flop 32A and the switching circuit 33A are designed as a first scan macro 31A, and the flip-flop 32B and the switching circuit 33B are designed as single circuit components as a second scan macro 31B. As a result, as shown in FIG.
3A is arranged near the flip-flop 32A, and the switching circuit 33B is arranged near the flip-flop 32B. Thereby, the wiring from the branch point J1 of the output signal line of the scan flip-flop 32A to the switching circuit 33A,
In addition, the length of the wiring from the branch point J2 of the output signal line of the scan flip-flop 32B to the switching circuit 33B becomes extremely short.

FIG. 5 is a diagram schematically showing an example of the layout of the semiconductor integrated circuit 1 of FIG. 1 according to the first embodiment. 5, the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG. In this case, the first switching circuit 2
1 is not necessarily arranged near the first scan flip-flop 11, and the second switching circuit 25 is not necessarily arranged near the second scan flip-flop 12. Therefore, the first scan flip-flop 1
1 from the branch point J1 of the output signal line to the first switching circuit 21, and the second scan flip-flop 12
The length of the wiring from the branch point J2 of the output signal line to the second switching circuit 25 becomes considerably longer than the layout of FIG.

That is, in the first embodiment, while a little useless power consumption occurs due to a signal change in the wiring from the branch point of the output signal line of the scan flip-flop to the switching circuit, according to the present embodiment, Since the switching circuit is arranged in the vicinity of the scan flip-flop, the wiring from the branch point of the output signal line of the scan flip-flop to the switching circuit is extremely short, thereby reducing power consumption in these wirings during normal operation. Can be eliminated.

Therefore, according to the present embodiment, the effect of suppressing power consumption can be obtained more remarkably than in the first embodiment.

In each of the embodiments, the NMOS gate is used as the switch gate of the switching circuit. However, instead of this, a PMOS gate, a CMOS gate, a three-state buffer, a three-state inverter, or the like is turned on in response to a control signal. -Other elements capable of switching control of non-conduction may be used.

In each of the embodiments, the pull-down element is used as the potential fixing element of the switching circuit. However, instead of this, a pull-up element or a hold element having a function of holding a signal value may be used. I don't care.

FIG. 6 is a diagram showing a modification of the scan macro shown in FIG. In the figure, in (a), the switching circuit 51A
Are constituted by a PMOS gate 52 as a switch gate and a pull-down element 53 as a potential fixing element. An inverter 54 is provided for controlling the PMOS gate 52 by the scan enable signal SE. In FIG. 6B, the switching circuit 51B includes a CMOS gate 55 as a switch gate and a pull-down element 53.

In FIG. 6C, the switching circuit 51C includes an NMOS gate 56 as a switch gate and a hold element 57 as a potential fixing element. The hold element 57 is constituted by two inverters having weak driving forces. The holding element 57 is an NMOS
When the gate 56 is non-conductive, the terminal Q of the scan flip-flop 23 immediately before the NMOS gate becomes non-conductive.
And outputs the output signal.

[0044]

As described above, according to the present invention, during normal operation, no signal change occurs on the output side wiring of the switching circuit and no power consumption occurs, so that wasteful power consumption due to the signal change on the wiring is suppressed. Can be Therefore, the power consumption of the semiconductor integrated circuit during normal operation can be further reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a scan macro according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a semiconductor integrated circuit configured using the scan macro shown in FIG. 2;

FIG. 4 is a diagram schematically illustrating an example of a layout of the semiconductor integrated circuit of FIG. 3;

FIG. 5 is a diagram schematically illustrating an example of a layout of the semiconductor integrated circuit of FIG. 1;

FIGS. 6A to 6C are diagrams showing modified examples of the scan macro shown in FIG.

FIG. 7 is a circuit diagram showing a conventional semiconductor integrated circuit.

[Explanation of symbols]

1, 1A Semiconductor integrated circuit 10, 30 Scan chain 11 First scan flip-flop (storage element) 12 Second scan flip-flop (storage element) 15, 16 Wiring 15a Output side wiring of first switching circuit 16a Second 21. First switching circuit 22, 26 NMOS gate (switch gate) 23, 27 Pull-down element (potential fixing element) 25 Second switching circuit 32, 32A, 32B Scan flip-flop (storage element) 33, 33A, 33B, 51A, 51B, 51C Switching circuit 34, 56 NMOS gate (switch gate) 35, 53 Pull-down element (potential fixing element) 52 PMOS gate (switch gate) 55 CMOS gate (switch gate) 57 Hold element ( Potential fixed element) SE scan Enable signal (control signal)

Claims (7)

[Claims] A storage element forming a scan chain; and an output signal line of the storage element, which is included in a signal path included in a signal path in a shift mode and not included in a signal path in a normal operation, A switching circuit for switching an output according to a control signal indicating whether or not the mode is a shift mode, wherein the switching circuit conducts the input side wiring and the output side wiring when the control signal indicates the shift mode. A semiconductor integrated circuit that outputs a fixed value irrespective of an input signal so as to output an input signal as it is and, when the shift mode is not indicated, to suppress power consumption in an output side wiring. 2. The semiconductor integrated circuit according to claim 1, wherein the storage element and the switching circuit are designed as a single circuit component when designing the semiconductor integrated circuit. circuit. 3. The semiconductor integrated circuit according to claim 1, wherein said switching circuit is arranged near said storage element. 4. The semiconductor integrated circuit according to claim 1, wherein the switching circuit switches and controls conduction / non-conduction between an input wiring and an output wiring in accordance with the control signal. A semiconductor integrated circuit comprising: a potential fixing element for fixing the potential of the output side wiring to a predetermined value when the switch gate is in a non-conductive state. 5. A switch gate comprising: an NMOS gate;
5. The semiconductor integrated circuit according to claim 4, wherein the semiconductor integrated circuit is constituted by a MOS gate or a CMOS gate. 6. The semiconductor integrated circuit according to claim 4, wherein said potential fixing element is constituted by a pull-down element, a pull-up element or a hold circuit. 7. The method for designing a semiconductor integrated circuit according to claim 1, wherein the storage element and the switching circuit are designed as a single circuit component.