JP2005210009A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of reducing its consuming current in a sleep state while suppressing the increase of its circuit scale. <P>SOLUTION: The semiconductor integrated circuit has logical circuits 21-23 for performing logical operations based on a plurality of signals, and has a plurality of scanning flip-flops 11-17 for so holding in a usual mode a plurality of signals inputted respectively to a plurality of input terminals as to feed them to the logical circuits, for so holding in a test mode test signals inputted as serial data as to feed them to the logical circuits, and for so holding in a sleep mode signals set in order to reduce leakage currents in the logical circuits as to feed it to the logical circuits. Further, the circuit has a control unit 31 for controlling the switching of the operations in the plurality of scanning flip-flops and for feeding in the sleep mode to the plurality of scanning flip-flops the signals set in order to reduce the leakage currents in the logical circuits. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention generally relates to semiconductor integrated circuits, and more particularly to a semiconductor integrated circuit including a logic circuit that performs a logical operation based on a plurality of signals.

  Conventionally, it is required to increase the operation speed of a semiconductor integrated circuit. A logic circuit included in a semiconductor integrated circuit includes a large number of transistors, and high-speed computation can be performed by speeding up a switching operation for turning on / off these transistors. In order to speed up the switching operation of the MOS transistor, it is effective to shorten the gate length between the source and the drain.

  Generally, the fineness of a semiconductor integrated circuit is expressed by a process rule (micron rule). In recent years, miniaturization of semiconductor integrated circuits has progressed, and the 0.18 micron rule with a basic wiring thickness of 0.18 μm, and the basic wiring thickness of 0.13 μm with 0.13 μm. Semiconductor integrated circuits such as rules are manufactured.

  As described above, by manufacturing a semiconductor integrated circuit with a fine structure, the gate length of the transistor is shortened to realize high-speed computation. On the other hand, by shortening the gate length, the transistor is turned off. There is a problem that the leakage current flowing between the source and the drain is increasing. Therefore, there is a demand for a semiconductor integrated circuit that can reduce current consumption in such a steady state.

  Patent Document 1 described below describes that the leakage current in a logic circuit largely depends on the input state. For example, a CMOS 2-way NAND gate has a leakage current that is an order of magnitude lower when both inputs are low than when both inputs are high.

  The logic system design method disclosed in Patent Document 1 forces a logic gate state and reduces leakage based on probability analysis. According to this logical system design method, the observability “don't care” information, which is a set of inputs in a situation not related to the value of the net, is used to identify the sleep state of each net, and the expected power consumption is reduced. Expected power consumption can be reduced by forcing the net to a specific value based on a probability analysis that determines the net to be reduced.

However, in order to gate the incoming signal, it is necessary to arrange gating logic and power minimization must be performed according to functional constraints. Accordingly, since the circuit configuration is redundant, the circuit scale is increased, and power minimization is performed according to the function restriction, so that there is a problem that the leakage current to be reduced is small.
JP 2002-230066 (pages 1, 9, 13 and FIG. 5)

  In view of the above, an object of the present invention is to provide a semiconductor integrated circuit that can reduce current consumption in a sleep state while suppressing an increase in circuit scale.

  In order to solve the above-described problem, a semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit in which a test mode, a normal mode, and a sleep mode can be set, and at least one logic that performs a logical operation based on a plurality of signals. In the normal mode, the circuit holds a plurality of signals input to a plurality of input terminals and supplies them to the logic circuit. In the test mode, a test signal input as serial data is held and supplied to the logic circuit In the sleep mode, a plurality of scan flip-flops that hold a signal set to reduce leakage current in the logic circuit and supply the logic circuit, and control switching of operations in the plurality of scan flip-flops, and sleep Mode, the signal set to reduce the leakage current in the logic circuit. The includes a supply control unit to a plurality of scan flip-flops.

  Here, each of the plurality of scan flip-flops selects one of the plurality of input signals according to the supplied control signal, and the selection circuit synchronizes with the supplied clock signal. A flip-flop that holds the selected signal may be included.

  In addition, the semiconductor integrated circuit stores a signal set to reduce the leakage current in the logic circuit and a signal held by the plurality of scan flip-flops immediately before shifting from the normal mode to the sleep mode. May be further provided.

  The semiconductor integrated circuit also includes a clock signal generation circuit that generates a clock signal, and a clock signal generation circuit and a plurality of scan flip-flops so that the plurality of scan flip-flops operate in synchronization with an external clock signal in the test mode. And a switch circuit that cuts off a signal path between the two.

  According to the present invention, a plurality of scan flip-flops provided for a test operation are used to supply a signal set to reduce a leakage current in a sleep state to a logic circuit. Current consumption in the sleep state can be reduced while suppressing an increase in scale.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. The same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 1 shows a configuration of a semiconductor integrated circuit according to an embodiment of the present invention. In this semiconductor integrated circuit, a plurality of scan flip flops (SFF) 11 to 17, a plurality of logic circuits (combining logic circuits) 21 to 23, and a control for controlling operation switching between a normal mode and a sleep mode. A unit 31, a memory 32, a switch circuit 33, and a clock signal generation circuit 34 for generating an internal clock signal CLK are included.

  By connecting an LSI tester to the input / output terminals of the semiconductor integrated circuit, a test operation using an SFF can be performed under the control of the LSI tester. The SFFs 11 to 17 are configured by selection circuits 11A to 17A and flip flops (FF) 11B to 17B, respectively. In the test mode, these SFFs 11 to 17 sequentially hold the test signals input as serial data and supply them to the logic circuits 21 to 23. In the semiconductor integrated circuit according to the present embodiment, the circuit configuration is prevented from becoming redundant by reducing the current consumption in the sleep mode by using the SFF provided for easily performing the test operation. It is out.

  The switch circuit 33 is obtained by inverting the stop signal STP by the inverter 33A that inverts the stop signal STP input from the control unit 31, the P-channel MOS transistor 33B that receives the stop signal STP at the gate, and the inverter 33A. And an N channel MOS transistor 33C to which a signal is input to the gate. The switch circuit 33 is turned on when the stop signal STP is at the low level, supplies the internal clock signal CLK generated by the clock signal generation circuit 34 to the SFFs 11 to 17, and when the stop signal STP is at the high level. Turn off.

Next, the operation of the semiconductor integrated circuit according to the present embodiment will be described.
In the normal mode, the stop signal STP is at a low level, and the internal clock signal CLK generated by the clock signal generation circuit 34 is supplied to the SFFs 11 to 17 through the switch circuit 33. The sleep enable signal SE is also at a low level, and the selection circuits 11A to 17A included in the SFFs 11 to 17 respectively select signals input to the terminal Y. The FFs 11B to 17B included in the SFFs 11 to 17 respectively hold the signals selected by the selection circuits 11A to 17A in synchronization with the internal clock signal CLK.

  Thus, in the normal mode, the SFFs 11 to 17 operate in the same manner as a normal flip-flop circuit. As a result, the signals input to the input terminals A to E are supplied to the logic circuits 21 and 22, and the signals S21 and S22 obtained by the logic operation in the logic circuits 21 and 22 are supplied to the logic circuit 23. A signal obtained by the logical operation in the circuit 23 is output from the output terminal F.

  In the test mode, a test enable signal TE, a test input signal TI, a test clock signal TCLK, and a stop signal STP are input from an LSI tester connected via an input / output terminal. The test input signal TI is a test pattern for detecting whether or not a fault location exists in the logic circuit of the semiconductor integrated circuit, and is input as serial data.

  As an operation in the test mode, first, the selection circuits 11A to 17A select the test input signal TI input to the terminal X in accordance with the high level test enable signal TE input from the LSI tester. Further, the FFs 11B to 17B hold the signals selected by the selection circuits 11A to 17A in synchronization with the test clock signal TCLK input from the LSI tester.

  Here, since the test input signal TI is input as serial data, each bit included in the test input signal TI is sequentially held in the FFs 11B to 17B for each pulse of the test clock signal TCLK. That is, when the test enable signal TE is at a high level, the SFFs 11 to 17 function as shift registers. By inputting clock pulses for the number of stages of FFs, a plurality of bits included in the test input signal TI are held in all the FFs, respectively, and then a signal obtained by logical operation in the logic circuit 23 is It is output to the LSI tester via the output terminal F.

  Next, in accordance with the low level test enable signal TE input from the LSI tester, the selection circuits 16A and 17A select the signals S21 and S22 that are logically operated in the logic circuits 21 and 22 and are supplied to the terminal Y, respectively. . Further, the FFs 16B and 17B hold the signals selected by the selection circuits 16A and 17A in synchronization with the pulse of the test clock signal TCLK input from the LSI tester. Thereafter, a signal obtained by the logical operation in the logic circuit 23 is output to the LSI tester via the output terminal F.

  Further, the selection circuit 17A selects a signal input to the terminal X in accordance with the high level test enable signal TE input again from the LSI tester. Further, the FF 17B holds the signal selected by the selection circuit 17A in synchronization with the test clock signal TCLK input from the LSI tester. Thereby, the signals S21 and S22 logically operated in the logic circuits 21 and 22 are output to the LSI tester as the test output signal TO of the serial data as the test result.

  In the sleep mode, a stop signal STP, a sleep enable signal SE, and a sleep input signal SI are supplied from the control unit 31. The sleep input signal SI is a data pattern for reducing the leakage current of the logic circuits 21 to 23 and is supplied as serial data.

  For example, it is assumed that the leakage currents of the logic circuits 21 and 22 are smaller when all input signals are at a low level. Further, it is assumed that the leakage current of the logic circuit 23 is smaller when all input signals are at a high level. In this case, the sleep input signal SI is set so that the SFFs 11 to 15 hold a low level signal and the SFFs 16 and 17 hold a high level signal. Thus, by fixing the input signals of the logic circuits that are not involved in the operation in the sleep mode to a predetermined level, current consumption in those logic circuits can be reduced.

  FIG. 2 is a timing chart for explaining the operation of the semiconductor integrated circuit according to the present embodiment. As shown in FIG. 2, in the normal operation, the control unit 31 sets the sleep enable signal SE to a low level and the stop signal STP to a low level. Accordingly, the SFFs 11 to 15 respectively hold signals input to the input terminals A to E in synchronization with the internal clock signal CLK. The logic circuits 21 and 22 perform a logical operation based on these signals.

  The SFF 16 holds the output signal S21 of the logic circuit 21 in synchronization with the internal clock signal CLK. Similarly, the SFF 17 holds the output signal S22 of the logic circuit 22 in synchronization with the internal clock signal CLK. The logic circuit 23 performs a logical operation based on these signals.

  In the sleep mode, the control unit 31 sets the sleep enable signal SE to a high level, so that the SFFs 11 to 17 function as shift registers. As shown in FIG. 2, in the sleep mode, three operations are performed: a sleep start setting operation, a sleep maintenance operation, and a sleep release setting operation.

  First, in the sleep start setting operation, the control unit 31 keeps the stop signal STP at a low level for a predetermined period, reads out and outputs the sleep input signal SI stored in the memory 32. As a result, the SFFs 11 to 17 sequentially hold the serial data P7 to P1 included in the sleep input signal SI output from the control unit 31 in synchronization with the internal clock signal CLK. The memory 32 stores data patterns for reducing leakage currents of the logic circuits 21 to 23 as serial data P1 to P7.

  The control unit 31 causes the SFFs 11 to 17 to hold the serial data P7 to P1, and reads the signal held by the SFFs 11 to 17 as the sleep output signal SO immediately before shifting from the normal mode to the sleep mode, and outputs the sleep output. The signal SO is stored in the memory 32. That is, the control unit 31 sequentially reads output signals from the SFFs 17 to 11 and stores them in the memory 32. The stored sleep output signal SO is used in the sleep cancel setting operation.

  Next, in the sleep maintaining operation, the control unit 31 maintains the stop signal STP at a high level. As a result, the internal clock signal CLK is not supplied to the SFFs 11 to 17 and the shift operation of the SFFs 11 to 17 is stopped, so that the SFFs 11 to 17 output a data pattern for reducing the leakage current of the logic circuits 21 to 23. to continue. Therefore, power consumption in these logic circuits can be reduced.

  Finally, in the sleep release setting operation, the control unit 31 sets the stop signal STP to the low level and restarts the supply of the internal clock signal CLK, and reads the sleep output signal SO stored in the memory 32 during the sleep start setting operation. And output to the SFF 11 as the sleep input signal SI. The SFFs 11 to 17 function as shift registers and sequentially hold the sleep input signal SI output from the control unit 31. Thereby, the signals held by the SFFs 11 to 17 can be returned to the state immediately before the sleep operation. Thereafter, the control unit 31 sets the sleep enable signal SE to a low level to cancel the sleep mode and return to the normal mode.

  In the present embodiment, a data pattern for reducing the leakage current of the logic circuits 21 to 23 is stored in the memory 32. However, the data pattern may be generated by a logic circuit such as a pattern generator. good.

  The present invention can be used in a semiconductor integrated circuit, in particular, a semiconductor integrated circuit including a logic circuit that performs a logical operation based on a plurality of signals.

1 is a diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention. 2 is a timing chart for explaining the operation of the semiconductor integrated circuit of FIG.

Explanation of symbols

11-17 SFF, 11A-17A selection circuit, 11B-17B FF, 21-23 logic circuit, 31 control unit, 32 memory, 33 switch circuit, 33A inverter, 33B P channel MOS transistor, 33C N channel MOS transistor, 34 clock Signal generation circuit

Claims (4)

A semiconductor integrated circuit capable of setting a test mode, a normal mode, and a sleep mode,
At least one logic circuit that performs a logical operation based on a plurality of signals;
In the normal mode, a plurality of signals respectively input to a plurality of input terminals are held and supplied to the logic circuit. In the test mode, a test signal input as serial data is held and supplied to the logic circuit. In sleep mode, a plurality of scan flip-flops that hold a signal set to reduce leakage current in the logic circuit and supply the signal to the logic circuit;
A control unit that controls switching of operations in the plurality of scan flip-flops, and supplies a signal set to reduce the leakage current in the logic circuit to the plurality of scan flip-flops in a sleep mode;
A semiconductor integrated circuit comprising: Each of the plurality of scan flip-flops is
A selection circuit that selects one of a plurality of input signals in accordance with a supplied control signal;
A flip-flop that holds a signal selected by the selection circuit in synchronization with a supplied clock signal;
The semiconductor integrated circuit according to claim 1, comprising:   Storage means for storing a signal set to reduce a leakage current in the logic circuit and a signal held by the plurality of scan flip-flops immediately before shifting from the normal mode to the sleep mode; The semiconductor integrated circuit according to claim 1 or 2. A clock signal generation circuit for generating a clock signal;
In a test mode, a switch circuit that blocks a signal path between the clock signal generation circuit and the plurality of scan flip-flops so that the plurality of scan flip-flops operate in synchronization with an external clock signal;
The semiconductor integrated circuit according to claim 1, further comprising:

Images