JPH112664A - Boundary scan register - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily detect malfunction independently of internal circuit without increasing circuit size by inputting the output signal of a boundary scan register in the output buffer of an input output I/O cell. SOLUTION: An input output I/O cell 22 has an input buffer 22a and an output buffer 22b and the input signal from the input output terminal. PAD is input in the input buffer 22a. In the output buffer 22b, a reverse signal PO<-> output from the multiplexer 18 of boundary scan register 10 is input, a control signal is input in the output control terminal and its output signal is input in the input buffer 22a. In this manner, the output buffer 22b of essentially unused input output I/O cell 22 is used as a part of constitution element of the boundary scan register 10 and so the circuit size of the boundary scan register 10 does not increase. By this, detection of malfunction can be easily done by logically separating from the internal circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI board on which a plurality of semiconductor devices are mounted, such as a printed circuit board, for testing the wiring of the LSI board for connecting the individual semiconductor devices, and for testing the LSI board. The present invention relates to a boundary scan register incorporated in each semiconductor device as a part of an internal circuit of the semiconductor device for a function test or the like of the semiconductor device mounted thereon.

[0002]

2. Description of the Related Art A boundary scan register uses an IEEE standard.
E (Institute of Electrical and Electronics Engine
ers: Association of Electrical and Electronic Engineers) 1149.1 (JTAG)
In the test circuit standardized in, provided in correspondence to each input terminal, output terminal, signal terminals such as input / output terminals of the semiconductor device, for example, by the test control signal, all the boundary scan registers It is electrically connected serially to constitute one large-scale scan chain (shift register).

An example of a conventional boundary scan register will be described below, and its problem will be described.

FIG. 3 is a circuit diagram showing an example of a conventional boundary scan register. The figure shows a part of a boundary scan register group provided corresponding to the input terminal of the semiconductor device, among the boundary scan registers provided corresponding to the respective signal terminals of the semiconductor device. The boundary scan register 24 includes multiplexers (MUX1, MUX2) 12, 18, flip-flops (FF1, FF2) 14, 16, and
It has an inverter 20.

Here, an input signal input from an input terminal of the semiconductor device is input to an input I / O cell 26. One input terminal of the multiplexer 12 has an input I / O cell 2
6, the other input terminal receives the scan-in signal SI input from the scan-in input terminal of the semiconductor device or the output signal of the flip-flop 14 of the other boundary scan register 24. The control signal SD is input to the selection input terminal.

The output signal of the multiplexer 12 is input to the data input terminal of the flip-flop 14. The clock signal CC is input to the clock input terminal of the flip-flop 14.
Is input to the data input terminal of the flip-flop 16 and the other input terminal of the multiplexer 12 of another boundary scan register 24, or the scan-out signal SO
Is output from the scan-out output terminal of the semiconductor device.

The clock signal UC is input to the clock input terminal of the flip-flop 16. The output signal PI of the input I / O cell 26 is input to one input terminal of the multiplexer 18, the output signal of the flip-flop 16 is input to the other input terminal, and the control signal is input to the selected input terminal. MD is input. Multiplexer 18
Is input to the inverter 20,
Output signal PO of inverter 20 is input to internal circuit 28.

As described above, the boundary scan register is provided corresponding to each signal terminal of the semiconductor device. Accordingly, each of the output terminals of the semiconductor device is provided with a boundary scan register 24 having the same configuration. However, in the case of the output terminal, the output signal PI of the input I / O cell 26 is replaced with the internal signal, as opposed to the input terminal. Circuit 2
8 and the output signal PO of the inverter 20 is output from the output terminal of the semiconductor device via an output I / O cell (not shown).

When performing a wiring test of an LSI board, first, a scan signal SI input from a scan input terminal or an output signal of a flip-flop 14 of another boundary scan register 24 is supplied to a multiplexer 12 by a control signal SD. Set to output from Thereby, one multiplexer 12 and flip-flop 14 constitute one scan chain that serially connects the scan-in input terminal and the scan-out output terminal.

The control signal MD sets the output signal of the flip-flop 16 from the multiplexer 18 to be output. Thereby, the internal circuit 28 includes
The output signal of the flip-flop 16 of the boundary scan register 24 provided corresponding to the input terminal of the semiconductor device is input via the multiplexer 18 and the inverter 20, and the output terminal of the semiconductor device is output from the output terminal of the semiconductor device. The output signal of the flip-flop 16 of the boundary scan register provided corresponding to the terminal is output.

Subsequently, while sequentially inputting the scan-in signal SI through the scan-in input terminal, the clock signal CC is supplied to the flip-flop 14, and the flip-flop 14 at the preceding stage of the scan chain
, The scan-in signal SI is sequentially shifted to the flip-flop 14 of the next stage, and a predetermined value is set in the flip-flop 14 of the boundary scan register provided corresponding to each output terminal of the semiconductor device.

Subsequently, a clock signal UC is applied to the flip-flops 16 and the output signals of the respective flip-flops 14 are held in the corresponding flip-flops 16 so as to correspond to the output terminals of the semiconductor device. The output signal of the flip-flop 16 of the provided boundary scan register is output from each output terminal. The output signal output from each of these output terminals is
Via the wiring of the board, for example, it is input as an input signal to each input terminal of another semiconductor device.

In a semiconductor device in which an input signal is input to each input terminal, an output signal PI of an input I / O cell 26 is set to be output from a multiplexer 12 by a control signal SD, and a clock is supplied to a flip-flop 14. A signal CC is supplied to each flip-flop 14 of a boundary scan register 24 provided corresponding to an input terminal of the semiconductor device, the input being an input signal input from each input terminal of the corresponding semiconductor device. The output signal PI of the I / O cell 26 is held.

Subsequently, the control signal SD is set so that the scan-in signal SI input from the scan-in input terminal or the output signal of the flip-flop 14 of another boundary scan register 24 is output from the multiplexer 12. , A clock signal CC is applied to the flip-flop 14 to sequentially shift the output signal of the flip-flop 14 from the preceding flip-flop 14 to the next-stage flip-flop 14 in the scan chain. Are sequentially output from the scan-out output terminal.

As described above, in the LSI board on which the semiconductor device incorporating the boundary scan register 24 is mounted, the scan-in signal SI serially input from the scan-in input terminal is output in parallel from each output terminal of the semiconductor device. By serially outputting an input signal input to each input terminal of another semiconductor device in parallel as a scan-out signal SO from the scan-out output terminal, it is possible to easily test the wiring of the LSI board.

Also, when performing a single function test of each semiconductor device mounted on the LSI board, first, the control signal SD is set so as to form a scan chain, and the control signal MD causes the multiplexer 18 to start the scan chain. After setting so that the output signal of the flip-flop 16 is output, the scan-in signal SI is sequentially input from the scan-in input terminal, and the scan-in signal SI of the boundary scan register 24 provided corresponding to each input terminal of the semiconductor device is provided. A predetermined value is set in the flip-flop 14.

Subsequently, by holding the output signal of the flip-flop 14 in the corresponding flip-flop 16, the output signal of the flip-flop 16 of the boundary scan register 24 provided corresponding to each input terminal of the semiconductor device. The signal is supplied as an input signal to the internal circuit 28. Therefore, the internal circuit 28 operates according to the value of the output signal of the flip-flop 16 of the boundary scan register 24 provided corresponding to each input terminal of the semiconductor device.

Then, the control signal SD is set so that the output signal of the internal circuit 28 is output from the multiplexer 12 of the boundary scan register provided corresponding to the output terminal. After holding the output signal output from 28,
The control signal SD is set so as to form a scan chain, and the signal held in the flip-flop 14 is sequentially output as a scan-out signal SO from a scan-out output terminal.

As described above, in the LSI board on which the semiconductor device incorporating the boundary scan register 24 is mounted, the scan-in signal SI serially input from the scan-in input terminal is supplied to the internal circuit 28 in parallel, and the internal circuit 28 By serially outputting the output signals output in parallel as the scan-out signal SO from the scan-out output terminal, it is possible to easily perform a functional test of the semiconductor device mounted on the LSI board.

Incidentally, the boundary scan register 24 is built in the semiconductor device as a part of the internal circuit 28, as described above. Therefore, the semiconductor device incorporating the boundary scan register 24 can be used, for example, in a final shipment test of the semiconductor device by a tester, not only for the internal circuit 28 but also for the boundary scan register 24 provided for each signal terminal. Needless to say, it is necessary to detect a failure.

For example, the failure of the multiplexer 12 and the flip-flop 14 is detected by the control signal SD.
An input signal input in parallel from each input terminal of the semiconductor device is held in the flip-flop 14, or a scan-in signal SI is serially input from the scan-in input terminal to set a predetermined value in the flip-flop 14, From the scan out output terminal to the scan out signal S
This can be easily performed by serial output as O.

On the other hand, the failure detection of the flip-flop 16 and the multiplexer 18 is performed by, for example, the above-described LS
The output signal of the flip-flop 16 is supplied to the internal circuit, and the output signal from the internal circuit 28 is output from the output terminal of the semiconductor device in the same manner as in the case of performing the function test of the semiconductor device mounted on the I board. Alternatively, if serial output is performed by a boundary scan register 24 provided corresponding to this output terminal, this can be performed although it is difficult.

However, in order to detect the failure of the flip-flop 16 and the multiplexer 18, an input signal is inputted from the input terminal of the semiconductor device and the input I / O cell 26 is inputted.
It is necessary to create a test pattern equivalent to the case of performing the fault detection of the above, but since the toggle state of the input signal must be determined based on the output signal from the internal circuit 28,
Unless a designer or the like is familiar with the logic of the internal circuit 28, it is difficult to create a test pattern, and there is a problem that the number of test patterns increases according to the circuit size.

In order to detect a failure of the flip-flop 16 and the multiplexer 18, the input I /
A test pattern for detecting a failure of the O cell 26,
The input signal input in parallel from the input terminal of the semiconductor device must be serially input from the scan-in input terminal and set in each flip-flop 16 forming the scan chain. It is necessary to convert a test pattern for detection into a test pattern for a scan test.

For this reason, the test pattern for the scan test for detecting the failure of the flip-flop 16 and the multiplexer 18 depends on the complexity of the logic of the internal circuit 28 and the increase in the number of input terminals of the semiconductor device. /
The test pattern for detecting the failure of the O-cell 26 is much larger than the test pattern, and the test pattern cannot be stored in the limited pattern memory of the tester, or even if it is, the test time becomes extremely long, and the test cost is increased. There was a problem that it increased.

On the other hand, the present inventor has disclosed in, for example,
148290 discloses a flip-flop 16
And a boundary scan register that can easily detect a failure of the multiplexer 18.

FIG. 4 is a circuit diagram showing an example of the boundary scan register disclosed in the above publication. The boundary scan register 30 in the illustrated example is different from the boundary scan register 24 shown in FIG. Since the other components are the same as those of the boundary scan register 24, the same components are denoted by the same reference numerals, and detailed description thereof will be omitted.

That is, the added multiplexer 32
The output signal PI of an input I / O cell (not shown) is input to one input terminal, and the inverted signal PO # output from the multiplexer 18 is input to the other input terminal. Receives a control signal BT. Note that one input terminal of the multiplexer 12 has
Instead of the output signal PI of the input I / O cell not shown, the output signal of the multiplexer 32 is input.

The illustrated boundary scan register 30
The operation when the output signal PI of the input I / O cell (not shown) is set to be output from the multiplexer 32 by the control signal BT, for example, is completely the same as the operation of the boundary scan register 24 shown in FIG. Is the same. The failure detection of the multiplexer 12 and the flip-flop 14 is also performed by the boundary scan register 24.
Can be performed in exactly the same way as in the case of

In the boundary scan register 30, the flip-flop 16 and the multiplexer 1
The fault detection of No. 8 is performed as follows.

First, the input I / O is controlled by the control signal BT.
The cell output signal PI is set to be output from the multiplexer 32, the control signal SD sets the output signal of the multiplexer 32 to be output from the multiplexer 12, and the control signal MD sets the flip-flop 16 After setting the output signal to be output from the multiplexer 18, the input signal is input from each input terminal of the semiconductor device, and is held in the corresponding flip-flop 14 in parallel.

Alternatively, the output signal of the flip-flop 14 of another boundary scan register 30 is set to be output from the multiplexer 12 by the control signal SD, and the output signal of the flip-flop 16 is set by the control signal MD. After the setting, the scan-in signal SI is serially input from the scan-in input terminal, and a predetermined value is set in the flip-flop 14 of each boundary scan register 30.

Subsequently, the control signal BT sets the inverted signal PO # output from the multiplexer 18 to be output from the multiplexer 32, and the control signal SD causes the output signal of the multiplexer 32 to be output from the multiplexer 12. Then, the output signal of the flip-flop 14 is held in the flip-flop 16, and the output signal of the flip-flop 16 inverted by the multiplexer 18 is held in the flip-flop 14 via the multiplexers 32 and 12.

That is, at this stage, an inverted signal of the input signal input in parallel from each input terminal of the semiconductor device or an inverted signal of the scan-in signal SI input serially from the scan-in input terminal is supplied to the flip-flop 14 at this stage. The signal is held. Therefore, the flip-flop 14
Is serially output from the scan-out output terminal, and by confirming that this is an inverted signal, the failure of the flip-flop 16 and the multiplexer 18 can be detected.

As described above, in the boundary scan register 30, by providing the multiplexer 32, the inverted signal PO output from the multiplexer 18 is provided.
に is held in the flip-flop 14 and can be serially output. Therefore, the failure detection can be performed by logically separating the internal circuit and the boundary scan register 30, and the failure detection of the boundary scan register 30 alone can be easily performed independently of the failure detection of the internal circuit. There are advantages.

However, the boundary scan register 30 requires a multiplexer 32 for each boundary scan register 30 provided corresponding to the input terminal of the semiconductor device, as compared with the boundary scan register 24 shown in FIG. In addition, since the boundary scan register is basically provided in accordance with each signal terminal, there is a problem that the circuit size of the boundary scan register 30 increases as the number of input terminals of the semiconductor device increases. there were.

[0037]

SUMMARY OF THE INVENTION An object of the present invention is to provide a boundary which can easily detect a fault independently of an internal circuit without increasing the circuit scale, in view of the problems based on the prior art. It is to provide a scan register.

[0038]

The inventor of the present invention has made intensive studies to solve the above-mentioned problems, and as a result, a boundary scan register is basically provided corresponding to a signal terminal of a semiconductor device. In addition, the input I / O cell provided corresponding to the input terminal of the semiconductor device generally uses the output buffer of the input / output I / O cell unused and uses only the input buffer. Attention has been paid, and it has been found that the above object can be achieved by using an unused output buffer of the input / output I / O cell, and based on this, the present invention has been completed.

That is, in order to achieve the above object, the present invention relates to a semiconductor device in which input / output I / O cells having an input buffer and an output buffer are provided corresponding to respective input terminals. A boundary scan register provided corresponding to each input terminal of the semiconductor device, wherein an input signal input from an input terminal of the semiconductor device via an input buffer of an input / output I / O cell, or
A first multiplexer that selectively outputs one of the scan-in signals, a first flip-flop that holds an output signal of the first multiplexer and outputs a scan-out signal, and a first flip-flop that outputs a scan-out signal. A second flip-flop that holds an output signal; an input signal input from an input terminal of the semiconductor device via an input buffer of an input / output I / O cell; or an output signal of the second flip-flop. Second to selectively output
And an inverter for inverting and outputting the output signal of the second multiplexer. The output (PO or PO #) of the boundary scan register is input to the output buffer of the input / output I / O cell. A boundary scan register is provided.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a boundary scan register according to the present invention will be described in detail with reference to a preferred embodiment shown in the accompanying drawings.

FIG. 1 is a circuit diagram showing an embodiment of a boundary scan register according to the present invention. The boundary scan register 10 in the illustrated example is different from the boundary scan register 24 shown in FIG.
, Except that an inverted signal PO # output from the multiplexer 18 is input to the output buffer of the input / output I / O cell 22. Elements have the same reference characters allotted, and detailed description thereof will not be repeated.

That is, the boundary scan register 1
0 is a multiplexer (MUX1) 1 which is basically exactly the same as the boundary scan register 24 shown in FIG.
2, flip-flop (FF1) 14, flip-flop (FF2) 16, multiplexer (MUX2) 1
8 and an inverter 20.

In this embodiment, the flip-flop 1
6, but a latch may be used instead of the flip-flop 16. Further, although the multiplexer 18 uses the one whose output signal is inverted, the present invention is not limited to this, and the multiplexer 18 whose output signal is not inverted may be used. In this case, the signal output from the multiplexer 18 is supplied to the internal circuit as the output signal PO, and
May be used as an inverted signal PO #.

The input / output I / O cell 22 has an input buffer 22a and an output buffer 22b. An input signal input from the input / output terminal PAD of the semiconductor device is input to the input buffer 22a. As described above, the output buffer 22b includes the boundary scan register 10
The inverted signal PO # output from the multiplexer 18 is input, the control signal BT is input to the output control terminal, and the output signal is input to the input buffer 22a.

Here, for example, in a semi-custom LSI such as a gate array system, the input / output I / O cell 22 is generally used.
Of the input terminal of the output buffer 22b of "1" or "0"
And in the case of the input / output I / O cell 22 in the illustrated example, by fixing the output control terminal to “1”, which is an inactive state, and always keeping the output buffer 22b in an unused state. Input buffer 2 of input / output I / O cell 22
2a is used as an input I / O cell.

In the above-mentioned semi-custom LSI,
Generally, input buffer 22a of input / output I / O cell 22
The output buffer 22b of the input / output I / O cell 22 is used as an output I / O cell by releasing the output signal PI of the I / O cell 22 without inputting it anywhere and leaving it unused. That is, by using the input / output I / O cell 22, there is an advantage that it can be used for any of the input I / O cell, the output I / O cell, and the input / output I / O cell. .

Therefore, the input / output I / O cell 22 shown in FIG. 1 is generally used as an input I / O cell provided corresponding to the input terminal of the semiconductor device. The output buffer 22b of the / O cell 22 is usually
It is in an unused state as described above. In the boundary scan register 10 of the present invention, since the unused output buffer 22b is used, the circuit scale as an internal circuit is not increased at all as compared with the boundary scan register 24 shown in FIG.

In a semi-custom LSI such as a standard cell system or a full custom LSI, for example, an input-only input I / O cell is generally used, and the boundary scan register 10 of the present invention is applied to this. For this purpose, the input / output I / O cell 22 may be simply used instead of the input I / O cell. Also in this case, since the I / O cells are arranged in the I / O cell area instead of the core area where the internal circuits are arranged, the internal circuits are not increased at all.

As described above, according to the boundary scan register 10 of the present invention, the boundary scan register 1
Since the originally unused output buffer 22b of the input / output I / O cell 22, which is present in excess of 0, is used as a component of the boundary scan register 10, the circuit scale of the boundary scan register 10 increases. In addition, there is an advantage that the internal circuit does not increase at all even if the number of input terminals of the semiconductor device increases.

The boundary scan register 10 of the present invention
In the case where the control signal BT is set to "1" and the output control terminal of the output buffer 22b of the input / output I / O cell 22 is set to the inactive state, for example, the operation of the boundary scan register 24 shown in FIG. In the same manner as in the case of the boundary scan register 24, the LSI board wiring test and the LSI
A function test of the semiconductor device mounted on the board can be performed.

That is, the boundary scan register 1
In an LSI board on which a semiconductor device having a built-in 0 is mounted, a scan-in signal SI serially input from a scan-in input terminal is output in parallel from each output terminal of the semiconductor device, and is output to each input terminal of another semiconductor device. By serially outputting an input signal input in parallel as a scan-out signal SO from the scan-out output terminal, it is possible to easily test the quality of the wiring of the LSI board.

In an LSI board on which a semiconductor device incorporating the boundary scan register 10 is mounted, a scan-in signal SI serially input from a scan-in input terminal is supplied in parallel to an internal circuit, and is output in parallel from the internal circuit. By serially outputting the output signal from the scan-out output terminal as the scan-out signal SO, the function test of the semiconductor device mounted on the LSI board can be easily performed.

On the other hand, the failure detection of the boundary scan register 10 itself at the time of the final shipping test of the semiconductor device can be easily performed. First, the failure detection of the multiplexer 12 and the flip-flop 14 is performed by setting the output control terminal of the output buffer 22b of the input / output I / O cell 22 to the inactive state by the control signal BT. It can be done in exactly the same way.

That is, the failure of the multiplexer 12 and the flip-flop 14 is detected, for example, by inputting the input signals input in parallel from the respective input / output terminals PAD of the semiconductor device to the respective flip-flops 1 by the control signal SD.
4 or the scan-in signal SI is serially input from the scan-in input terminal and the flip-flop 1
This can be easily performed by setting a predetermined value to 4 and serially outputting this as a scan-out signal SO from the scan-out output terminal.

In the boundary scan register 10, the flip-flop 16 and the multiplexer 1
The fault detection of No. 8 is performed as follows. here,
FIG. 2 is a timing chart of one embodiment showing the operation of the boundary scan register of the present invention. Hereinafter, the operation of the flip-flop 16 and the multiplexer 18 when a failure is detected will be described with reference to the timing chart shown in FIG.

First, in the first phase PH1, the control signal BT is set to “0”, the output control terminal of the output buffer 22b of the input / output I / O cell 22 is set to the active state, and the control signal SD is set to “1”. The output signal of the flip-flop 14 of the other boundary scan register 10 is set so as to be output from the multiplexer 12, and the control signal MD is set to “1” to set the flip-flop 1
6 is set to be output from the multiplexer 18.

Thus, the multiplexer 12 and the flip-flop 14 of each boundary scan register 10 constitute one scan chain that serially connects the scan-in input terminal and the scan-out output terminal. The multiplexer 18 outputs an inverted signal PO # of the output signal of the flip-flop 16.
Is output to the output buffer 22 of the input / output I / O cell 22.
b outputs an inverted signal PO # output from the multiplexer 18.

After that, while sequentially inputting the signal train DI as the scan-in signal SI via the scan-in input terminal, the clock signal CC is supplied to the flip-flop 14 in synchronization with the signal train DI, and the flip-flop 14 at the preceding stage of the scan chain is input. Then, the scan-in signal SI is sequentially shifted to the next-stage flip-flop 14 via the multiplexer 12, and the signal sequence DI is set in each flip-flop 14 of the boundary scan register 10 provided corresponding to the signal terminal.

In the second phase PH 2, first, the control signal SD is set to “0” and the output signal PI of the input buffer 22 a of the input / output I / O cell 22 is
Set to output from Subsequently, the clock signal UC is supplied to the flip-flops 16, and the signal train DI held in each flip-flop 14 is held in parallel in each corresponding flip-flop 16.

Thus, each flip-flop 16
Is inverted by the multiplexer 18. The inverted signal PO # output from the multiplexer 18, that is, the signal train DI #, is supplied to the input / output I / O cell 2
And output from the input / output terminal PAD of the semiconductor device via the second output buffer 22b.
And the data input terminal of the flip-flop 14 via the multiplexer 12.

In the third phase, the clock signal CC is supplied to the flip-flops 14, and each flip-flop 14 holds the output signal PI of the input buffer 22 a input via the multiplexer 12. That is, at this stage, each flip-flop 14 holds a signal sequence DI # obtained by inverting the signal sequence DI which is the scan-in signal SI serially input from the scan-in input terminal.

In the fourth phase, first, the control signal SD is set to “1”, and the multiplexer 12 and the flip-flop 14 are set so as to form a scan chain. The signal sequence DI # is sequentially shifted from the flip-flop 14 at the preceding stage of the chain to the flip-flop 14 at the next stage via the multiplexer 12, and is sequentially output as the scan-out signal SO from the scan-out output terminal.

As described above, in the boundary scan register 10, the inverted signal PO # output from the multiplexer 18 is held in the flip-flop 14 via the output buffer 22b and the input buffer 22a of the input / output I / O cell 22. , Which can be serially output. Therefore, the failure detection of the boundary scan register 10 can be easily performed by logically separating it from the internal circuit, and the test pattern can be automatically generated (ATPG: Auto T).
est Pattern Generation) is also easy.

In the boundary scan register 10 of the present invention, at the time of the final shipping test of the semiconductor device, the signal train DI # output in parallel from each of the input / output terminals PAD can be monitored on the tester. Therefore, after executing the first and second phases of the first to fourth phases of the timing chart shown in FIG. 2, by monitoring the signal train DI # output from the input / output terminal PAD, The operations in the third and fourth phases can be omitted.

As described above, by monitoring the signal sequence output from the input / output terminal PAD, the test pattern and the test time can be reduced, and the test cost can be reduced. When monitoring a signal string output from the input / output terminal PAD, the input / output terminal PA
From D, an inverted signal PO # inverted by the multiplexer 18 may be output, or an output signal PO further inverted by the inverter 20 may be output.

Although the boundary scan register of the present invention has been described in detail, the present invention is not limited to the above-described embodiment, and various improvements and changes may be made without departing from the gist of the present invention. Of course.

[0067]

As described in detail above, the boundary scan register of the present invention is obtained by inputting the output signal of the boundary scan register to an output buffer which is originally unused of the input / output I / O cell. As a result, according to the boundary scan register of the present invention, even if the number of input terminals of the semiconductor device increases, the circuit scale of the test circuit for the boundary scan register does not increase, and logic from the internal circuit does not increase. Thus, the failure of the boundary scan register can be easily detected, and the ATPG of the test pattern can be easily achieved. Further, according to the boundary scan register of the present invention, the output signal of the boundary scan register can be directly monitored at the input / output terminal at the time of the final shipment test of the semiconductor device, so that the test pattern and the test time can be reduced. Test cost can be reduced as a result.

[Brief description of the drawings]

FIG. 1 is a configuration circuit diagram of an embodiment of a boundary scan register of the present invention.

FIG. 2 is a timing chart of an embodiment showing the operation of the boundary scan register of the present invention.

FIG. 3 is a configuration circuit diagram of an example of a conventional boundary scan register.

FIG. 4 is a configuration circuit diagram of another example of a conventional boundary scan register.

[Explanation of symbols]

 10, 24, 30 Boundary scan register 12, 18, 32 Multiplexer 14, 16 Flip-flop 20 Inverter 22 Input / output I / O cell 22a Input buffer 22b Output buffer 26 Input I / O cell 28 Internal circuit

Claims (1)

[Claims] In a semiconductor device provided with input / output I / O cells having an input buffer and an output buffer corresponding to each input terminal, a boundary provided corresponding to each input terminal of the semiconductor device. A scan register, comprising: a first multiplexer for selectively outputting either an input signal input from an input terminal of the semiconductor device via an input buffer of an input / output I / O cell or a scan-in signal; A first flip-flop that holds an output signal of the first multiplexer and outputs a scan-out signal, a second flip-flop that holds an output signal of the first flip-flop, and an input of the semiconductor device. An input signal input from a terminal via an input buffer of an input / output I / O cell, or an output signal of the second flip-flop. A second multiplexer for selectively outputting one of the output signals, and an inverter for inverting and outputting the output signal of the second multiplexer. The output of the boundary scan register (PO or P
O￣) is a boundary scan register which is inputted to an output buffer of the input / output I / O cell.