JPH11326456A - Test method and integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To conduct a test to an integrated circuit device in a high speed without using a tester. SOLUTION: In a test method of an integrated circuit device 1 having plural pins 6 and plural flip-flops 11 which are connected to the plural pins 6 and also connected respectively in series so as to compose a scan path 3 which performs a shift motion as a shift resister at the time of the test, following steps are established, namely, a step in which a test control circuit 5, by which a test using the scan path 3 is performed, is installed beforehand in the integrated circuit device 1 in the state where the test control circuit 5 is connected to the scan path 3, and a step in which the plural pins 6 are connected respectively by an external wiring 4, and also a step in which the test using the scan path 3 is performed by the test control circuit 5, by giving a test mode signal to the test control circuit 5 in the state where the plural pins 6 are connected respectively by the external wiring 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a technique for inspecting an integrated circuit device such as a package or a card designed to constitute a scan path as a device under test.

[0002]

2. Description of the Related Art Conventionally, a package or a card (integrated circuit device) produced by mounting an integrated circuit unit such as an IC or an LSI on a printed circuit board or a ceramic substrate is inspected as a device under test. A method of accessing an I / O (input / output) pin of a test object or a method of probing each node of a test object and accessing from a tester to perform a test, which is called an in-circuit test, is generally used. . In any of these methods, a tester requires an enormous number of pins (drivers / receivers) as the density of the device under test increases.

Further, as shown in FIG. 4, in order to facilitate inspection of the integrated DUT 1, an LSI of the DUT 1 is used.
A method is known in which the scan path 3 is configured using flip-flops (or latches) 11 originally provided as constituent elements of the scan path 3. That is, in this method, the scan path 3 is configured in advance by connecting the flip-flops (or latches) 11 of the LSI 2 of the device under test 1 serially so as to function as a shift register. Then, data is set to all flip-flops 11 bit by bit from the tester 10 via the scan-in pin of the scan path 3 by a shift operation, and then the shift operation is released. Subsequently, a normal clock CLK is supplied from the tester 10 connected to the I / O (input / output) pin 6 connected to the flip-flop 11 of the LSI 2 of the DUT 1 to the LSI 2 of the DUT 1. By operation,
Now send and receive data in the normal direction. The result data is again extracted one bit at a time from the scan-out pin of the scan path 3 by the shift operation, observed, and the result data is compared with an expected value by the tester 10 for inspection.

However, the operating speed at the time of the test is
It is practically impossible to test at high speed because it depends on the operation speed of the device.

[0005]

The first problem with the conventional method described with reference to FIG. 4 is that, with the increase in the density of the DUT 1, a very large number of pins (drivers / receivers) is expensive. That is, the tester 10 is required.

The reason is that a tester pin is connected to each of the pins 6 on a one-to-one basis with respect to the DUT 1 having a very large number of pins, and the test is performed.

A second problem with the conventional method described with reference to FIG. 4 is that it is difficult to perform a test while operating at high speed.

The reason is that the operation speed at the time of the test is limited by the operation speed of the tester 10.

An object of the present invention is to provide a method for testing an integrated circuit device (package or card) at high speed without using a tester.

Another object of the present invention is to provide an integrated circuit device (package or card) that can be tested at high speed without using a tester.

[0011]

According to the present invention, there is provided a test method for testing an integrated circuit device having a plurality of pins and a plurality of constituent elements connected to the plurality of pins, respectively. In the method of testing the integrated circuit devices in a state where the components are serially connected to each other to configure a scan path that performs a shift operation as a shift register during a test, a test control that performs a test using the scan path Providing a circuit unit in advance in the integrated circuit device in a state where the test control circuit unit is connected to the scan path; connecting the plurality of pins to each other via external wiring; A test mode signal to the test control circuit unit in a state where the pins of the test control circuit unit are connected to each other by the external wiring. , Testing method characterized by a step to perform a test using the scan path is obtained.

Further, according to the present invention, a substrate, a plurality of first pins mounted on the substrate, and a plurality of first structures mounted on the substrate and connected to the plurality of first pins, respectively. A first integrated circuit portion having an element, a plurality of second pins mounted on the substrate, and a plurality of second components mounted on the substrate and connected to the plurality of second pins, respectively. A test method for testing an integrated circuit device having a second integrated circuit unit, wherein the plurality of first constituent elements and the plurality of second constituent elements perform a shift operation as a shift register during a test. In the method of testing the integrated circuit devices serially connected to each other to configure a scan path, a test control circuit unit that performs a test using the scan path is provided on the substrate in advance. Mounting the test control circuit unit in a state connected to the scan path; connecting the plurality of first pins and the plurality of second pins to each other by a plurality of external wirings; In a state where the first pin and the plurality of second pins are connected to each other by the plurality of external wirings, a test mode signal is given to the test control circuit unit, and the scan path is provided to the test control circuit unit. Performing the used test.

Further, according to the present invention, there is provided an integrated circuit device having a plurality of pins and a plurality of constituent elements respectively connected to the plurality of pins, wherein the plurality of constituent elements are shifted as shift registers during a test. In the integrated circuit device, which is serially connected to each other to form a scan path for performing an operation, an external wiring connecting the plurality of pins to each other, and a test mode signal connected to the scan path, An integrated circuit device having a test control circuit unit for performing a test using a scan path is obtained.

Further, according to the present invention, a substrate, a plurality of first pins mounted on the substrate, and a plurality of first structures mounted on the substrate and connected to the plurality of first pins, respectively. A first integrated circuit portion having an element, a plurality of second pins mounted on the substrate, and a plurality of second components mounted on the substrate and connected to the plurality of second pins, respectively. A plurality of first constituent elements and the plurality of second constituent elements constitute a scan path that performs a shift operation as a shift register during a test. Therefore, in the integrated circuit device, which is serially connected to each other, the plurality of external wirings connecting the plurality of first pins and the plurality of second pins to each other, and the substrate is connected to the scan path. Condition It is implemented, when receiving a test mode signal, the integrated circuit device is obtained, characterized in that it comprises a test control circuit section for performing a test using the scan path.

The integrated circuit device is typically a package or a card having an integrated circuit unit (LSI or IC) having a flip-flop or a latch as a constituent element.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

Hereinafter, the case where the integrated circuit device is a package having an LSI having a flip-flop as a constituent element will be mainly described. However, a case where a latch is used as a constituent element or an IC is used instead of the LSI. When the integrated circuit device is a package, the same operation is performed.

According to the present invention, a test control circuit is provided in a device under test (ie, an integrated circuit device), and at the time of a test, the I / O signal of the device under test 1 is turned back and a high-speed test is performed without connecting to a tester. I do.

More specifically, a scan path is designed for a package or card to be tested, and I / O pins are connected at the time of testing. At this time, the connected I
The / O pins are selected and connected so as to have an input / output relationship in which data can be transmitted and received. In addition, the DUT
A test control circuit for controlling a scan path and executing a test pattern is provided. The test control circuit operates only by supplying power and setting the test mode for the device under test, and performs a test using a scan path.

The DUT has a scan path design. As for the connection between the LSIs, the data is transmitted and received by the scan path of each LSI and the inspection is performed as in the related art. I /
The O-pin is connected to the output pin and the input pin by a jig or the like in a 1: 1 connection or a 1: n (an integer of 2 or more) connection to perform the return wiring. The bidirectional pins are controlled so as to be arbitrarily fixed to input or output during testing. Since all I / O pins use one output data as the other input data, the tester does not need to drive / receive.

The test control circuit 5 has a function of storing test patterns and expected values prepared in advance by simulation or the like. When a test is started, the test control circuit 5 controls a scan path to perform a shift operation and set data. The test control circuit extracts again the result of data transmission / reception observed by the scan path by the shift operation, compares it with the expected value stored in advance, and outputs the result. Therefore, there is no need to input data, observe data, and compare expected values with a tester.

Since there is no need to connect to the tester, the operation speed during the test does not depend on the operation speed of the tester, and a high-speed inspection can be performed.

Referring to FIG. 1, a first embodiment of the present invention includes similar parts indicated by similar reference numerals. In this embodiment, the DUT (package as an integrated circuit device)
Reference numeral 1 denotes an LSI 2 having a scan path 3 incorporated therein and a test control circuit 5 for controlling the LSI 2. An I / O (input / output) pin 6 of the device under test has an output pin and an input pin in a 1: 1 ratio by a return wiring (external wiring) 4 provided outside.
Or they are connected at 1: n. The bidirectional pin is controlled by the test control circuit 5 so as to be arbitrarily fixed to an input or an output. In this way, all I
The / O pin 6 uses one output data as the other input data and does not drive / receive from the tester.

The test control circuit 5 starts a test in response to power-on and a test mode signal. The test control circuit 5 has a portion for storing test patterns and expected values prepared in advance by simulation or the like. When a test is started, the test control circuit 5 controls the scan path 3 to perform a shift operation, and Data is set in the flip-flop 11. When the data has been set, the dest control circuit 5 releases the shift operation of the scan path 3 and sets the L level.
A clock is supplied to SI2, and between flip-flops 11,
Data is transmitted and received between the LSIs 2. At this time, the signal connected to the I / O pin 6 changes the I / O pin from the output pin to the input pin.
Data is transmitted and received between pins.

The test control circuit 5 extracts the result of data transmission / reception observed by the scan path 3 again by the shift operation and compares it with the expected value prepared in advance.
Output the result.

Thus, a high-speed test can be performed without connecting to a tester.

Referring to FIG. 2, a second embodiment of the present invention includes similar parts indicated by similar reference numerals. In this embodiment, the DUT 1 includes an LSI 2 having a scan path 3 incorporated therein, and a test control circuit 5 for controlling the LSI 2 and performing a test on the DUT alone. I / of test sample 1
The 0 pin 6 is connected to the output pin and the input pin in a 1: 1 or 1: n (n is an integer of 2 or more) by a return wiring 4 provided outside. The bidirectional pins are controlled by the test control circuit 5 so as to be arbitrarily fixed to an input or an output. In this way, all I / O pins 6 use one output data as the other input data, and do not drive / receive from the tester.

Next, the function of each section will be described.

The test control circuit 5 includes, for example, a pattern memory unit 7 for storing a test pattern to be set in the scan path 3 during a test and an expected value for the test pattern. A comparator section 8 for comparing values and a control section 9 for controlling their operations
It is composed of When power is supplied to the DUT 1 and the test control circuit 5 is set to the test mode by the test mode signal, the test starts. The control unit 9 reads a test pattern from the pattern memory unit 7 and reads an LSI test mode signal (TST) or a scan mode control signal (SM).
C) to control the scan path 3 to shift,
Data is set in each flip-flop 11 constituting the scan path 3. When the data has been set, the control unit 9 releases the shift operation of the scan path 3, supplies a predetermined number of clocks (CLK) to the LSI 2, and sends and receives data between the flip-flops 11 via the return wiring 4. I do. In some cases, this operation may be repeated several times. At this time, the signal connected to the I / O pin 6 is transmitted and received between the I / O pin 6 via the return wiring 4 from the output pin to the input pin.

After data transmission / reception between the flip-flops 11, the control unit 9 extracts again the data transmission / reception result observed by the scan path 3 by the shift operation, and the result is stored in the pattern memory unit 7 in advance. The comparator 8 compares the expected value with the expected value and outputs the result.

In this way, a test at a speed close to the actual operation of the DUT 1 can be performed without connecting to the tester.

Referring to FIG. 3, a third embodiment of the present invention includes similar parts indicated by similar reference numerals. The feature of this embodiment is that the test control circuit 5 does not exist independently but is distributed and built in each LSI 2. In such a configuration, the test control circuit 5 must be built in each of the LSIs 2. However, it is not necessary to mount a component such as an LSI dedicated to the test, and the mounting density of the DUT 1 can be increased. There is an effect that can be.

[0033]

A first advantage of the present invention is that a test including I / O pins can be performed without using an expensive tester.

The reason is that the I / O pins are turned back and connected, and a test using a scan path is performed by a built-in test control circuit.

A second effect of the present invention is that a test object can be tested at a speed close to actual operation.

The reason is that the test is performed by the test control circuit of the DUT itself without connecting to the tester.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a second embodiment of the present invention.

FIG. 3 is a diagram for explaining a third embodiment of the present invention.

FIG. 4 is a diagram for explaining a conventional technique.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 device under test (integrated circuit device) 2 LSI 3 scan path 4 return wiring 5 test control circuit 6 I / O pin 7 pattern memory unit 8 comparator unit 9 control unit 10 tester 11 flip-flop (component element)

Claims (16)

[Claims] 1. A test method for testing an integrated circuit device having a plurality of pins and a plurality of components respectively connected to the plurality of pins, wherein the plurality of components are shifted as shift registers during a test. In a method of testing said integrated circuit devices serially connected to each other to form a scan path for performing an operation, a test control circuit unit for performing a test using said scan path is provided in advance of said integrated circuit device. Providing the test control circuit section in a state where the test control circuit section is connected to the scan path; connecting the plurality of pins to each other via external wiring; and connecting the plurality of pins to each other via the external wiring. In this state, a test mode signal is given to the test control circuit unit, and a test using the scan path is sent to the test control circuit unit. Performing a test. 2. The test method according to claim 1, wherein the integrated circuit device includes the plurality of pins and a plurality of flip-flops or a plurality of latches respectively connected to the plurality of pins as the plurality of components. A test method characterized by being a package or a card having the same. 3. A substrate, and a plurality of first substrates mounted on the substrate.
A first integrated circuit unit having a plurality of first constituent elements mounted on the board and connected to the plurality of first pins, respectively, and a plurality of second pins mounted on the board. A second component having a plurality of second components mounted on the substrate and connected to the plurality of second pins, respectively.
A test method for testing an integrated circuit device having an integrated circuit unit, wherein the plurality of first constituent elements and the plurality of second constituent elements perform a scan path that performs a shift operation as a shift register during a test. In the method for testing the integrated circuit devices serially connected to each other to configure, a test control circuit unit that performs a test using the scan path is provided on the substrate in advance, and the test control circuit unit Mounting in a state connected to the scan path; connecting the plurality of first pins and the plurality of second pins to each other with a plurality of external wirings; In a state where the plurality of second pins are connected to each other by the plurality of external wirings, a test mode signal is supplied to the test control circuit unit to perform the test control. The circuit portion, the test method characterized by a step to perform the test using the scan path. 4. The test method according to claim 3, wherein the first integrated circuit section includes a plurality of first flip-flops or a plurality of first latches respectively connected to the plurality of first pins. As the plurality of first constituent elements, and the second integrated circuit unit includes a plurality of second flip-flops or a plurality of second latches respectively connected to the plurality of second pins. A plurality of second constituent elements, wherein the integrated circuit device includes the plurality of first pins, the first integrated circuit unit, the plurality of second pins, and the second
A test method characterized by being a package or a card having an integrated circuit unit according to (1). 5. An integrated circuit device having a plurality of pins and a plurality of components connected to the plurality of pins, respectively, wherein the plurality of components perform a shift operation as a shift register during a test. The integrated circuit device serially connected to each other, wherein the external path connecting the plurality of pins to each other, and the test path signal is connected to the scan path. An integrated circuit device comprising: a test control circuit unit for performing a test. 6. The integrated circuit device according to claim 5, wherein the integrated circuit device includes the plurality of pins and a plurality of flip-flops or a plurality of latches respectively connected to the plurality of pins. An integrated circuit device, characterized in that it is a package having the following. 7. The integrated circuit device according to claim 5, wherein the test control circuit unit is connected to the pattern memory unit that stores a test pattern and an expected value pattern based on the test pattern in advance. Receiving the test mode signal, causing the scan path to perform the shift operation, setting the test pattern as data in the plurality of constituent elements of the scan path, and releasing the shift operation; A function of transmitting and receiving the data between the plurality of components via the external wiring, and causing the scan path to perform the shift operation again, and a result of transmitting and receiving the data from the plurality of components of the scan path. And a function of comparing the result of the data transmission and reception with the expected value pattern, and outputting the comparison result as a test result. An integrated circuit device comprising: a control and comparison unit having: 8. The integrated circuit device according to claim 7, wherein the integrated circuit device includes the plurality of pins and a plurality of flip-flops or a plurality of latches respectively connected to the plurality of pins. An integrated circuit device, characterized in that it is a package having the following. 9. A substrate, and a plurality of first substrates mounted on the substrate.
A first integrated circuit unit having a plurality of first constituent elements mounted on the board and connected to the plurality of first pins, respectively, and a plurality of second pins mounted on the board. A second component having a plurality of second components mounted on the substrate and connected to the plurality of second pins, respectively.
Wherein the plurality of first constituent elements and the plurality of second constituent elements are:
In the integrated circuit device, which is serially connected to each other so as to form a scan path that performs a shift operation as a shift register during a test, a plurality of external circuits that connect the plurality of first pins and the plurality of second pins to each other An integrated circuit device comprising: a wiring; and a test control circuit unit mounted on the substrate so as to be connected to the scan path, and performing a test using the scan path when receiving a test mode signal. . 10. The integrated circuit device according to claim 9, wherein the first integrated circuit section includes a plurality of first flip-flops or a plurality of first flip-flops respectively connected to the plurality of first pins. A plurality of second flip-flops or a plurality of second latches connected to the plurality of second pins, respectively, having a latch as the plurality of first constituent elements; The plurality of second constituent elements, wherein the integrated circuit device includes the plurality of first pins, the first integrated circuit unit, the plurality of second pins, and the second
An integrated circuit device, which is a package or a card having the integrated circuit unit of (1). 11. The integrated circuit device according to claim 9, wherein the test control circuit unit is connected to the pattern memory unit that stores a test pattern and an expected value pattern based on the test pattern in advance. Receiving the test mode signal, causing the scan path to perform the shift operation, and setting the test pattern as data in the plurality of first constituent elements and the plurality of second constituent elements of the scan path. A function of canceling the shift operation and transmitting and receiving the data between the plurality of first constituent elements and the plurality of second constituent elements via the plurality of external wirings. Causing the campus to perform the shift operation again to transmit and receive the data from the plurality of first constituent elements and the plurality of second constituent elements of the scan path. An integrated circuit device comprising: a control and comparison unit having a function of extracting a result and a function of comparing a result of data transmission / reception with the expected value pattern and outputting a comparison result as a test result. 12. The integrated circuit device according to claim 11, wherein the first integrated circuit section includes a plurality of first flip-flops or a plurality of first flip-flops respectively connected to the plurality of first pins. A plurality of second flip-flops or a plurality of second latches connected to the plurality of second pins, respectively, having a latch as the plurality of first constituent elements; The plurality of second constituent elements, wherein the integrated circuit device includes the plurality of first pins, the first integrated circuit unit, the plurality of second pins, and the second
An integrated circuit device, which is a package or a card having the integrated circuit unit of (1). 13. The integrated circuit device according to claim 9, wherein the test control circuit unit is mounted on the substrate in a distributed manner corresponding to the first and second integrated circuit units. And a second distributed test control circuit section. 14. The integrated circuit device according to claim 13, wherein the first integrated circuit section includes a plurality of first flip-flops or a plurality of first flip-flops respectively connected to the plurality of first pins. A plurality of second flip-flops or a plurality of second latches connected to the plurality of second pins, respectively, having a latch as the plurality of first constituent elements; The plurality of second constituent elements, wherein the integrated circuit device includes the plurality of first pins, the first integrated circuit unit, the plurality of second pins, and the second
An integrated circuit device, which is a package or a card having the integrated circuit unit of (1). 15. The integrated circuit device according to claim 13, wherein the first and second distributed test control circuit units are incorporated in the first and second integrated circuit units. Integrated circuit device. 16. The integrated circuit device according to claim 15, wherein the first integrated circuit section includes a plurality of first flip-flops or a plurality of first flip-flops respectively connected to the plurality of first pins. A plurality of second flip-flops or a plurality of second latches connected to the plurality of second pins, respectively, having a latch as the plurality of first constituent elements; The plurality of second constituent elements, wherein the integrated circuit device includes the plurality of first pins, the first integrated circuit unit, the plurality of second pins, and the second
An integrated circuit device, which is a package or a card having the integrated circuit unit of (1).