CN103809104B - Scan clock generator and method for generating scan clock - Google Patents

Abstract

The invention discloses a scanning clock generator and a scanning clock generation method, which are used for providing a plurality of on-chip scanning clocks required by testing a plurality of elements to be tested, and the scanning clock generator comprises: a receiving circuit for receiving an off-chip scan clock; and a clock processing circuit, coupled to the receiving circuit, for generating the plurality of on-chip scanning clocks according to the received off-chip scanning clock; wherein the clock edges of the scan clocks in the chips are staggered, and the scan clock generator and the plurality of devices to be tested are arranged in the same chip. The scanning clock generator can reduce the condition that pins are occupied because a chip needs a plurality of scanning clocks to input in a scanning test mode, and can generate a plurality of groups of internal scanning clocks with different phases to achieve the purpose of reducing the instantaneous test power.

Description

Scan clock generator and method for generating scan clock

technical field

The embodiments disclosed in the present invention relate to the generation of scan clocks, in particular to a scan clock generator capable of generating multiple scan clocks and related methods.

Background technique

Scan test has excellent detection ability for process defects, and can provide an accurate and single scoring number regardless of circuit size or function, so scan test has become an indispensable part of chip mass production test important indicators. However, in order to shorten the test time, the scan test usually allows the circuit to be triggered (toggle) as much as possible on the machine, hoping to detect the largest part of the circuit in the least time. Therefore, the test power consumption (test power) It is often much greater than the energy consumption during normal operation of the circuit. In severe cases, the excessive current may cause the chip to burn or cause test over-kill. In order to avoid such disadvantages, the circuit is traditionally divided into several smaller blocks, each block has its own independent scan clock, and each scan clock will not be started at the same time during the test, but have a relationship with each other. Phase skew, in other words, the clock edges of each scan clock are staggered from each other during testing. This approach effectively solves the problem of excessive power consumption in testing. However, as the circuit complexity increases, the circuit size also continues to grow. Therefore, the circuit under test in a chip under test needs to be finely divided into more cells. Block, which means that more scan clock signals provided by the test machine are required to be input from the scan clock input port of the chip to the internal circuit. However, the number of pins (pins) after the chip is packaged and the number of signals that the test machine can provide are different. is fixed, so the continuously growing number of scan clock signals will face the problem of insufficient pins (or test signals).

Considering the above requirements, an innovative design is needed to effectively reduce the number of chip pins (or test signals) required for scan testing by using simple on-chip circuits.

Contents of the invention

One of the objectives of the present invention is to provide a scan clock generator capable of generating multiple scan clocks and a related method to solve the above problems.

According to the first embodiment of the present invention, a scan clock generator is disclosed, which is used to provide a plurality of on-chip scan clocks required for testing a plurality of DUTs. The scan clock generator includes a receiving circuit for to receive an off-chip scan clock; and a clock processing circuit, coupled to the receiving circuit, for generating the plurality of on-chip scan clocks according to the received off-chip scan clock; wherein the plurality of chips The clock edges of the internal scan clocks are staggered from each other, and the scan clock generator and the plurality of DUTs are arranged in the same chip.

According to the second embodiment of the present invention, a scan clock generation method for providing a plurality of on-chip scan clocks required for testing a plurality of DUTs is disclosed, including receiving an off-chip scan clock; and according to The received off-chip scan clocks are used to generate the plurality of on-chip scan clocks; wherein the clock edges of the plurality of on-chip scan clocks are staggered from each other.

By adopting the scan clock generator and the scan clock generation method proposed by the present invention, an external scan clock input from a chip can be used to generate multiple groups of multiple internal scan clocks with different phases, reducing the number of chips in the chip. In the scan test mode, pins are occupied due to the need for multiple scan clock inputs, and the scan clock generator of the present invention can generate multiple sets of internal scan clocks with different phases to reduce the instantaneous test power.

Description of drawings

FIG. 1 is a structural diagram of a first exemplary embodiment of a scan clock generator of the present invention.

FIG. 2 is a structural diagram of a second exemplary embodiment of the scan clock generator of the present invention.

FIG. 3 is a structural diagram of a third exemplary embodiment of the scan clock generator of the present invention.

FIG. 4 is a schematic diagram of an embodiment of the clock switching circuit shown in FIG. 3 .

FIG. 5 is a circuit diagram of an embodiment of the controller shown in FIG. 4 .

Wherein, the reference signs are explained as follows:

100, 200, 300 scan clock generator

102, 202, 302 chips

104 receiving circuit

106, 206, 306 clock processing circuit

108_1~108_M delay circuit

110, 210 Controller

111 triggers

112_1~112_M scan clock domain

208_1~208_M, 308_1~308_M delay elements

310 clock switching circuit

312 controller

314 decoder

502, 504, 506 selectors

508, 510, 512 flip flops

detailed description

Please refer to FIG. 1 , which is a structural diagram of a first exemplary embodiment of a scan clock generator of the present invention. In this exemplary embodiment, the scan clock generator 100 includes a receiving circuit 104 and a clock processing circuit 106 coupled to the receiving circuit 104, wherein the receiving circuit 104 is used to receive an off-chip scan time pulse _{sclk off_chip} and output the scan clock sclk to the clock processing circuit 106 , for example, one or more buffers/inverters are set in the receiving circuit 104 . In this embodiment, the clock processing circuit 106 can generate multiple on-chip scan clocks sclk ₁ , sclk ₂ , . . . , sclk _M according to the scan clock sclk. In addition, preferably, these chips The clock edges of the internal scan clocks sclk ₁ , _{sclk 2} , . ,..., 112_M scan test clock. In other words, a plurality of on-chip scan clocks sclk ₁ , _{sclk 2} , . Not intended to limit the scope of the present invention), the plurality of DUTs may include a plurality of flip flops 111 . In addition, the scan clock generator 100 and the plurality of scan clock domains are disposed in the same chip 102 , more specifically, the scan clock generator 100 and the plurality of DUTs are disposed in the same chip 102 .

Regarding the clock processing circuit 106, it includes a controller 110 and a plurality of delay circuits 108_1, 108_2, . to generate M delay control signals S _CTR1 , S _CTR2 , . . _. Signals S _CTR1 , S _CTR2 , ..., S _CTRM to add corresponding multiple delays to the scan clock sclk, and obtain the final desired value between multiple scan clocks in subsequent multiple scan clock domains In other words, the delay circuits 108_1, 108_2, . pulse.

It should be noted that, in this exemplary embodiment, in order to achieve the purpose of saving the input and output ports (I/O ports) of the chip 102 at the same time, the control data sequence input d_in of the controller 110 is serially (serial) Input, together with the input control signal hold and scan clock sclk as the basis for the controller 110 to identify the control data sequence input d_in, more specifically, the user can use the control data sequence input d_in from outside the chip to arbitrarily set the delay circuit Delay time/delay amount for 108_1, 108_2, ..., 108_M. However, the input method of the controller 110 is only illustrated here as an example, and is not a limitation of the present invention. Any design capable of achieving similar functions falls within the scope of the present invention.

Please refer to FIG. 2 , which is a structural diagram of a second exemplary embodiment of the scan clock generator of the present invention. In this exemplary embodiment, the scan clock generator 200 includes the aforementioned receiver 104 and a clock processing circuit 206, wherein the receiver circuit 104 is used to receive an off-chip scan clock _{sclk off_chip} and output the scan clock sclk off_chip The pulse processing circuit 206, so that the clock processing circuit 206 can generate a plurality of on-chip scanning clocks sclk ₁ , sclk ₂ , ..., sclk _M according to the scanning clock sclk, related to the on-chip scanning clocks sclk ₁ , sclk ₂ , . . . , _sclkM and the operations and concepts among the subsequent multiple scan clock domains 112_1, 112_2, . It should be noted that the scan clock generator 200 and the multiple scan clock domains 112_1, 112_2, . in the same chip.

Regarding the clock processing circuit 206, it includes a controller 210 and a plurality of delay elements 208_1, 208_2, . hold to generate M delay control signals S _CTR1 , S _CTR2 , . . _. , ..., 208_M are composed in series, that is to say, the output end of the delay element 208_1 is coupled to the input end of the delay element 208_2 of the next stage, and the output end of the delay element 208_2 is coupled to the delay element of the next stage The input terminal of 208_3, the connection mode of subsequent delay elements can be deduced by analogy. In this way, the delay elements 208_1 , 208_2 , . . . , _{208_M} can add corresponding delays to the scan clock sclk according to the delay control signals S _CTR1 , S _CTR2 , . . . , S CTRM . For example, based on sclk, the delay time of the scan clock sclk ₁ compared to sclk is the delay time caused by the delay element 208_1, and the delay time of the scan clock sclk ₂ compared to sclk is the delay element The sum of the delay times caused by 208_1 and delay elements 208_2, and so on, so the delay time of the last scan clock sclk _M compared to sclk is the sum of the delay times caused by delay elements 208_1, 208_2, . . . , 208_M . In other words, the delay elements 208_1 , 208_2 , . . . , 208_M sequentially delay the received off-chip scan clocks (ie, sclk) in series to generate desired on-chip scan clocks respectively. In addition, the operation process of the controller 210 is the same as that of the aforementioned exemplary embodiment, and will not be repeated here.

Please refer to FIG. 3 , which is a structural diagram of a third exemplary embodiment of the scan clock generator of the present invention. In this exemplary embodiment, the scan clock generator 300 includes the aforementioned receiver 104 and a clock processing circuit 306, wherein the receiver circuit 104 is used to receive an off-chip scan clock _{sclk off_chip} and output the scan clock sclk to The clock processing circuit 306, so that the clock processing circuit 306 can generate a plurality of on-chip scanning clocks sclk ₁ , sclk ₂ , ..., sclk _M according to the scanning clock sclk, related to the on-chip scanning clocks sclk ₁ , sclk ₂ , . . . , _sclkM and the operations and concepts among the subsequent multiple scan clock domains 112_1, 112_2, . It should be noted that the scan clock generator 300 and the multiple scan clock domains 112_1, 112_2, . set in the same chip.

Regarding the clock processing circuit 306, it includes a clock switching circuit 310 and a plurality of delay elements _{308_1} , _{308_2} , . . . ', ..., sclk _M ' are respectively input to the clock switching circuit 310, please note that in this exemplary embodiment, the delay elements 308_1, 308_2, ..., 308_M are composed in series, that is to say, the delay elements The output terminal of 308_1 is coupled to the input terminal of the delay element 308_2 of the next stage, the output terminal of the delay element 308_2 is coupled to the input terminal of the delay element 308_3 of the next stage, and the connection of the subsequent delay elements is analogous. In addition, the clock switching circuit 310 will switch the scan clocks sclk ₁ ′, sclk ₂ ′ input by the delay elements 308_1, 308_2, . . . , 308_M according to the scan clock sclk, a control data sequence input d_in, and an input control signal hold , ..., sclk _M ' switch in the corresponding order, and further output the scan clocks sclk ₁ ', sclk ₂ ', ..., sclk _M ' in a new order as the on-chip scan clocks sclk ₁ , sclk ₂ ,..., sclk _M , in this way, the scan clock settings of the subsequent multiple scan clock domains 112_1, 112_2,..., 112_M can be changed through the scan clock sclk, the control data sequence input d_in, and the input control signal hold , that is to say, the user can reset the phase relationship between the scan clocks of the DUT from outside the chip.

FIG. 4 is a schematic diagram of an embodiment of the clock switching circuit 310 shown in FIG. 3 . The clock switching circuit 310 includes a controller 312 and a decoder 314, wherein the controller 312 reads the externally input control data sequence input d_in according to the scan clock sclk and the input control signal hold, and converts it into control data parallel Output d_out0, d_out1, ..., d_outM to the decoder 314 as a basis for changing the order of sclk ₁ ', sclk ₂ ', ..., sclk _M ' to sclk ₁ , sclk ₂ , ..., sclk _M. Please refer to FIG. 5 , which is a circuit diagram of an embodiment of the controller 312 shown in FIG. 4 . The controller 312 includes a plurality of selectors (selectors/multiplexers) 502, 504, 506 for switching inputs according to the input control signal hold, and a plurality of flip-flops (such as D-type flip-flops) 508 driven by the scan clock sclk , 510, 512, when the control signal hold decreases from 1 to 0, a first bit of the control data sequence input d_in will be input to the flip-flop 508 and stored therein, until the next clock, the first bit will be Input to the flip-flop 510 and stored therein, and a second bit of the control data sequence input d_in will be input to the flip-flop 508 and stored therein, and so on, when the next clock starts, the control data sequence input d_in The first bit is stored in the flip-flop 512 , the second bit of the control data sequence input d_in is stored in the flip-flop 510 , and the third bit of the control data sequence input d_in is stored in the flip-flop 508 . In addition, at this time, the control signal hold will rise from 0 to 1 to keep the stored results in the flip-flops 508-512 until the next time a new control data sequence input d_in needs to be written. The architecture and the number of bits of the controller 312 are only used as examples here, and are not limitations of the present invention. The number of bits can be determined according to the numbers in the scan clock domain. Regarding the design of the architecture, any similar function can be achieved. The practices all belong to the scope covered by the present invention.

In summary, by using the scan clock generator and the scan clock generation method proposed by the present invention, an external scan clock input from a chip can be used to generate multiple sets of multiple internal scan clocks with different phases. Pulse, to reduce the situation that the pins are occupied due to the need for multiple scan clock inputs in the scan test mode of the chip. At the same time, the scan clock generator of the present invention can generate multiple sets of internal scan clocks with different phases, which can also reduce the instantaneous Purpose of testing power.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the patent claims of the present invention shall fall within the scope of the present invention.

Claims (18)

1. a kind of scanning clock pulse generator, scans seasonal pulse in order to provide in the multiple chips tested needed for multiple element under tests, should Scanning clock pulse generator includes：

One receiving circuit, scans seasonal pulse for receiving outside a chip；And

One seasonal pulse process circuit, is coupled to this receiving circuit, for producing this according to scanning seasonal pulse outside this chip being received Scanning seasonal pulse in multiple chips；

In wherein the plurality of chip, the seasonal pulse edge of scanning seasonal pulse offsets one from another, and this scanning clock pulse generator is to be measured with the plurality of Element is arranged in same chip.

2. scanning clock pulse generator as claimed in claim 1, wherein this seasonal pulse process circuit include：

Multiple delay circuits, in order to postpone respectively to scan seasonal pulse outside this chip being received, to produce scanning in the plurality of chip Seasonal pulse.

3. scanning clock pulse generator as claimed in claim 2, wherein this seasonal pulse process circuit have additionally comprised：

One controller, is coupled to the plurality of delay circuit, in order to adjust a retardation of each delay circuit.

4. scanning clock pulse generator as claimed in claim 3, wherein this controller receive a control data sequence, an input control Scan seasonal pulse outside signal processed and this chip, and sweep according to outside this control data sequence, this input control signal and this chip Retouch seasonal pulse and produce this delay that multiple delayed control signals are separately input into the plurality of delay circuit each delay circuit of adjustment Amount.

5. scanning clock pulse generator as claimed in claim 1, wherein this seasonal pulse process circuit include：

One delay circuit, in order to postpone to scan seasonal pulse outside this chip being received, wherein this delay circuit includes multiple concatenations Delay element, in order to produce in the plurality of chip scanning seasonal pulse respectively.

6. scanning clock pulse generator as claimed in claim 5, wherein this seasonal pulse process circuit have additionally comprised：

One controller, is coupled to the delay element of the plurality of concatenation, in order to adjust a retardation of each delay element.

7. scanning clock pulse generator as claimed in claim 6, wherein this controller receive a control data sequence, an input control Scan seasonal pulse outside signal processed and this chip, and sweep according to outside this control data sequence, this input control signal and this chip Retouch seasonal pulse and produce multiple delayed control signals and be separately input into the delay element of the plurality of concatenation and adjust each delay element This retardation.

8. scanning clock pulse generator as claimed in claim 5, wherein this seasonal pulse process circuit have additionally comprised：

One seasonal pulse switching circuit, is connected with the pairing between the plurality of element under test for switching scanning seasonal pulse in the plurality of chip Mode.

9. scanning clock pulse generator as claimed in claim 8, wherein this seasonal pulse switching circuit receive a control data sequence, one Seasonal pulse is scanned outside input control signal and this chip, and according to this control data sequence, this input control signal and this core Outside piece, scanning seasonal pulse adjusts the pairing connected mode between scanning seasonal pulse and the plurality of element under test in the plurality of chip.

10. scanning clock pulse generator as claimed in claim 9, wherein this seasonal pulse switching circuit comprise：

One controller, for producing a control signal；And

One decoder, is coupled to this controller and the plurality of delay element concatenating, to adjust this in order to decode this control signal Pairing connected mode between scanning seasonal pulse and the plurality of element under test in multiple chips.

11. scanning clock pulse generators as claimed in claim 10, wherein this controller receive multiple control bits, and foundation should Multiple control bits are producing this control signal；And the plurality of control bit by sequence transmission in the way of input this controller.

12. scanning clock pulse generators as claimed in claim 11, wherein controller include to be cut according to this input control signal Change multiple selectores of input and driven and the multiple triggerings corresponding with the plurality of selector by scanning seasonal pulse outside this chip Device.

A kind of 13. scanning seasonal pulse generation sides in order to provide scanning seasonal pulse in the multiple chips tested needed for multiple element under tests Method, includes：

Receive and scan seasonal pulse outside a chip；And

Scanning seasonal pulse in the plurality of chip is produced according to scanning seasonal pulse outside this chip being received；

In wherein the plurality of chip, the seasonal pulse edge of scanning seasonal pulse offsets one from another.

14. scanning clock pulse generation methods as claimed in claim 13, wherein according to outside this chip being received scanning seasonal pulse The step producing scanning seasonal pulse in the plurality of chip includes：

Individually to postpone to scan seasonal pulse, to produce the plurality of chip respectively outside this chip of being received in the way of parallel processing Interior scanning seasonal pulse.

15. scanning clock pulse generation methods as claimed in claim 13, wherein according to outside this chip being received scanning seasonal pulse The step producing scanning seasonal pulse in the plurality of chip includes：

To postpone in order to scan seasonal pulse outside this chip of being received with tandem, to produce scanning in the plurality of chip respectively Seasonal pulse.

16. scanning clock pulse generation methods as claimed in claim 15, wherein according to outside this chip being received scanning seasonal pulse The step producing scanning seasonal pulse in the plurality of chip has additionally comprised：

Switch the pairing connected mode between scanning seasonal pulse and the plurality of element under test in the plurality of chip.

17. scanning clock pulse generation methods as claimed in claim 16, wherein switch scanning seasonal pulse in the plurality of chip many with this The step of the pairing connected mode between individual element under test includes：

Produce a control signal；And

Decode this control signal to adjust the pairing connection side between scanning seasonal pulse and the plurality of element under test in the plurality of chip Formula.

18. scanning clock pulse generation methods as claimed in claim 17, the step wherein producing this control signal comprises：

Receive the multiple control bits being inputted in the way of sequence transmission；And

To produce this control signal according to the plurality of control bit.