CN106896317A - By circuit misarrangement method and circuit debuggers performed by the scan chain of sweep test - Google Patents
By circuit misarrangement method and circuit debuggers performed by the scan chain of sweep test Download PDFInfo
- Publication number
- CN106896317A CN106896317A CN201610820540.3A CN201610820540A CN106896317A CN 106896317 A CN106896317 A CN 106896317A CN 201610820540 A CN201610820540 A CN 201610820540A CN 106896317 A CN106896317 A CN 106896317A
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- Prior art keywords
- circuit
- misarrangement
- judged result
- particular electrical
- electrical circuit
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/302—Contactless testing
- G01R31/303—Contactless testing of integrated circuits
Abstract
The disclosure provides the circuit misarrangement method and circuit debuggers performed by a kind of scan chain by sweep test.Wherein, misarrangement method is included：Using a mode of operation and one judged result of generation of the particular electrical circuit of a misarrangement circuit judges one；The judged result is stored by the register on one scan chain path, wherein the scan chain pathway is used to perform one scan test；And the judged result is exported by the output connection gasket in the scan chain pathway, wherein the judged result is used for being observed carries out misarrangement with to the particular electrical circuit.The misarrangement method that the disclosure is provided can save a large amount of output pads to save manufacturing cost.
Description
Technical field
This disclosure relates to ic test technique field, in particular to a kind of one scan by sweep test
A circuit misarrangement method and a circuit debuggers performed by chain.
Background technology
In integrated circuit testing field, because the holding wire of numeral or Analogous Integrated Electronic Circuits is large number of, therefore even
In the quantity control of connection pad (Pad) always for IC design one it is great consider, and misarrangement (debug) is while also for integrated
The very important link of circuit test, traditionally, to carry out misarrangement for a certain particular electrical circuit, for example, if in one
Above there is any discrepancy, it is necessary to right with design the frequency that a phase-locked loop (phase lock loop, PLL) is shaken in integrated circuit
When this frequency is observed, the frequency signal that phase-locked loop can be made to shake generation in the prior art passes through again into a frequency eliminator
Observed to carry out misarrangement by user after the output of one connection gasket, consequently, it is possible to carry out misarrangement to multiple particular electrical circuits, it will
Substantial amounts of connection gasket is consumed, the increase of production cost is caused.
The content of the invention
The first purpose of the disclosure is to provide the circuit misarrangement performed by a kind of one scan chain by sweep test
Method and a circuit debuggers.
According to the embodiment of the disclosure one, a kind of circuit misarrangement method is disclosed, wherein the method is included：Using a misarrangement circuit
Judge a mode of operation of a particular electrical circuit and produce a judged result；By on one scan chain (scan chain) path
Register stores the judged result, and wherein the scan chain pathway is used to perform one scan test (scan test)；And by this
In scan chain pathway one exports connection gasket (Pad) to export the judged result, and wherein the judged result is used for observed with right
The particular electrical circuit carries out misarrangement.
According to the embodiment of the disclosure one, a kind of circuit debuggers is disclosed, the wherein system is included：One particular electrical circuit, one
Misarrangement circuit, a register and an output connection gasket.The misarrangement circuit is used to judge a mode of operation of the particular electrical circuit simultaneously
Produce a judged result；The register is used to store the judged result, and the wherein register-bit is in being used to perform one scan test
On one scan chain (Scan chain) path of (scan test)；And the connection gasket (pad) is used to export the judged result, its
In the connection gasket be contained in the sweep test, and the judged result is used for observed carrying out misarrangement with to the particular electrical circuit.
Brief description of the drawings
Fig. 1 is the schematic diagram in the sweep test region according to prior art.
Fig. 2 is the circuit debuggers schematic diagram according to the embodiment of the disclosure one.
Fig. 3 is the circuit debuggers schematic diagram according to another embodiment of the disclosure.
Fig. 4 is the test environment schematic diagram of the application circuit debuggers according to the embodiment of the disclosure one.
Fig. 5 is the test environment schematic diagram of the application circuit debuggers according to another embodiment of the disclosure.
Description of reference numerals：
111st, 112,113 combinational circuit
121st, 122,123 multiplexer
131st, 132,304 register
N1, N2 end points
100th, 210,310,511,512 sweep test region
CS control signals
201st, 301,401,501,503 particular electrical circuit
202nd, 302,402,502,504 misarrangement circuit
203rd, 303 misarrangement multiplexer
DR judged results
DRS misarrangement control signals
200th, 300 circuit debuggers
400th, 500 test environment
410th, 510 scan test system
420th, 520 output connection gasket
430th, 530 test equipment
Specific embodiment
Some vocabulary have been used in the middle of specification and claim to censure specific element.Technology people in art
Member is, it is to be appreciated that hardware manufacturer may call same element with different nouns.This specification and claims are simultaneously
Not in the way of the difference of title is used as distinguishing element, but the difference with element functionally is used as the criterion distinguished.
In the whole text, the "comprising" of specification and claim mentioned in is an open term, therefore should be construed to " include but not
It is defined in ".Additionally, " coupling " one word herein comprising it is any directly and indirectly electrical connection, therefore, if one described in text
First device is coupled to a second device, then representing the first device can directly be electrically connected in the second device, or pass through
Other devices or connection means are electrically connected to the second device indirectly.
Fig. 1 is the schematic diagram in sweep test (scan test) region 100 according to prior art, as shown in figure 1, one passes
Include combinational circuit 111,112 and 113 in system sweep test region 100, multiplexer 121,122 and 123 and register 131 and
132, wherein combinational circuit 111,112 and 113 is not restricted to any kind of numeral or analog circuit, register 131 and 132
Do not limit its circuit species equally, can be D flip-flop (D Flip Flop) or toggle flip-flop etc., and shown in Fig. 1
Each arrow simultaneously not only represents a signal, can be one or more signals, and such as combinational circuit 111 exports two output letters
Number to multiplexer 121, technical staff should be able to be readily appreciated that these circuit implementations in scan test field, and the disclosure is answered
Misarrangement method is overweighted, therefore the details on the circuit in sweep test region 100 will be omitted to save length herein.Traditionally,
Control signal CS control multiplexers 121,122 and 123 operate in immigration (shift-in), catch (capture) and remove
(shift-out) pattern, when multiplexer 121,122 and 123 operates in immigration pattern, multiplexer 121,122 with 123 and post
Storage 131 and 132 forms one scan chain (scan chain) path, it should be noted that, sweep test region 100 does not represent
Entire scan test system, can be solely the part in scan test system, that is, may coupling before combinational circuit 111
In the exit point N1 in another sweep test region, and another sweep test region input may be coupled to after multiplexer 123
End points N2.
Fig. 2 is the schematic diagram of circuit debuggers 200 according to the embodiment of the disclosure one, as shown in Fig. 2 circuit debuggers
200 treat with the misarrangement circuit 202 of particular electrical circuit 201 and of misarrangement comprising one scan test zone 210, wherein scanning is surveyed
Examination region 210 has additionally comprised a misarrangement multiplexer in addition to containing the element in the sweep test region 100 shown in Fig. 1
203；Particular electrical circuit 201 is a phase-locked loop (Phase Lock Loop, PLL) circuit, however, specific in other embodiments
Circuit 201 can be a static RAM (Static Random Access Memory, SRAM), a low voltage difference
Linear voltage regulator (Low Dropout Linear Regulator, LDO) or a flash memory (flashmemory), that is,
One limitation of the circuit framework of the particular electrical circuit 201 not disclosure.Misarrangement circuit 202 is used to detect a behaviour of particular electrical circuit 201
Make state OS and produce a judged result DR, for example, when particular electrical circuit 201 is a phase-locked loop, mode of operation OS can
Be particular electrical circuit 201 concussion produce a frequency, and misarrangement circuit 202 receive the frequency after judge the frequency whether with set
Meter is consistent, and produces judged result DR, and wherein judged result DR is a logical value, if judged result DR is logical value 1, is represented
Frequency is correct, if judged result DR is logical value 0, represents frequency errors；For another example, mode of operation OS can be
The shake (Jitter) of phase-locked loop, and misarrangement circuit 202 judges whether the resolution ratio of the shake is more than after receiving wobble information
One preset value, if it is logical value 1 then to produce judged result DR, it is logical value 0 otherwise to produce judged result DR；Should be noted
It is that the judged result DR produced by misarrangement circuit 202 is not intended to be limited to the logical value of single bit, also can is patrolling for multiple bits
Collect value, for example, judged result DR can be 00,01,10 and 11, and various logic value represents particular electrical circuit 201 not
Biconditional operation state, for example, 00 is duty cycle error, 01 is frequency errors etc., and the change in these designs should all be under the jurisdiction of
The category of the disclosure.Misarrangement multiplexer 203 is used to receive judged result DR, and controls to arrange by a misarrangement control signal DRS
Wrong multiplexer 203 operates in a misarrangement pattern, and when the misarrangement pattern is operated in, misarrangement multiplexer 203 will determine that result DR is deposited
Enter in register 132, then, when multiplexer 121,122 and 123 operates in removal pattern, will determine that result DR from register
The output connection gasket (Pad) (being not depicted in Fig. 2) at rear is sent in 132, for user in can be direct on tester table
Judged result DR is to carry out misarrangement for observation.It is noted that when misarrangement multiplexer 203 not operates in misarrangement pattern, will
With multiplexer 121,122 with 123 synchronously operated, that is, misarrangement multiplexer have no effect on normal scan test operation, when
When multiplexer 121,122 and 123 operates in immigration pattern, the same output signal by multiplexer 122 of misarrangement multiplexer 203 is transmitted
Into register 132.
Fig. 3 is the schematic diagram of circuit debuggers 300 according to another embodiment of the disclosure, as shown in figure 3, circuit misarrangement system
System 300 includes one scan test zone 310, particular electrical circuit 301, misarrangement circuit 302, and wherein sweep test region 310 is except bag
Contain outside the element in sweep test region 100 shown in Fig. 1, additionally comprised the register 304 of misarrangement multiplexer 303 and,
The wherein purpose and function of particular electrical circuit 301, misarrangement circuit 302 and misarrangement multiplexer 303 and phase described by Fig. 2 embodiments
Together, its details is omitted herein, and Fig. 3 embodiments are with the difference of Fig. 2 embodiments, the path of the scan chain of Fig. 3 embodiments
Upper use misarrangement multiplexer 303 stores judged result DR, wherein misarrangement multiplexer 303 with register 304 not with register 304
A part for original scan test system, that is, misarrangement multiplexer 303 has no effect on any combinations circuit with register 304, only
Only store and transmit used by judged result DR, it is different from the register in the shared scan chain pathway in Fig. 2 embodiments.
After reading above-described embodiment, those skilled in the art should be able to be readily appreciated that the detailed operation of the embodiment shown in Fig. 3, therefore
Detailed description is omitted herein.
Fig. 4 is the test environment schematic diagram of the application circuit debuggers 400 according to the embodiment of the disclosure one, such as Fig. 4 institutes
Show, can be comprising multiple sweep tests region (in figure shown in dotted line), such as sweep test region 210 in scan test system 410
Or 310, after misarrangement circuit 402 judges the mode of operation DR of particular electrical circuit 401, will determine that result DR is sent to and be contained in scanning survey
Misarrangement multiplexer (being not depicted in Fig. 4) in examination region, in the present embodiment, misarrangement multiplexer can will determine that result DR is passed
The exclusive register of as shown in Figure 3 one is delivered to, in the register also or on former scanning pattern as shown in Figure 2, Zhi Houtong
Removal pattern is crossed, will determine that result DR is exported to being coupled to the output connection gasket 420 of a test equipment 430, then led to by user
Cross test equipment 430 and observe judged result DR to carry out misarrangement.It is noted that one scan test system is not simply possible to use in sight
Examine the mode of operation of single particular electrical circuit to carry out misarrangement, Fig. 5 is the application circuit debuggers according to the embodiment of the disclosure one
500 test environment schematic diagram, as shown in figure 5, one scan test system 510 can observe multiple particular electrical circuits (in this implementation
It is particular electrical circuit 501 and mode of operation 503) in example, (is then specific in this embodiment via corresponding misarrangement circuit
Circuit 502 and 504) respective judged result DR1 and DR2 be sent in sweep test region 511,512, and by above-mentioned reality
The operation for applying example will determine that result DR1 and DR2 is exported to an output connection gasket 520, wherein output connection gasket 520 is coupled to a survey
Examination equipment 530, then judged result DR1 and DR2 is observed by test equipment 530 by user enter with 503 with to particular electrical circuit 501
Row misarrangement.
Simple to conclude the disclosure, the disclosure proposes a circuit debuggers and method, by the scan chain in scanning pattern
Exporting the mode of operation of particular electrical circuit can save a large amount of output pads to carry out misarrangement, thus to save manufacturing cost.
The foregoing is only the preferred embodiment of the disclosure, all impartial changes done according to disclosure claim with repair
Decorations, should all belong to the covering scope of the disclosure.
Claims (10)
1. a kind of circuit misarrangement method, it is characterised in that include：
Using a mode of operation and one judged result of generation of the particular electrical circuit of a misarrangement circuit judges one；
The judged result is stored by the register on one scan chain path, wherein the scan chain pathway is used to perform one scan
Test；And
The judged result is exported by an output connection gasket, wherein the judged result is used for being observed to enter with to the particular electrical circuit
Row misarrangement.
2. circuit misarrangement method as claimed in claim 1, additionally comprises：
A multiplexer is controlled to be stored to the register with by the judged result into a misarrangement pattern, wherein the one of the multiplexer is defeated
Enter to be coupled to the misarrangement circuit.
3. circuit misarrangement method as claimed in claim 1, the wherein particular electrical circuit are a phase-locked loop.
4. circuit misarrangement method as claimed in claim 3, wherein mode of operation of the particular electrical circuit is the phase-locked loop institute
The frequency for producing, the misarrangement circuit produces the judged result to determine whether the phase-locked loop is normally run according to the frequency.
5. circuit misarrangement method as claimed in claim 3, wherein mode of operation of the particular electrical circuit is the phase-locked loop institute
The shake for producing, the misarrangement circuit produces the judged result to determine whether the phase-locked loop is normally run according to the shake.
6. circuit misarrangement method as claimed in claim 1, the wherein particular electrical circuit are a static RAM, low
Pressure difference linear voltage regulator or a flash memory.
7. a kind of circuit debuggers, it is characterised in that include：
One particular electrical circuit；
One misarrangement circuit, is used to judge a mode of operation of the particular electrical circuit and produces a judged result；
One register, is used to store the judged result, and wherein the register-bit is in the one scan chain for being used to perform one scan test
On path；And
One output connection gasket, is used to export the judged result, and wherein the judged result is used for being observed to enter with to the particular electrical circuit
Row misarrangement.
8. circuit debuggers as claimed in claim 7, additionally comprises：
One multiplexer, controls the multiplexer to be posted so that the judged result is stored to this into a misarrangement pattern by a control signal
One input of storage, the wherein multiplexer is coupled to the misarrangement circuit.
9. circuit debuggers as claimed in claim 7, the wherein particular electrical circuit are a phase-locked loop.
10. circuit debuggers as claimed in claim 9, wherein mode of operation of the particular electrical circuit is the phase-locked loop institute
The frequency for producing, the misarrangement circuit produces the judged result to determine whether the phase-locked loop is normally run according to the frequency.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562270542P | 2015-12-21 | 2015-12-21 | |
| US62/270,542 | 2015-12-21 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106896317A true CN106896317A (en) | 2017-06-27 |
| CN106896317B CN106896317B (en) | 2020-03-31 |
Family
ID=59191050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610820540.3A Active CN106896317B (en) | 2015-12-21 | 2016-09-13 | Circuit debugging method and circuit debugging system executed by scan chain of scan test |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106896317B (en) |
| TW (1) | TWI625534B (en) |
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| CN109725245A (en) * | 2017-10-30 | 2019-05-07 | 瑞昱半导体股份有限公司 | Arrangement for testing integrated circuit |
| CN111103531A (en) * | 2018-10-26 | 2020-05-05 | 瑞昱半导体股份有限公司 | Chip and method for manufacturing the same |
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Also Published As
| Publication number | Publication date |
|---|---|
| TWI625534B (en) | 2018-06-01 |
| TW201723516A (en) | 2017-07-01 |
| CN106896317B (en) | 2020-03-31 |
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