CN101102232A - A test shell circuit and its design method - Google Patents
A test shell circuit and its design method Download PDFInfo
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- CN101102232A CN101102232A CNA2006100902434A CN200610090243A CN101102232A CN 101102232 A CN101102232 A CN 101102232A CN A2006100902434 A CNA2006100902434 A CN A2006100902434A CN 200610090243 A CN200610090243 A CN 200610090243A CN 101102232 A CN101102232 A CN 101102232A
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Abstract
The invention comprises: at least one test enclosure register chain used for testing the core to be tested; an interconnection circuit for connecting said test enclosure register chain to the core to be tested; an interconnection circuit for connecting said test enclosure register chain to the external data channel. The invention also reveals a method for designing the test enclosure circuit.
Description
Technical field
The present invention relates to the Testability Design technical field of integrated circuit (IC) chip, relate in particular to a kind of test shell circuit and method for designing thereof at the design of network-on-chip data path bandwidth.
Background technology
Following System on Chip/SoC will be on the single chip of forming by billions of transistors integrated hundreds and thousands of cores.Such System on Chip/SoC will need the communication component of tens of G bits per second bandwidth, for these communication components of demand that satisfy Time To Market must be reusable.Many research work have proposed to use the replacement scheme of switching network as the interconnection of System on Chip/SoC core.Such network just is called as network-on-chip (NoC), and it can satisfy two crucial requirements of system in future: reusable and bandwidth varying.Recent many studies show that, network-on-chip will become the optimal case of system in future core on-chip interconnect.
If use the interconnection platform of network-on-chip, because all there being actual connection on the sheet between each core, so can realize arriving the electric path of each core as system.Multiplexing these communication resources are suggested as the idea of test access mechanism in test process, the result of many research work shows, this method can shorten the testing time greatly, and some test expenses, and for example number of pins and area overhead have also reduced greatly.
Yet how multiplexing effectively network-on-chip resource is a very challenging problem, because the design of network-on-chip router and data path all is to be optimized at the communication characteristics under the mode of operation, rather than according to test pattern.For example, in legacy system core framework, equate with the width of test access mechanism (TAM) usually, and in network-on-chip between the scan chain width of available network channel width and core and unequal, be to be unmatched between the scan chain width of available network channel width and core, this may have very serious negative effect to testing efficiency and test expense.
This waste to the network path bandwidth can be increased in quantity of data packets active in the network path, thereby brings extra power consumption expense.The test shell design of optimizing can be utilized bandwidth chahnel effectively, thereby reduces required data packets transmitted number in the test process, and reaches the purpose that improves the test concurrency.
Because different with in System on Chip/SoC of the target of testing in network-on-chip, so concrete allocation plan also is not quite similar.The main distinction shows following two aspects:
One, in traditional System on Chip/SoC framework, the width of test access bus directly has influence on the cost of test, so each embedded core only allows very limited scanning chain number.Therefore the configuration of scan chain need be carried out under this restrictive condition, need be with the prolongation of single core testing time as cost.Yet this no longer becomes bottleneck problem under the network-on-chip test structure of traditional test access bus not utilizing.Replace, test vector and output response utilize already present chip-on communication network to be transmitted.Each embedded core has been encapsulated (for example network interface) so that the communication of all input and output pins of core to be provided by one deck shell under mode of operation.This connection to each input and output pin can be taken as test access port under test pattern, and the number of scan chain only is subjected to the restriction of network channel bandwidth, number of scan chains is significantly smaller than the network channel bandwidth under most of situation, and therefore the test shell according to the conventional method design can bring very big waste to the network channel bandwidth.
Two, in traditional System on Chip/SoC, core scan chain to be measured is configured to the length (for example, identical length) of balance as much as possible, and all of each test vector all are moved in the scan chain simultaneously and go.Because the test access bus run bandwidth of design equates with the number of core scan chain to be measured, can make the bandwidth chahnel waste minimum like this.Yet situation is different in network-on-chip.The network channel structure is that the operation according to network-on-chip under the mode of operation designs and disposes, and therefore may exist between the network channel bandwidth of a core logic and the core scan chain number to be measured not match.This problem will can not influence the testing time of single core, but the waste of network channel will bring extra network traffic, and therefore the total testing time to entire chip brings tremendous influence.
Therefore,, can utilize the test shell design of the bandwidth of network channel to be suggested to greatest extent,, reduce testing cost to shorten the testing time according to new test access mode characteristics.
Summary of the invention
(1) technical problem that will solve
In view of this, a main purpose of the present invention is to provide a kind of test shell circuit at the design of network-on-chip data path bandwidth, to make full use of the bandwidth of network channel, shortens the testing time, reduces testing cost.
Another main purpose of the present invention is to provide a kind of method for designing at network-on-chip data path bandwidth test shell circuit, to make full use of the bandwidth of network channel, shortens the testing time, reduces testing cost.
(2) technical scheme
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of test shell circuit, this circuit comprises: at least one is used to test the test shell chain of registers of core test data to be measured, connect the interconnection circuit between described test shell chain of registers and the core to be measured, and connect the interconnection circuit between described test shell chain of registers and the external data path.
Described test shell chain of registers is made of a plurality of register polyphones, by the interconnection circuit between test shell chain of registers and the core to be measured, and the interconnection circuit between test shell chain of registers and the external data path, realize the Data Matching between core to be measured and the external data path.
A kind of method for designing of test shell circuit, this method comprises:
A, determine the length of test shell chain of registers;
The theory lower bound value of B, calculating transmission core test data desired data bag number to be measured;
C, according to the length of test shell chain of registers with transmit the theory lower bound value of core test data desired data bag number to be measured, determine the inner number that merges the new scan chain in back of core to be measured, core internal scan chain to be measured and base i/o port are merged on the described new scan chain that ascertains the number;
D, set up the inner corresponding relation that merges the new scan chain in back of test shell chain of registers and core to be measured, connect the interconnection circuit between test shell chain of registers and external data path and test shell chain of registers and the core to be measured.
The length of determining the test shell chain of registers described in the steps A comprises: the number of data path data bit is defined as the number of registers on every test shell chain of registers, the i.e. length of every test shell chain of registers.
The theory lower bound value of calculating transmission core test data desired data bag number to be measured described in the step B is according to formula
Calculate, wherein n
pFor transmitting the theory lower bound value of core test data desired data bag number to be measured, t is the data volume sum that the test vector of core to be measured comprises, this data volume sum comprises test data on base i/o port and the internal scan chain, and w is the bandwidth value of network-on-chip data path.
Described in the step C according to the theory lower bound value of the length of test shell chain of registers and transmission core test data desired data bag number to be measured, determine that the inner number that merges the new scan chain in back of core to be measured comprises: the length of supposing every test shell chain of registers is N, and the theory lower bound value of transmitting core test data desired data bag number to be measured is n
p, the inner number that merges the new scan chain in back of core to be measured is g, and the number before core internal scan chain to be measured merges is m, and the length of every scan chain is L
iI=1 wherein, 2, ..., m then merges to the new scan chain of g bar with original m bar scan chain and base i/o port and gets on, under every indivisible prerequisite of internal scan chain, if there is practicable Merge Scenarios, m bar scan chain is merged into the new scan chain of g bar, and the inner length of the new scan chain in back that merges of core to be measured is smaller or equal to (N/g) * n
p, then determine the inner number g that merges the new scan chain in back of core to be measured.
The inner number g that merges the new scan chain in back of described core to be measured is the factor of every test shell chain of registers length N, can be divided exactly by N.
The inner span that merges the number g of the new scan chain in back of described core to be measured is { 2
n, 2
N-1, 2
N-2... 2,1}, in order to shorten the packing cycle as far as possible, successively above-mentioned value is attempted from big to small, there is practicable Merge Scenarios until satisfying, m bar scan chain is merged into the new scan chain of g bar, and the inner length of the new scan chain in back that merges of core to be measured is smaller or equal to (N/g) * n
pTill the condition.
Setting up the inner corresponding relation that merges the new scan chain in back of test shell chain of registers and core to be measured described in the step D is one-to-one relationship.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, utilize the present invention, by determining the length of test shell chain of registers, calculate the theory lower bound value of transmission core test data desired data bag number to be measured, and according to the length of test shell chain of registers and the theory lower bound value of transmission core test data desired data bag number to be measured, determine the inner number that merges the new scan chain in back of core to be measured, core internal scan chain to be measured and base i/o port are merged on the described new scan chain that ascertains the number, set up the inner corresponding relation that merges the new scan chain in back of test shell chain of registers and core to be measured, connect the interconnection circuit between test shell chain of registers and external data path and test shell chain of registers and the core to be measured, realized design to test shell circuit, the test access function of traditional test shell not only is provided, and carried out optimal design according to the characteristics of network-on-chip test data transmission, made full use of the bandwidth of network channel.
2, utilize test shell circuit provided by the invention and method for designing,,, improved the concurrency of test greatly so reduced the number of transmits data packets in the network-on-chip owing to made full use of the bandwidth of network channel.
3, utilize test shell circuit provided by the invention and method for designing, owing to made full use of the bandwidth of network channel, reduced the number of transmits data packets in the network-on-chip, thus greatly reduce the extra power consumption expense that a large amount of alive data bags cause, and then shortened the testing time greatly.
4, utilize test shell circuit provided by the invention and method for designing, owing to made full use of the bandwidth of network channel, reduced the required number of pins of Testability Design and the expense of area, so greatly reduce the Testability Design cost.
Description of drawings
Fig. 1 is the schematic diagram of the test shell circuit at network-on-chip data path bandwidth design provided by the invention;
Fig. 2 is the realization flow figure at network-on-chip data path bandwidth design test shell circuit overall technological scheme provided by the invention;
Fig. 3 is the circuit interconnection mode schematic diagram of one group of register on the test shell;
Fig. 4 has the System on Chip/SoC frame diagram that adopts the network-on-chip communication structure at the test shell of bandwidth Design.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 1, Fig. 1 is the schematic diagram of the test shell circuit at network-on-chip data path bandwidth design provided by the invention, this circuit comprises two parts: at least one is used to test the test shell chain of registers of core test data to be measured, and interconnection circuit between test shell register and core to be measured and external data path.
Wherein, the test shell chain of registers that is used to test core test data to be measured is generally many, and concrete number determines that according to actual conditions the method for determining hereinafter will be described in detail, and temporarily omit here.Described test shell chain of registers is made of a plurality of register polyphones, by the interconnection circuit between test shell chain of registers and the core to be measured, and the interconnection circuit between test shell chain of registers and the external data path, realize the Data Matching between core to be measured and the external data path.
Interconnection circuit comprises between described test shell register and core to be measured and external data path: be connected the interconnection circuit between described test shell chain of registers and the core to be measured, and connect the interconnection circuit between described test shell chain of registers and the external data path.
In Fig. 1, described one and be applicable to that data path bandwidth is 16 the test shell circuit at bandwidth Design.Every the test shell chain of registers is made of one group of register, comprises 5 internal scan chains and 4 basic input/output end ports in the core to be measured, and the network-on-chip data path bandwidth is 16.The test shell chain of registers realizes Data Matching between core to be measured and the data path by the interconnection circuit between itself and core to be measured and the external data path.
For a concrete test shell at bandwidth Design, its basic configuration parameter has following three: the length N of every test shell chain of registers, the bar of test shell chain of registers is counted g, the maximum length l of the inner new scan chain of core to be measured of every test shell chain of registers correspondence.
At first, for realizing making full use of the purpose of data bandwidth, the size of packet, be the length of every test shell chain of registers, register number N on the test shell chain of registers in other words, should equate with the bandwidth value w of network-on-chip data path, could make all corresponding effectively test data of data bit in each packet.
Suppose that the data volume that the test vector of core to be measured comprises adds up to t, this data volume sum comprises test data on base i/o port and the internal scan chain, and the data channel bandwidth of network-on-chip is w, then transmits test vector desired data bag quantity n
pThe theory lower bound value be
Design object at the test shell circuit of bandwidth Design is exactly to utilize minimum hardware spending to make the test data desired data bag quantity of transmission core to be measured reach above-mentioned lower limit.
For realizing this purpose, according to the present invention, a kind of merging core scan chain to be measured and base i/o port have been proposed, and with itself and the corresponding method of test shell register grouping.Whether comprise scan chain according to core to be measured inside method for designing be divided into following two kinds of situations:
There is not internal scan chain in situation 1, the core to be measured,, transmitted the required number-of-packet of these base i/o port test datas and be then with p average being assigned on N the test shell register of base i/o port:
Promptly transmit the theory lower bound value of core test data desired data bag number to be measured.
There is internal scan chain in situation 2, the core to be measured, then needs the number-of-packet theory lower bound value n that calculates according to formula (1)
pInternal scan chain and base i/o port are merged, and it is corresponded on each test shell registers group.Concrete grouping and corresponding method analysis are described as follows:
The length of supposing every test shell chain of registers is N, and the theory lower bound value of transmitting core test data desired data bag number to be measured is n
p, the inner number that merges the new scan chain in back of core to be measured is g, and the number before core internal scan chain to be measured merges is m, and the length of every scan chain is L
iI=1 wherein, 2, ..., m then merges to the new scan chain of g bar with original m bar scan chain and base i/o port and gets on, under every indivisible prerequisite of internal scan chain, if there is practicable Merge Scenarios, m bar scan chain is merged into the new scan chain of g bar, and the inner length of the new scan chain in back that merges of core to be measured is smaller or equal to (N/g) * n
p, the test shell register number that every new scan chain is assigned to then is
Then determine the inner number g that merges the new scan chain in back of core to be measured.
When choosing suitable g, mainly carry out following 2 considerations:
Consider 1, if the aliquant N of g then will have N-(N/g) * g=N modg bit data to be wasted in each packet.Therefore, for making full use of data channel bandwidth, g is required to be the factor of N.
Consider 2, since in digit chip data channel bandwidth w be generally 2
n, so the possible span of g is generally { 2
n, 2
N-1, 2
N-2... 2,1}, in order to shorten the packing cycle as far as possible, successively above-mentioned value is attempted from big to small, there is practicable Merge Scenarios until satisfying, m bar scan chain is merged into the new scan chain of g bar, and the inner length of the new scan chain in back that merges of core to be measured is smaller or equal to (N/g) * n
pTill the condition.
Above-mentioned test shell chain of registers has two kinds of mode of operations:
1, loading pattern, be used for the test stimulus data of test shell chain of registers is moved on to core base i/o port to be measured and internal scan chain input/output port, or the test response data in core base i/o port to be measured and the internal scan chain input/output port moved on on the test shell chain of registers, according to the needed clock periodicity difference of the different loading patterns of design parameter, computing formula is T=N/g.
2, transmission mode is squeezed in the test shell chain of registers the test stimulus data in the network-on-chip data path is parallel, or squeezes in the network-on-chip data path the test response data in the test shell chain of registers is parallel.
Foregoing has elaborated at the optimization aim of network-on-chip data path bandwidth design test shell circuit and the design rule of recommendation, meet these rules and can guarantee that test shell can provide on the basis of basic test visit and test data packing function, utilizes fully to the bandwidth of network-on-chip data channel when carrying out the test data transmission.
Based on above-mentioned at the optimization aim of network-on-chip data path bandwidth design test shell circuit and the design rule of recommendation, Fig. 2 shows the realization flow figure at network-on-chip data path bandwidth design test shell circuit overall technological scheme provided by the invention, and this method may further comprise the steps:
Step 201: the length of determining the test shell chain of registers;
Step 202: the theory lower bound value of calculating transmission core test data desired data bag number to be measured;
Step 203: according to the length of test shell chain of registers and the theory lower bound value of transmission core test data desired data bag number to be measured, determine the inner number that merges the new scan chain in back of core to be measured, core internal scan chain to be measured and base i/o port are merged on the described new scan chain that ascertains the number, make every new scan chain length less than the value of determining according to the new scan chain number of merging;
Step 204: set up the inner corresponding relation that merges the new scan chain in back of test shell chain of registers and core to be measured, connect the interconnection circuit between test shell chain of registers and external data path and test shell chain of registers and the core to be measured.
In above-mentioned steps 201, in order to make full use of the network channel bandwidth, should make each all corresponding Validity Test data in the data path, so the length N of test shell chain of registers should equal the number w of data path data bit as far as possible.Be that the length of determining the test shell chain of registers described in the above-mentioned steps 201 comprises: the number w of data path data bit is defined as the number of registers on every test shell chain of registers, the i.e. length N of every test shell chain of registers.
In above-mentioned steps 202, described calculating is transmitted the theory lower bound value of core test data desired data bag number to be measured according to formula
Calculate, wherein n
pFor transmitting the theory lower bound value of core test data desired data bag number to be measured, t is the data volume sum that the test vector of core to be measured comprises, this data volume sum comprises test data on base i/o port and the internal scan chain, and w is the bandwidth value of network-on-chip data path.
In above-mentioned steps 203, described according to the length of test shell chain of registers and the theory lower bound value of transmission core test data desired data bag number to be measured, determine that the inner number that merges the new scan chain in back of core to be measured comprises: the length of supposing every test shell chain of registers is N, and the theory lower bound value of transmitting core test data desired data bag number to be measured is n
p, the inner number that merges the new scan chain in back of core to be measured is g, and the number before core internal scan chain to be measured merges is m, and the length of every scan chain is L
iI=1 wherein, 2, ..., m then merges to the new scan chain of g bar with original m bar scan chain and base i/o port and gets on, under every indivisible prerequisite of internal scan chain, if there is practicable Merge Scenarios, m bar scan chain is merged into the new scan chain of g bar, and the inner length of the new scan chain in back that merges of core to be measured is smaller or equal to (N/g) * n
p, the test shell register number that every new scan chain is assigned to then is
Then determine the inner number g that merges the new scan chain in back of core to be measured.
The inner number g that merges the new scan chain in back of described core to be measured is the factor of every test shell chain of registers length N, can be divided exactly by N.The inner span that merges the number g of the new scan chain in back of described core to be measured is { 2
n, 2
N-1, 2
N-2... 2,1}, in order to shorten the packing cycle as far as possible, successively above-mentioned value is attempted from big to small, there is practicable Merge Scenarios until satisfying, m bar scan chain is merged into the new scan chain of g bar, and the inner length of the new scan chain in back that merges of core to be measured is smaller or equal to (N/g) * n
pTill the condition.
In above-mentioned steps 204, the described corresponding relation of setting up the new scan chain of test shell chain of registers and core to be measured inner merging back is an one-to-one relationship.Every group of register on the test shell, i.e. new scan chain in the corresponding core to be measured of every test shell chain of registers, the interconnection circuit width is w between registers group and router, and the interconnection circuit width is g between core to be measured.
Based on the described realization flow figure at network-on-chip data path bandwidth design test shell circuit overall technological scheme provided by the invention of Fig. 2, the method that the present invention is directed to network-on-chip data path bandwidth design test shell circuit is further described below in conjunction with specific embodiment.
Embodiment
In the present embodiment, suppose to comprise in the core to be measured 15 scan chains that contain 45 registers, article 5, the scan chain that comprises 20 registers, and 108 input/output end ports, 108 is the maximum of between input port number and output port number, the bandwidth w of data path is 16, then equals the bandwidth w of data path according to test shell register sum N, can determine that at first test shell register sum N is 16.
Then, calculate the theory lower bound value of transmission core test data desired data bag number to be measured according to formula (1):
Then, because w=16, successively according to { 16,8,4,2, the order trial of 1} is assigned to the test shell register in g the grouping and goes.
At first suppose g=16, then the register on every new scan chain is counted the base i/o port that l comprises interpolation and must not be surpassed (N/g) * n
p=(16/16) * 56=56.Under the inner indivisible prerequisite of every scan chain of hypothesis, because 15+5=20 bar scan chain was arranged originally, for the new scanning chain number after satisfied the merging is 16, then need at least 5 scan chains that comprise 20 registers are combined into 1, perhaps 54 of comprising in 20 register scan chains are merged in other 16 scan chains, 16 scan chains described here comprise 1 scan chain and 15 scan chains that contain 45 registers of containing 20 registers.So, the length of new scan chain is at least 45+20=65, greater than (N/g) * n
p=(16/16) * 56=56, so this length can't meet the demands, so the hypothesis of g=16 is false.
Continue hypothesis g=8 then, then the register on every new scan chain is counted the base i/o port that l comprises interpolation and must not be surpassed (N/g) * n
p=(16/8) * 56=112.After the inner number that merges the new scan chain in back of hypothesis core to be measured is 8, seek and whether have a practicable Merge Scenarios, make 20 original scan chains can merge into 8 new scan chains, if there is a practicable Merge Scenarios, make 20 original scan chains can merge into 8 new scan chains, then the hypothesis of g=8 is set up; Otherwise the hypothesis of g=8 is false.
Above-mentioned 20 scan chains merging can be assigned on 8 new scan chains by following scheme, and the length of every scan chain is no more than 112:
1) 15 scan chains that contain 45 registers is merged into 7 scan chain and scan chains that contain 45 registers that contain 90 registers;
2) 5 scan chains that contain 20 registers are merged to 1) in the scan chain that contains 90 registers that produces, have 5 scan chains that contain 110 registers, 2 scan chain and 1 scan chains that contain 45 registers of containing 90 registers in the circuit this moment;
3) base i/o port is filled in the above-mentioned scan chain, and make the length of every scan chain be no more than 112, specify for: on 5 scan chains that contain 110 registers, respectively fill two ports, on 2 scan chains that contain 90 registers, respectively fill 22 ports, remaining 54 ports are filled on 1 scan chain that contains 45 registers.
Therefore, the hypothesis of g=8 is set up, and determines the inner number g=8 that merges the new scan chain in back of core to be measured.So, 16 registers on the test shell can be assigned in 8 registers group, wherein each registers group contains 2 registers, distributes to 8 above-mentioned new scan chains respectively.2 test data positions that in each packet, comprise every new scan chain.
At last, set up the inner one-to-one relationship that merges between the new scan chain in back of test shell chain of registers and core to be measured, connect the interconnection circuit between test shell chain of registers and external data path and test shell chain of registers and the core to be measured.As shown in Figure 3, Fig. 3 is the circuit interconnection mode schematic diagram of one group of register on the test shell.
The present invention can be applied in adopting the system chip test technology of network-on-chip as test access mechanism.As shown in Figure 4, Fig. 4 has the System on Chip/SoC frame diagram that adopts the network-on-chip communication structure at the test shell of bandwidth Design.Data path bandwidth among the figure is w, and test shell is positioned at core to be measured and the network-on-chip communication resource (as router) coupling part, and the bandwidth between test shell and router is w, and the bandwidth between core to be measured is g.Utilize the form of packet to send to test shell test data and use, or the test response of core to be measured is sent on the test shell, send to the network-on-chip data channel by the mechanism of packing, and output to observation station for comparative result for core to be measured.Owing to may make the corresponding a plurality of registers of every scan chain at the test shell of bandwidth Design, every to data bit clock cycle of needs of a register immigration, owing to comprise N/g register in each registers group, therefore needing N/g clock cycle is test shell chain of registers loading data.
Owing on the System on Chip/SoC of the on-chip network structure that adopts, include a plurality of cores to be measured, in order rationally to arrange each transmission of test core test data in network-on-chip, reduce total testing time, need be to test packet transmission the carrying out test dispatching of individual core to be measured.
Use is dispatched at the core test packet to be measured of the test shell of bandwidth Design can take two kinds of schemes, the one, do not change test data and between test shell and core to be measured, move in and out clock frequency, interlock in the interval in each core packing cycle to be measured and carry out the transmission of other core test datas, this requires core test shell of staggered transmission that the identical packing cycle is arranged; Another kind is that the clock frequency that moves in and out between test shell and core to be measured is improved N/g doubly, thereby equated in the packing cycle of each core to be measured on the sheet, but this may bring the sharp increase of testing power consumption, because chip power-consumption and operating frequency claim direct ratio, frequency improves N/g doubly in theory, testing power consumption also can increase N/g doubly, need carry out under certain power consumption constraints condition.
The present invention has the high characteristics of data bandwidth chahnel utilance at the test shell of bandwidth Design.Design can reach the upper limit of the theoretical utilance of data channel bandwidth at the test shell of the test shell of bandwidth Design in application, has reduced the number of transmits data packets in the network-on-chip, cooperates suitable test dispatching algorithm to reduce the testing time.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1, a kind of test shell circuit is characterized in that, this circuit comprises:
At least one is used to test the test shell chain of registers of core test data to be measured, connects the interconnection circuit between described test shell chain of registers and the core to be measured, and connects the interconnection circuit between described test shell chain of registers and the external data path.
2, test shell circuit according to claim 1, it is characterized in that, described test shell chain of registers is made of a plurality of register polyphones, by the interconnection circuit between test shell chain of registers and the core to be measured, and the interconnection circuit between test shell chain of registers and the external data path, realize the Data Matching between core to be measured and the external data path.
3, a kind of method for designing of test shell circuit is characterized in that, this method comprises:
A, determine the length of test shell chain of registers;
The theory lower bound value of B, calculating transmission core test data desired data bag number to be measured;
C, according to the length of test shell chain of registers with transmit the theory lower bound value of core test data desired data bag number to be measured, determine the inner number that merges the new scan chain in back of core to be measured, core internal scan chain to be measured and base i/o port are merged on the described new scan chain that ascertains the number;
D, set up the inner corresponding relation that merges the new scan chain in back of test shell chain of registers and core to be measured, connect the interconnection circuit between test shell chain of registers and external data path and test shell chain of registers and the core to be measured.
4, the method for designing of test shell circuit according to claim 3 is characterized in that, determines described in the steps A that the length of test shell chain of registers comprises:
The number of data path data bit is defined as the number of registers on every test shell chain of registers, the i.e. length of every test shell chain of registers.
5, the method for designing of test shell circuit according to claim 3 is characterized in that, the theory lower bound value of calculating transmission core test data desired data bag number to be measured described in the step B is according to formula
Calculate, wherein n
pFor transmitting the theory lower bound value of core test data desired data bag number to be measured, t is the data volume sum that the test vector of core to be measured comprises, this data volume sum comprises test data on base i/o port and the internal scan chain, and w is the bandwidth value of network-on-chip data path.
6, the method for designing of test shell circuit according to claim 3, it is characterized in that, according to the length of test shell chain of registers and the theory lower bound value of transmission core test data desired data bag number to be measured, determine that the inner number that merges the new scan chain in back of core to be measured comprises described in the step C:
The length of supposing every test shell chain of registers is N, and the theory lower bound value of transmitting core test data desired data bag number to be measured is n
p, the inner number that merges the new scan chain in back of core to be measured is g, and the number before core internal scan chain to be measured merges is m, and the length of every scan chain is L
iI=1 wherein, 2, ..., m then merges to the new scan chain of g bar with original m bar scan chain and base i/o port and gets on, under every indivisible prerequisite of internal scan chain, if there is practicable Merge Scenarios, m bar scan chain is merged into the new scan chain of g bar, and the inner length of the new scan chain in back that merges of core to be measured is smaller or equal to (N/g) * n
p, then determine the inner number g that merges the new scan chain in back of core to be measured.
7, the method for designing of test shell circuit according to claim 6 is characterized in that, the inner number g that merges the new scan chain in back of described core to be measured is the factor of every test shell chain of registers length N, can be divided exactly by N.
8, the method for designing of test shell circuit according to claim 6 is characterized in that, the inner span that merges the number g of the new scan chain in back of described core to be measured is { 2
n, 2
N-1, 2
N-2... 2,1}, in order to shorten the packing cycle as far as possible, successively above-mentioned value is attempted from big to small, there is practicable Merge Scenarios until satisfying, m bar scan chain is merged into the new scan chain of g bar, and the inner length of the new scan chain in back that merges of core to be measured is smaller or equal to (N/g) * n
pTill the condition.
9, the method for designing of test shell circuit according to claim 3 is characterized in that, setting up the inner corresponding relation that merges the new scan chain in back of test shell chain of registers and core to be measured described in the step D is one-to-one relationship.
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