CN103279405A - Testing shell suitable for on-chip network embedded type IP core - Google Patents
Testing shell suitable for on-chip network embedded type IP core Download PDFInfo
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Abstract
The invention discloses a testing shell suitable for an on-chip network embedded type IP core and belongs to the technical field of embedded type IP core testing. The testing shell suitable for the on-chip network embedded type IP core comprises a parallel input port, a parallel bypass temporary storage, a parallel output port, a serial input port, a serial bypass temporary storage, a serial output port, a testing control temporary storage, a first multiplexer, a parallel testing response comparator, a serial testing response comparator, a correct testing response signal parallel input port and a correct testing response signal serial input port. Testing stimulus and correct testing response are simultaneously sent in an IP core to be tested, only one data sub-package is needed to complete testing, and the transmitting data size can be effectively reduced for a multicast transmission mode.
Description
Technical field
The invention discloses the test shell that is applicable to the embedded IP kernel of network-on-chip, belong to the technical field of embedded IP kernel test.
Background technology
NoC(Network-on-Chip, network-on-chip) design is adopted and SoC(System on Chip, SOC (system on a chip)) identical based on the multiplexing Design Mode of IP kernel, by a large amount of multiplexing by third party's design and through the IP kernels of checking, promote the design efficiency of NoC, shortened the R﹠D cycle.IP kernel multiplexing not only comprises the multiplexing of circuit logic, also comprises the test reuse of IP kernel simultaneously.After a large amount of IP kernels is embedded in NoC, the external terminal of chip can only conduct interviews by the port of packet forward mode to IP kernel, the original method of testing of single IP kernel is no longer suitable to the IP kernel after integrated, thereby makes embedded IP kernel test port lose original ornamental and controllability.In addition, multiplexing IP kernel is from different companies, function is different and different Testability Design strategies, the heterogeneite between the nuclear are arranged is the multiplexing difficulty that increased of test circuit, therefore needs a kind of general purpose control pattern of design to be beneficial to the multiplexing of IP kernel test circuit among the NoC.
IEEE 1500 standards are to aim at test problem such as the test access that solves embedded IP kernel among the SoC, isolation, control and a testing standard developing.In this standard, test shell (Wrapper) is in key position, and it is used for the encapsulation IP kernel, and making the IP kernel of different structure and DFT Test Strategy is isomorphism from testing integrated angle, thereby has simplified the nuclear test circuit system-level multiplexing.As the SoC of special shape, IEEE 1500 standards are equally applicable to the test of embedded IP kernel among the NoC.Usually adopt multiplexing NoC as test access visit passage in the IP kernel test based on NoC, so the design of its test shell also needs to adjust adaptively.
The embedded IP kernel test shell of existing a kind of NoC and interface circuit block diagram thereof are as shown in Figure 1, comprise following characteristic: (a) test data is with the network channel transmission of the same form with packet of normal function data by NoC, and group bag and the work that unpacks are finished by network interface NI; (b) code translator A and code translator B are responsible for respectively differentiating type of data packet and generating the various test commands of test shell; (c) design of Scan Architecture meets IEEE 1500 standards in the test shell, and the number of scan chain is consistent with the bit wide of NoC network packet microplate.
Existing test interface design proposal only is applicable to the test of the embedded IP under the common unicast mode, weak point is the test optimization effect of not mentioning the concrete NoC under the ad hoc structure, and the adaptability to other test patterns is relatively poor, also namely and be not suitable for the multicast test pattern.
Summary of the invention
Technical matters to be solved by this invention is the deficiency at the above-mentioned background technology, and the test that is applicable to the embedded IP kernel of network-on-chip shell is provided.
The present invention adopts following technical scheme for achieving the above object:
Be applicable to the test shell of the embedded IP kernel of network-on-chip, comprise parallel input port, parallel bypass register, parallel output terminal mouth, serial input terminal mouth, serial bypass register, serial output terminal mouth, test control register, first MUX, the described test shell of the embedded IP kernel of network-on-chip that is applicable to also comprises concurrent testing response comparator, serial test response comparer, the parallel input port of correct test response signal, correct test response signal serial input terminal mouth, wherein:
The parallel input port of described parallel bypass register input termination;
Described concurrent testing response comparator first input end is connected with the parallel input port of correct test response signal, the second input termination scan chain output terminal, the described parallel bypass register output terminal of the 3rd input termination, the described parallel output terminal mouth of output termination;
Described serial bypass register input end, test control register input end are connected with described serial input terminal mouth respectively;
Described serial test response comparer first input end is connected with correct test response signal serial input terminal mouth, second input end of the described concurrent testing response comparator of the serial test response comparer second input termination, the described serial bypass register of serial test response comparer the 3rd input termination output terminal;
The first input end of described first MUX connects described serial test response comparator output terminal, the described test control register of second input termination output terminal, the described serial output terminal mouth of output termination.
In the described test shell that is applicable to the embedded IP kernel of network-on-chip, the concurrent testing response comparator comprises concurrent testing unit, n road, the first input end of concurrent testing unit, every road is connected with the parallel input port of correct test response signal, the 1st second input termination scan chain output terminal to concurrent testing unit, n-1 road, second input end of n concurrent testing unit is connected with serial test response comparer, concurrent testing unit, every road output termination parallel output terminal mouth, described n is the integer greater than 1.
In the described test shell that is applicable to the embedded IP kernel of network-on-chip, serial test response comparer is a serial test cell, described serial test cell first input end is connected with correct test response signal serial input terminal mouth, serial test cell second input end is connected with second input end of concurrent testing unit, n road, serial test cell output termination first MUX.
In the described test shell that is applicable to the embedded IP kernel of network-on-chip, concurrent testing unit, serial test cell structure are identical, include XOR gate device, MUX, a correct test response signal of input termination of described XOR gate device, another input termination test signal; An input termination XOR gate device output end of described MUX, another input end receives the instruction that bypass register is sent.
The present invention adopts technique scheme, has following beneficial effect: test and excitation and correct test response are sent into IP kernel to be measured simultaneously, just can finish test only to need a data sub-packets, can effectively reduce transmitted data amount for the multicast transmission pattern.
Description of drawings
Fig. 1 is the embedded IP kernel test shell of a kind of NoC and interface circuit block diagram thereof.
Fig. 2 utilizes the frame diagram that is applicable to the test shell test S444 circuit of the embedded IP kernel of network-on-chip of the present invention.The number in the figure explanation: m1 to m12 is the first to the 12 MUX, and Y1 to Y4 is first to fourth XOR gate device.
Fig. 3 is the circuit diagram of bypass register.
Fig. 4 is the circuit diagram of test boundary element.
Fig. 5 is the circuit diagram of order register.
Embodiment
Be elaborated below in conjunction with the technical scheme of accompanying drawing to invention.
With the S444 circuit in the ISCAS89 benchmark sequential circuit be that the circuit that example describes each component part of test shell in detail is realized, the data transmission route of test shell joint mouth circuit and various test patterns.
Add behind the test shell the S444 nuclear structure as shown in Figure 2, comprise parallel input port Pi[2:0], parallel bypass register, parallel output terminal mouth Po[2:0], serial input terminal mouth Si, serial bypass register, serial output terminal mouth So, test control register, the first MUX m1, serial test response comparer, concurrent testing response comparator, the parallel input port Com_pi[2:0 of correct test response signal], correct test response signal serial input terminal mouth Com_si.The parallel input port Pi[2:0 of parallel bypass register input termination].Concurrent testing response comparator first input end meets the parallel input port Com_pi[2:0 of correct test response signal], the second input termination scan chain output terminal, the parallel bypass register output terminal of the 3rd input termination, output termination parallel output terminal mouth Po[2:0].Being connected with serial input terminal mouth Si respectively of the input end of serial bypass register, test control register input end.Serial test response comparer first input end meets correct test response signal serial input terminal mouth Com_si, second input end of the serial test response comparer second input termination concurrent testing response comparator, serial test response comparer the 3rd input terminated serial bypass register output terminal.The first input end of the first MUX m1 connects serial test response comparator output terminal, the second input termination test control register output terminal, output termination serial output terminal mouth So.Parallel comparator comprises 3 road concurrent testing unit, the 1 road concurrent testing unit is made up of the first XOR gate device Y1, the second MUX m2, the 2 road concurrent testing unit is made up of the second XOR gate device Y2, the 3rd MUX m3, and the 3 road concurrent testing unit is made up of the 3rd XOR gate device Y3, the 4th MUX m4.Serial test response comparer is a serial test cell, and the serial test cell is made up of the 4th XOR gate device Y4, the 5th MUX m5.The first input end of the 4th XOR gate device Y4 is connected with correct test response signal serial input terminal mouth Com_si.The first input end of XOR gate device meets the parallel input port Com_pi[2:0 of correct test response signal in the concurrent testing unit, every road], second of the XOR gate device input termination scan chain 1 in the 1st to the 2 road concurrent testing unit, scan chain 2 output terminals, second input end of XOR gate device in the XOR gate device second input terminated serial test cell in the 3rd concurrent testing unit, an input of the 5th MUX m5 termination the 4th XOR gate device Y4 output terminal, another input terminated serial bypass register output terminal of the 5th MUX m5, input end of the 5th MUX m5 output termination first MUX m1, another input termination test control register output terminal of the first MUX m1, first MUX m1 output termination serial output terminal mouth So.
The insertion of scan chain is exactly all triggers in replacing designing with special trigger, the most generally the structure of Shi Yonging is that multichannel is selected trigger, these multichannels selection triggers couple together and have constituted a scan chain, just as the shift register of a serial, scan chain can be operated in normal mode and test pattern.The length of all scan chains that insert should keep evenly, thereby avoids the multi-strip scanning chain length to differ the waste of too big test duration of causing.By first scan chain, second scan chain that the 8th MUX m8 to the 12 MUX m12 constitute, the test signal that the parallel input port of processing enters obtains the input signal of concurrent testing response comparator.
Test shell bypass register (WBY, Wrapper BYpass register)) as shown in Figure 3, for not needing to provide a quick transmission channel by the data of IP kernel at the corresponding levels, be the indispensable structure of Wrapper in IEEE 1500 standards, the function of data transmission and maintenance is arranged.The used bypass register of the present invention is made of MUX and d type flip flop.When data will be passed through from bypass register, enable signal was high level, and data are imported into from the bypass register input end, through d type flip flop, from the output of bypass register output terminal, when data are not transmitted from bypass register, enable signal is low level, and trigger is preserved currency.Test shell among the present invention has serial bypass and two kinds of structures of parallel bypass, and parallel bypass register is by single bypass register and constitutes together.
WBR is by test shell boundary element (WBC, Wrapper Boundary Cell) constitutes, the normal function input port in[2:0 of IP kernel], normal function output port out[5:0] signals such as (do not comprise clock) resetting all will place a WBC, with ornamental and the measurability that realizes these ports.A WBC should comprise four fens ports at least: function number inbound port, function number outbound port, test input mouth and test output terminal mouth.Under the effect of control signal, performance data can be transferred to the function number outbound port from the function number inbound port, and test data also can be passed to the test output terminal mouth from the test input oral instructions.Single WBC is after inserting MUX, and a plurality of test input mouths and test output terminal mouth link together and just constituted a WBR.Test boundary element circuit diagram as shown in Figure 4.
The control signal of test boundary element WBC is enable signal and sweep signal, when the both is 0, realizes that performance data is transferred to the function number outbound port from the function number inbound port, moves into the IP kernel function port that links to each other with the function number outbound port then; The both is 1 o'clock, realizes that test data moves into the test output terminal mouth from the test input mouth, realizes the locomotive function of test data.The present invention has designed inside and outside two kinds of test patterns, and for the external testing pattern, performance data and test data all will be transmitted from WBR, is 0 so enable signal is set, and the surface sweeping signal is 1; For internal test mode, have only test data mobile in WBR, so enable signal is set and sweep signal all is 1.Employing is inserted the mode of MUX and test input mouth, test output terminal mouth head and the tail is connected in turn to WBC and just constituted a WBR, thereby by the test under the gated mode realization different mode of controlling each MUX.
The order register circuit structure as shown in Figure 5, wherein the input MUX Enable Pin of order register is shift signal, it is the figure place of instruction code that shift signal keeps the clock periodicity of high level.Upgrade the enable signal of register input end MUX for resetting/update signal, at test period, reset signal keeps high level always, update signal keeps the high level of a clock period after the instruction end of transmission (EOT), in order to upgrade data in the register, become low level then, make data be kept at and upgrade in the register.
The present invention adds the test response comparer in the test shell after, can send into IP kernel to be measured to test and excitation and correct test response simultaneously, judge directly by testing the result of shell self according to comparer whether IP kernel exists fault, and give the test place test result of a microplate length.Can only need a data sub-packets just can finish test like this, can effectively reduce transmitted data amount for the multicast transmission pattern especially.
Claims (4)
1. be applicable to the test shell of the embedded IP kernel of network-on-chip, comprise parallel input port, parallel bypass register, parallel output terminal mouth, serial input terminal mouth, serial bypass register, serial output terminal mouth, test control register, first MUX, it is characterized in that, the described test shell of the embedded IP kernel of network-on-chip that is applicable to also comprises concurrent testing response comparator, serial test response comparer, the parallel input port of correct test response signal, correct test response signal serial input terminal mouth, wherein:
The parallel input port of described parallel bypass register input termination;
Described concurrent testing response comparator first input end is connected with the parallel input port of correct test response signal, the second input termination scan chain output terminal, the described parallel bypass register output terminal of the 3rd input termination, the described parallel output terminal mouth of output termination;
Described serial bypass register input end, test control register input end are connected with described serial input terminal mouth respectively;
Described serial test response comparer first input end is connected with correct test response signal serial input terminal mouth, second input end of the described concurrent testing response comparator of the serial test response comparer second input termination, the described serial bypass register of serial test response comparer the 3rd input termination output terminal;
The first input end of described first MUX connects described serial test response comparator output terminal, the described test control register of second input termination output terminal, the described serial output terminal mouth of output termination.
2. the test shell that is applicable to the embedded IP kernel of network-on-chip according to claim 1, it is characterized in that, described concurrent testing response comparator comprises concurrent testing unit, n road, the first input end of concurrent testing unit, every road is connected with the parallel input port of correct test response signal, the 1st second input termination scan chain output terminal to concurrent testing unit, n-1 road, second input end of n concurrent testing unit is connected with serial test response comparer, concurrent testing unit, every road output termination parallel output terminal mouth, described n is the integer greater than 1.
3. the test shell that is applicable to the embedded IP kernel of network-on-chip according to claim 2, it is characterized in that, described serial test response comparer is a serial test cell, described serial test cell first input end is connected with correct test response signal serial input terminal mouth, serial test cell second input end is connected with second input end of concurrent testing unit, n road, serial test cell output termination first MUX.
4. the test shell that is applicable to the embedded IP kernel of network-on-chip according to claim 3, it is characterized in that, described concurrent testing unit, serial test cell structure are identical, include XOR gate device, MUX, a correct test response signal of input termination of described XOR gate device, another input termination test signal; An input termination XOR gate device output end of described MUX, another input end receives the instruction that bypass register is sent.
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| CN107300666A (en) * | 2017-06-15 | 2017-10-27 | 西安微电子技术研究所 | The test of embedded IP stone accesses isolation structure on a kind of SOC pieces |
| CN107345997A (en) * | 2016-05-04 | 2017-11-14 | 中国科学院微电子研究所 | A kind of IP kernel method of testing based on test shell |
| CN107345999A (en) * | 2016-05-04 | 2017-11-14 | 中国科学院微电子研究所 | Test shell design method and device |
| CN107729191A (en) * | 2016-08-10 | 2018-02-23 | 中国科学院微电子研究所 | Resolution chart interpretation method and core test housing apparatus |
| CN113484604A (en) * | 2021-07-08 | 2021-10-08 | 中国人民解放军国防科技大学 | SET pulse measuring circuit capable of eliminating influence of measuring circuit and integrated circuit chip |
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| CN107300666A (en) * | 2017-06-15 | 2017-10-27 | 西安微电子技术研究所 | The test of embedded IP stone accesses isolation structure on a kind of SOC pieces |
| CN113484604A (en) * | 2021-07-08 | 2021-10-08 | 中国人民解放军国防科技大学 | SET pulse measuring circuit capable of eliminating influence of measuring circuit and integrated circuit chip |
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Application publication date: 20130904 |