JP2001110200A - Diagnostic method for ram and lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a manufacturing cost of a tester using a tester having lower speed than an operation frequency of a LSI or to reduce overhead for chip area of a BIST circuit. SOLUTION: A tester 10 operated with speed of half of an operation frequency of a LSI 12 inputs data 1, 2 into input pins 24, 25 synchronously with a clock of the tester 10. A parallel-serial converting circuit 27 in a RAM test logic circuit 13 converts inputted data to serial data switched by a clock of the LSI 12, and writes it in a RAM 14 by a clock of the LSI in order of data 1, data 2. A RAM test logic circuit 15 reads out the data 1 and the data 2 written in the RAM 14 synchronously with a clock of the LSI 12. A serial- parallel converting circuit 30 writes the read out data 1, 2 in a tester 17 by outputting alternately the data 1, 2 to output pins 31, 32 so as to be switched by the tester 17. The tester 17 compares read out data with an expected value and extracts fault of the RAM 14. Operation speed of the tester 10 may be 1/t of the LSI 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of diagnosing a RAM mounted on an LSI and an LSI, and more particularly to a method for testing a RAM at a high speed by using a tester having an operation frequency lower than the operation frequency of the RAM inside the LSI. R that enabled
The present invention relates to an AM diagnosis method and an LSI.

[0002]

2. Description of the Related Art Generally, a diagnosis of a RAM mounted on an LSI is performed by operating the RAM mounted on the LSI at an actual operating frequency by a tester and extracting a failure of the RAM. As a conventional technique for diagnosing a RAM mounted on such an LSI, a method of connecting a tester having the same frequency as that of the LSI to the LSI to diagnose the RAM,
The BIST logic for generating random test data provided inside the SI is operated at the operating frequency of the LSI and RA
There is known a method of performing M diagnosis.

FIG. 5 shows that the RAM mounted on the LSI is
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating a configuration of a conventional technique for performing a diagnostic test using a tester having the same operating frequency as that of an SI, and the conventional technique will be described below. In FIG. 5, 10 and 17 are testers, 11 is an LSI input edge pin, 12 is an LSI,
13 and 15 are RAM test logic circuits, 14 is RAM, 1
Reference numeral 6 denotes an LSI output edge pin. Although only one input and output edge pin is shown, actually, data having a predetermined bit width is used as data, and therefore, pins for the number of bits are provided. This means
The same applies to the case of another conventional technique described below.

Inside the LSI 12, RAM test logic circuits 13 and 15, which are circuits for reading and writing data directly from the LSI edge pins to the RAM, and a RAM 14, are mounted. Many logic circuits are mounted. Testers 10 and 17 are connected to the LSI input edge pin 11 and the LSI output edge pin 16 for diagnosis of the RAM 14 in the LSI 12 having such a configuration. Although the testers 10 and 17 are illustrated as being connected to the input side and the output side of the LSI 12 for ease of description, these are integrated.

[0005] The tester 10 operates at the same frequency as the LSI 12, and test data is input from the tester 10 to the LSI input edge pin 11. RA
The M test logic circuit 13 converts the input test data into R
Write to AM14. When the data is written, the written data is read out by the RAM test logic circuit 15 and is output from the LSI output edge pin 16 to the tester 17.
Is output to The tester 17 extracts a failure of the RAM 14 by comparing the read data with an expected value.

[0006] The test method according to the prior art described above uses L
As the operating speed of the SI increases, a tester capable of operating at a higher speed must be prepared accordingly.

FIG. 6 shows a RAM mounted on an LSI,
BIST (Built In) provided inside the LSI
FIG. 2 is a diagram illustrating a configuration of a conventional technique for performing a diagnostic test using a Self Test (Self Test) circuit. Next, the conventional technique will be described. 6, reference numeral 19 denotes a random pattern generation circuit, reference numeral 21 denotes an output buffer, and other reference numerals are the same as those in FIG.

FIG. 6 shows an example of the RAM 14 to be tested.
Pattern generator 19 which is a circuit for generating random test data inside an LSI 12 having
This is an example in which a BIST circuit is provided which is configured to collect data read from the RAM 14 and to perform compression or comparison with an expected value.

In FIG. 6, a random pattern generating circuit 19 generates test data having the operating frequency of the LSI 12 and writes the generated test data into the RAM 14. The output buffer 21
The data written in the AM 14 is collected, and a failure of the RAM 14 is extracted by comparing the data with an expected value.

As described above, the RAM included in the LSI
In any case, the conventional technology for performing the high-speed diagnostic test requires a tester that operates at the same frequency as the operating frequency of the LSI or a high-speed BIST circuit that can operate at the same frequency as the operating frequency of the LSI. come.

[0011]

The test method according to the prior art performed by connecting the above-described tester is based on a high-speed RAM provided inside the LSI as the speed of the LSI increases.
There is also a problem that the tester required to perform the diagnosis of the above needs to be speeded up, and as a result, the tester becomes expensive and costly.

A conventional test method in which a BIST circuit is provided inside an LSI to perform a test uses a BIST circuit which is a test circuit provided inside the LSI. Must be provided inside the LSI, and the BIST circuit occupies a large area in the chip and increases the so-called overhead as the BIST circuit that operates at high speed is to be constructed. However, there is a problem that a part of the LSI that can be used for realizing the original operation specifications is squeezed or a chip area becomes large.

An object of the present invention is to solve the above-mentioned problems of the prior art, and to diagnose a RAM in an LSI at a high speed by using a low-speed tester or a low-speed BIST circuit. And to provide an LSI diagnostic method and an LSI.

[0014]

According to the present invention, an object of the present invention is to provide a RAM for reading and writing a RAM mounted on an LSI at an operating clock frequency of the LSI to detect a failure of the RAM.
In the diagnostic method of M, a tester operating at a frequency of 1 / t (t is an integer of 2 or more) of the operating clock frequency of the LSI uses a t
The bits are input to the LSI in parallel, and the parallel-serial conversion circuit is incorporated in the RAM test circuit mounted on the LSI or connected to the RAM test circuit.
A serial-parallel conversion circuit that converts test data that is switched at an LSI operating clock frequency and writes the test data into the RAM, and that incorporates the test data read from the RAM into the RAM test circuit or connected to the RAM test circuit This is achieved by reading out to the tester as t parallel test data converted to a frequency of 1 / t of the operating clock frequency of the LSI, which is the operating clock frequency of the tester, and extracting a fault in the RAM.

The object of the present invention is to provide a method of diagnosing a RAM in which a RAM mounted on an LSI is read and written at an operating clock frequency of the LSI to isolate a failure of the RAM.
BI built in an LSI that operates at a frequency of 1 / t (t is an integer of 2 or more) of the operating clock frequency of the SI
The ST circuit generates, in parallel, t bits of data for setting a value to be used for the diagnosis of the RAM, and converts the generated t-bit data into test data that is switched at the operating clock frequency of the LSI by a parallel-serial conversion circuit. Then, the test data read from the RAM is converted into 1 / t of the operation clock frequency of the LSI, which is the operation clock frequency of the BIST, by the serial-parallel conversion circuit. This is achieved by reading out to the BIST circuit as parallel test data and extracting a failure in the RAM.

Further, the above object is achieved by generating the above-mentioned LSI operation clock by a PLL circuit based on a clock having a lower frequency than the externally input LSI operation clock.

As described above, the LSI which is provided with the RAM inside in which the diagnosis of the RAM is performed is one of the operating clock frequencies of the LSI provided for testing the RAM.
A parallel-serial conversion circuit for converting the t-bit parallel data at the operating speed of / t into write data to the RAM at the operating clock frequency of the LSI, and the t-bit data read from the RAM at the operating clock frequency of the LSI. L
And a serial-parallel conversion circuit for converting the data into t-bit parallel data at an operation speed of 1 / t of the operation clock frequency of the SI.

[0018]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a method for diagnosing a RAM according to the present invention;

FIG. 1 shows an RA according to a first embodiment of the present invention.
It is a figure explaining the diagnostic method of M. In FIG. 1, 2
4 and 25 are LSI input pins. 27 is a parallel-serial conversion circuit, 30 is a serial-parallel conversion circuit, 31,
32 is an LSI output pin, 34 is a clock pin, 35 is P
This is an LL circuit, and other symbols are the same as those in FIG.
The first embodiment of the present invention shown in FIG. 1 uses a tester having a low operating frequency of １ ／ of the operating frequency of the LSI, and
It is an example in the case of diagnosing AM.

A first embodiment of the present invention is a RAM in the LSI 12 in the example of the prior art described with reference to FIG.
A parallel-serial conversion circuit 27 for performing frequency conversion and a serial-parallel conversion circuit 30 are provided inside the test logic circuits 13 and 15 for the present invention.
A PLL circuit 35 for converting the operating speeds (operating frequencies) of 0 and 17 and the operating speed (operating frequency) of the LSI 12 is provided, and the testers 10 and 17 are connected to diagnose the RAM 14.

In FIG. 1, testers 10 and 17 are LS
It may have an operation speed that is half the operation speed of I12. Then, the tester 10 operating at half the operating frequency of the LSI 12 puts data 1 into the LSI input pin 24,
Data 2 is input to the SI input pin 25 in synchronization with the clock of the tester 10. Data 1 and 2 are 1
Is a bit.

RAM test logic circuit 13 in LSI 12
The parallel-to-serial conversion circuit 27 incorporated in the LSI converts the data input from the input pins 24 and 25 into the LSI 12
Is converted to serial data switched by the clock of R
AM1 cyclically L in order of data 1 and data 2
Writing is performed by the clock of SI12. The RAM test logic circuit 15 reads the data 1 and data 2 written in the RAM 14 in synchronization with the clock of the LSI 12,
The serial-parallel conversion circuit 30 in the AM test logic circuit 15 outputs the data 1 to the LSI output pin 31 and the data 2 to the LSI output pin 32 so that the read data 1 and 2 are switched by the clock of the tester 17. And the tester 17 reads the data. The tester 17 compares the read data with the expected value, and
14 faults are isolated.

According to the embodiment of the present invention shown in FIG. 1 described above, the RAM 14 is tested by reading and writing data at the operating speed of the LSI 12.
The operation speed of the RAM test logic circuit 1 in the LSI 12
Since the parallel-serial conversion circuit 27 and the serial-parallel conversion circuit 30 are provided in 3 and 15, the LSI 1
In other words, half of the operation speed of 2 is sufficient.

In the above-described operation, the clock of the LSI 12 can be used by generating the clock of the double frequency by the PLL circuit 35 from the clock of the tester supplied from the clock pin 34 by the tester.
Further, in the above-described embodiment of the present invention, the diagnosis of the RAM is described assuming that the operation speed of the tester is 動作 of the operation speed of the LSI. The diagnosis of the RAM may be performed at an operation speed of 1 / t (t is an arbitrary integer of 2 or more) of the speed. In this case, the testers 10 and 17 supply the t data to the LSI 12 and transmit the t data to the LSI 12.
From the I12
The parallel-serial conversion circuit 27 in the M test logic circuit 13 cyclically serializes t data into L
The data of the operating speed of the SI 12 is written into the RAM 14,
The serial-parallel conversion circuit 30 in the RAM test logic circuit 15 converts the data read from the RAM 14 into t
What is necessary is just to make it output in parallel to pieces of data. In this case, the PLL circuit 35 may generate a clock having a frequency t times the frequency of the clock from the tester, and output this clock as an LSI clock to a constituent circuit in the LSI.

The above-described embodiment of the present invention employs a parallel
Serial conversion circuit and serial-parallel conversion circuit
Although described as being provided in the AM test logic circuit, in the present invention, the parallel-serial conversion circuit and the serial-parallel conversion circuit may be provided between the RAM test logic circuit and the input pin and the output pin in the LSI.

FIG. 2 shows an RA according to a second embodiment of the present invention.
It is a figure explaining the diagnostic method of M. 2 are the same as those in FIGS. 1 and 6. The second embodiment of the present invention shown in FIG. 2 uses a BIST circuit that operates at a low operating frequency that is half the operating frequency of an LSI.
It is an example in the case of diagnosing AM.

The second embodiment of the present invention is the same as the prior art example described with reference to FIG. 6 except that the random pattern generator 19 in the LSI 12 and the RAM 14 and the RA
A parallel-serial conversion circuit 27 for performing frequency conversion for the present invention and a serial-parallel conversion circuit 30 are provided between the M14 and the output buffer 21.
Operating speed (operating frequency) of the random pattern generator 19
A PLL circuit 35 is provided for conversion between the data and the operating speed (operating frequency) of the LSI 12, and the RAM 14 is diagnosed.

In FIG. 2, a random pattern generation circuit 19 generates test data 1 and 2 by operating with a low-speed clock (hereinafter, referred to as a BIST clock) having a half of the operating frequency of the LSI 12, and generates the generated data 1. To signal line 3
8, the data 2 is output at a timing synchronized with the signal line 39BIST clock. When receiving the data 1 and 2 described above, the parallel-serial conversion circuit 27
Is converted to serial data switched by the clock of R
AM1 cyclically L in order of data 1 and data 2
Writing is performed by the clock of SI12. The serial-parallel conversion circuit 30 reads out the data 1 and data 2 written in the RAM 14 in synchronization with the clock of the LSI 12, and outputs the read data 1 and 2 to the output buffer 2.
Data 1 is connected to signal line 4 so that
4, the data 2 is alternately output to the signal line 45 and is read into the output buffer 21. The output buffer 21 extracts a failure of the RAM 14 by compressing the read data or comparing the read data with an expected value.

In this embodiment, as in the first embodiment, the operating speed of the random pattern generator 19 and the output buffer 21 is set to one of the operating speeds of the LSI.
The diagnosis of the RAM can be performed as the operation speed of / t.

FIG. 3 is a block diagram showing the configuration of the parallel-serial conversion circuit used in the embodiment of the present invention described with reference to FIGS. 1 and 2, and a time chart for explaining its operation. This will be described below. In FIG.
48 to 51 are input signal lines, 52 is a clock input line, 53
Is a selector, and other symbols are the same as those in FIGS.

The parallel-to-serial conversion circuit 27 is shown in FIG.
As shown in (a), the selector 53 is configured to include a selector 53 as a main component. The selector 53 is connected to t input signal lines 48 to 51 and connected to the selector 53.
Is connected to a clock input line to which a clock signal of an operating frequency of an LSI for controlling the clock is input. As shown in FIG. 3B, tester 1 is connected to t input signal lines 48 to 51.
0 or test data 1 to t from the random pattern generator 19 are input in parallel in synchronization with the operation clock of the tester 10 or the random pattern generator 19. The data 1 to t input in parallel are updated every operation clock of the tester 10 or the random pattern generator 19.

The selector 53 is controlled by a clock signal of the operating frequency of the LSI input from the clock input line 52, and as shown in FIG.
The data 1 to t input from 1 are sequentially taken in cyclically by a clock signal of the operating frequency of the LSI, output to the RAM 14, and written to the RAM 14. As described above, since the operation clock of the tester 10 or the random pattern generator 19 is 1 / t of the clock of the operation frequency of the LSI, data 1 to t
While LS is being input to the selector by the operation clock of the tester 10 or the random pattern generator 19,
The data is serially output from the selector 53 by the clock of I. After the data t is output, the data 1 from the tester 10 or the random pattern generator 19 is output.
Since ~ t is updated, data 1 ~ t are serially output from selector 53 again. As a result, data 1 to t are written into the RAM 14 at the operation speed of the LSI.

In the first and second embodiments of the present invention, the use of the parallel-serial conversion circuit 27 as described above allows the use of 1/1/3 of the clock of the operating frequency of the LSI.
The data input in synchronization with the clock of frequency t
Converts to data switched by SI clock and RAM
14 can be written.

FIG. 4 is a block diagram showing the configuration of the serial-parallel conversion circuit used in the embodiment of the present invention described with reference to FIGS. 1 and 2, and a time chart for explaining its operation. This will be described below. In FIG.
Reference numerals 57, 59 to 62 denote flip-flops (FF), 58 denotes an enable signal line, and the other reference numerals are the same as those in FIGS.

The serial-to-parallel conversion circuit 30 corresponds to FIG.
As shown in FIG. 1A, a plurality of FFs are provided, and data read from the RAM 14 is input to the FFs 57 and FF60. Between the FF 57 and the FF 59, t-1 FFs including the FF 57 and the FF 59 are serially connected so as to form a shift register, and their outputs are connected to the FFs 61 to 62. The FFs 60 to 62 are t FFs to which the enable signal lines are connected.

The RAM 14 is sequentially read by the LSI clock, and data 1 to t are input to the serial-parallel conversion circuit 30 according to the LSI clock as shown in FIG. When data 1 to data t-1 are sequentially read out, these data are sequentially shifted into a shift register including FFs 57 and 59 in accordance with the LSI clock, and when data t-1 is read out, data t1 is read out. Are taken into the FF 59 and the data 1 is taken into the FF 57. By setting the enable signal on the enable signal line 58 to the high level at the timing when the data t is read, the data 1 to the data t
62 to FF60. FF62 ~
The data fetched by the FF 60 is read out to the tester 17 or the output buffer 21 in parallel by a clock having a speed of 1 / t of the LSI clock.

In the first and second embodiments of the present invention, by using the serial-parallel conversion circuit 30 as described above, t pieces of data written in the RAM by the clock of the operating frequency of the LSI are used. Can be output in synchronization with a clock having a frequency of 1 / t of the LSI clock.

According to the above-described two embodiments of the present invention, the parallel-serial conversion circuit and the serial-parallel conversion circuit are provided on the input side and the output side of the RAM, so that the operation speed of the tester or the BIST circuit can be controlled by the LSI. A test can be performed by reading / writing data from / to the RAM at the operating speed of the LSI as 1 / t of the clock.

Thus, according to the above-described two embodiments of the present invention, the circuit configuration of the tester can be simplified to reduce the cost, or the area of the chip occupied by the BIST circuit can be reduced. Thus, the LSI chip can be efficiently used for realizing the original operation specifications of the LSI, and the chip area of the entire LSI can be reduced.

[0040]

As described above, according to the present invention, L
A test of the RAM in the LSI can be performed at a high speed with a tester having an operating frequency of 1 / t of the operating frequency of the SI, so that it is not necessary to obtain a high-speed and expensive tester, and the cost can be reduced. Since the operating frequency of the BIST logic circuit can be set to 1 / t of the operating frequency of the LSI, it is possible to reduce the overhead of wiring and gate amount to the chip area of the LSI.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method for diagnosing a RAM according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a method for diagnosing a RAM according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a parallel-serial conversion circuit used in an embodiment of the present invention, and a time chart explaining the operation thereof.

FIG. 4 is a block diagram showing a configuration of a serial-parallel conversion circuit used in an embodiment of the present invention, and a time chart explaining the operation thereof.

FIG. 5 is a diagram illustrating a configuration of a conventional technology for performing a diagnostic test on a RAM mounted on an LSI using a tester having the same operating frequency as the LSI.

FIG. 6 is a diagram illustrating a configuration of a conventional technique for performing a diagnostic test on a RAM mounted on an LSI using a BIST circuit provided inside the LSI.

[Explanation of symbols]

 10, 17 tester 11 LSI input edge pin 12 LSI 13, 15 RAM test logic circuit 14 RAM 16 LSI output edge pin 19 random pattern generation circuit 21 output buffer 24, 25 LSI input pin 27 parallel-serial conversion circuit 30 serial-parallel conversion circuit 31 , 32 LSI output pin 34 clock pin 35 PLL circuit 48-51 input signal line 52 clock input line 53 selector 57, 59-62 flip-flop (FF) 58 enable signal line

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tetsuya Takahashi 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture Inside Nichi Information Technology Co., Ltd. F term in the server division (reference) 2G032 AA07 AB02 AC03 AD05 AE08 AG07 AL16 5L106 AA01 AA02 AA15 DD00 DD04 FF01 GG00

Claims (4)

[Claims] 1. A RAM mounted on an LSI is integrated with an LSI.
In the method of diagnosing a RAM which extracts a failure of the RAM by reading and writing at the operating clock frequency of the RAM, the tester which operates at a frequency of 1 / t (t is an integer of 2 or more) of the operating clock frequency of the LSI is used for the diagnosis of the RAM. T bits of data for setting the value to be set are input to the LSI in parallel and incorporated in the RAM test circuit mounted on the LSI or
The parallel-serial conversion circuit connected to the AM test circuit converts the data into test data that is switched at the LSI operation clock frequency and writes the test data into the RAM.
The test data read from the RAM is converted by the serial-parallel conversion circuit incorporated in the RAM test circuit or connected to the RAM test circuit into 1/1 / LSI operation clock frequency, which is the tester operation clock frequency.
A diagnostic method for a RAM, comprising: reading out as t parallel test data converted to a frequency of t into a tester to extract a RAM failure; 2. The method according to claim 1, wherein the RAM mounted on the LSI is an LSI.
A RAM diagnostic method for detecting a failure in a RAM by reading and writing at an operating clock frequency of the BIST circuit incorporated in the LSI operating at a frequency of 1 / t (t is an integer of 2 or more) of the operating clock frequency of the LSI And RAM
T bits of data for setting values to be used for the diagnosis are generated in parallel, and the generated t bits of data are generated in parallel.
The serial conversion circuit converts the data into test data which is switched at the operation clock frequency of the LSI and writes the test data into the RAM. The test data read from the RAM is converted by the serial-parallel conversion circuit into the LSI which is the operation clock frequency of the BIST. Of the operating clock frequency of
A RAM diagnostic method characterized by reading out t parallel test data converted to a frequency of / t into a BIST circuit to isolate a RAM failure. 3. The RAM according to claim 1, wherein the operation clock of the LSI is generated by a PLL circuit based on a clock having a lower frequency than the operation clock of the LSI input from the outside. Diagnostic method. 4. An LSI comprising a RAM therein
LS provided for testing the RAM
A parallel-serial conversion circuit for converting t-bit parallel data at an operating speed of 1 / t of the operating clock frequency of I into write data to the RAM at the operating clock frequency of the LSI, and reading from the RAM at the operating clock frequency of the LSI; And a serial-parallel conversion circuit for converting the t-bit data into t-bit parallel data having an operation speed of 1 / t of the operation clock frequency of the LSI.