JP2004111029A - Semiconductor integrated circuit and memory testing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of testing a high-speed memory at a real operation speed even when the operational speed of a BIST circuit is restricted. <P>SOLUTION: In order to test a memory 105 operated by a first clock CK1, this circuit is provided with a first test pattern generation section 101 operated by a second clock CK2 to generate test data, and a second test pattern generation section 102 operated by a third clock CK3 which is the inverted clock of the second clock CK2 to generate test data. Further, a test data selection section 104 is disposed to selectively output one of test data output from the first and second test pattern generation sections 101 and 102 based on the signal value of the second clock CK2, and input it as test data to a memory 105. The frequency of the second clock CK2 is 1/2 of that of the first clock. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a semiconductor integrated circuit capable of testing a memory by a built-in self test, and more particularly to a semiconductor integrated circuit capable of testing a memory that operates at high speed and a method of testing the memory.

In recent years, with the progress of LSI technology, the speed of operation of memories mounted on semiconductor integrated circuits has been increasing. To test these memories, a built-in self test (so-called BIST) is generally used.

FIG. 21 shows a circuit block for performing BIST. In FIG. 21, reference numeral 401 denotes a BIST circuit, and reference numeral 402 denotes a memory to be subjected to the BIST. The memory 402 receives a first clock (Memory @ Clock), and the BIST circuit 401 receives a second clock (BIST @ Clock). The memory 402 has a normal data rate memory operating in synchronization with either one of the rising and falling edges of the clock, and a double data memory operating in synchronization with both the rising and falling edges of the clock. There is a rate memory.

(4) Address and data inputs and control signals such as a write enable signal are input from the BIST circuit 401 to the memory 402. Further, an output (Data-Out) of the memory 402 is input to the BIST circuit 401 and a normal logic circuit. Then, an expected value comparison circuit in the BIST circuit 401 compares the data input from the memory 402 with the expected value, thereby making a pass / fail determination.

Here, FIG. 22 shows a clock timing when the BIST is applied to the memory 402 when the memory 402 is a double data rate (DDR; Double @ Data @ Rate) memory. FIG. 22 shows the first clock (Memory @ Clock), the second clock (BIST @ Clock), and the data output Data-Out of the memory 402.

The memory 402, which is a DDR memory, can operate in synchronization with both rising and falling edges of the first clock (Memory @ Clock). Therefore, for example, when a read operation is performed, data is output at the rising edge of the first clock (Memory @ Clock) at time t1 in FIG. 22, and the rising of the first clock (Memory @ Clock) at time t2. At the falling edge, the next data is output.

In the BIST circuit 401 for testing the memory 402, the DDR memory is tested at the actual operation speed by setting the rising edge of the second clock (BIST @ Clock) to times t1, t2,..., Tn. be able to.

As described above, in the BIST circuit 401 for testing the high-speed memory 402, it is necessary to increase the operation speed of the BIST circuit 401 according to the operation speed of the memory 402.
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{Circle around (2)} When the memory operates at a double speed of the clock frequency like the DDR memory described above, or when a memory operating at a very high speed is tested at the actual operation speed, the BIST circuit itself needs to operate at a high speed. However, there is a problem that it is difficult to realize a BIST circuit because the operating frequency is very high.

In addition, for high-speed operation, a cell having a high driving capability is required, and there is a problem that the BIST circuit area increases. In addition, for high-speed operation, power consumption increases because the clock frequency increases. There was a problem.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor integrated circuit capable of performing a high-speed memory test at an actual operation speed even if the operation speed of the BIST circuit is suppressed. is there.

Another object of the present invention is to provide a memory test method capable of performing a high-speed memory test at an actual operation speed even if the operation speed of the BIST circuit is suppressed.

In order to solve the above problems, a semiconductor integrated circuit according to a first aspect of the present invention has a memory that operates with a first clock and a second clock that operates with a second clock having half the frequency of the first clock. A first test pattern generator that generates test data, a second test pattern generator that operates on a third clock that is an inverted clock of the second clock, and generates second test data; One of the first and second test data output from the test pattern generation unit and the second test pattern generation unit, respectively, using either the signal value of the second clock or the signal value of the third clock. And a test data selection section for selectively outputting the test data in accordance with one of them and inputting it as third test data to the memory.

According to this configuration, the first test pattern generation unit generates the first test data in accordance with the second clock having a half frequency of the first clock supplied to the memory. Further, the second test pattern generator generates second test data according to the third clock obtained by inverting the second clock. Then, one of the first and second test data is selected by the test data selector in accordance with one of the signal value of the second clock and the signal value of the third clock, and the third data is stored in the memory. As test data. Thus, the memory test can be performed at the actual operation speed even when the operation speed of the first and second test pattern generation units and the test data selection unit is suppressed to の of the operation speed of the memory. Since the operation speeds of the first and second test pattern generation units and the test data selection unit may be low, the driving capability may be small, and therefore the circuit area may be small, and the power consumption may be reduced.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit which operates with a first clock and a second clock which operates with a second clock having a half frequency of the first clock and generates first test data. A test pattern generator, a second test pattern generator that operates with a second clock and generates second test data, and a first test pattern generator and a second test pattern generator that are output from the first and second test pattern generators, respectively. And a test data selector for selectively outputting one of the first and second test data according to the signal value of the second clock, and inputting it as third test data to the memory. .

According to this configuration, the first test pattern generation unit generates the first test data in accordance with the second clock having a half frequency of the first clock supplied to the memory. Further, the second test data is generated by the second test pattern generator in accordance with the second clock. Then, one of the first and second test data is selected by the test data selection unit according to the signal value of the second clock, and is input to the memory as the third test data. Thereby, the same operation and effect as those of the first invention are exerted.

A semiconductor integrated circuit according to a third aspect of the present invention includes a memory that operates with a first clock and a test pattern generation that operates with a second clock having half the frequency of the first clock to generate first test data. Unit, an LSB0 processing unit that adds a numerical value 0 as the least significant bit to the first test data generated by the test pattern generation unit to generate second test data, and a first LSB0 processing unit that is generated by the test pattern generation unit. LSB1 processing unit that generates a third test data by adding a numerical value 1 as the least significant bit to the test data, and one of the second and third test data output from the LSB0 processing unit and the LSB1 processing unit, respectively. A test data selecting unit for selectively outputting one of the two in accordance with the signal value of the second clock and inputting the selected test data to the memory as fourth test data.

According to this configuration, the first test data is generated by the test pattern generator in accordance with the second clock having a half frequency of the first clock applied to the memory. Further, the LSB0 processing unit adds a numerical value 0 as the least significant bit to the first test data to generate second test data, and the LSB1 processing unit adds a numerical value 1 as the least significant bit to the first test data. To generate third test data. Then, one of the second and third test data is selectively output by the test data selector in accordance with the signal value of the second clock. Thus, even when the operation speeds of the test pattern generation unit, the LSB0 processing unit, the LSB1 processing unit, and the test data selection unit are suppressed to half the operation speed of the memory, the memory test can be performed at the actual operation speed. . Since the operation speeds of the test pattern generation unit, the LSB0 processing unit, the LSB1 processing unit and the test data selection unit may be low, the driving capability may be small, and therefore the circuit area may be small and the power consumption may be reduced. .

In the configuration of the third aspect, a delay circuit that delays the second clock and provides the delayed clock to the test data selection unit may be provided.

According to this configuration, since the second clock is delayed, a hold time can be secured for the first clock, and a stable test pattern can be applied to a memory that operates at high speed.

A semiconductor integrated circuit according to a fourth aspect of the present invention is a memory that operates with a first clock and a test pattern generation that operates with a second clock having half the frequency of the first clock to generate first test data. Unit, an LSB0 processing unit that adds a numerical value 0 as the least significant bit to the first test data generated by the test pattern generation unit to generate second test data, and a first LSB0 processing unit that is generated by the test pattern generation unit. A LSB1 processing unit that adds a numerical value 1 as the least significant bit to the test data to generate third test data, and a clock selection unit that can select one of a second clock and an inverted clock of the second clock And one of the second and third test data output from the LSB0 processing unit and the LSB1 processing unit, respectively, according to the output of the clock selection unit. And, and a test data selecting section for inputting a fourth test data into memory.

According to this configuration, one of the second clock and the inverted clock of the second clock is selected by the clock selection unit, and the second and third tests are performed by the test data selection unit in accordance with the selected clock. Since either one of the data is selected, the timing of selecting the second and third test data can be reversed by reversing the selection state of the clock selection unit. As a result, the quality of the test pattern is improved, and the increment and decrement of the address signal can be selectively performed when the address signal is provided as the test pattern. Others are the same as the third invention.

According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit, comprising: a memory which operates on a first clock; A second output data output from the storage element operated by the second clock, and a third output data output from the memory immediately after the first output data. And an expected value comparing unit that compares each with a predetermined expected value.

According to this configuration, the first output data output from the memory in synchronization with the first clock is fetched by the inverted clock of the second clock having half the frequency of the first clock applied to the memory. . Then, the second output data output from the storage element and the third output data output from the memory immediately after the first output data are compared with each other in the expected value comparing section by the second clock in a predetermined manner. Compare with expected value. Thus, the memory test can be performed at the actual operation speed even when the operation speed of the storage element and the expected value comparison unit is suppressed to half of the operation speed of the memory. Since the operation speed of the storage element and the expected value comparison unit may be low, the driving capability may be small, and therefore, the circuit area may be small, and the power consumption may be reduced.

A semiconductor integrated circuit according to a sixth aspect of the present invention includes a double data rate memory operating with a first clock and a first data operating with a second clock having the same frequency as the first clock to generate first test data. A test pattern generator, a second test pattern generator that operates on a third clock that is an inverted clock of the second clock, and generates second test data, a first test pattern generator, and a second test pattern generator. One of the first and second test data respectively output from the test pattern generation unit is selectively output in accordance with one of the signal value of the second clock and the signal value of the third clock. And a test data selector for inputting the third test data to the double data rate memory.

According to this configuration, the first test pattern generation unit generates the first test data according to the second clock having the same frequency as the first clock supplied to the double data rate memory. Further, the second test pattern generator generates second test data according to the third clock obtained by inverting the second clock. Then, one of the first and second test data is selected by the test data selector in accordance with one of the signal value of the second clock and the signal value of the third clock, and the double data rate memory is selected. Is input as the third test data. Thus, even when the operation speeds of the first and second test pattern generation units and the test data selection unit are suppressed to the same as the operation speed of the double data rate memory, the test of the double data rate memory is performed at the actual operation speed. Can be. Since the operation speeds of the first and second test pattern generation units and the test data selection unit may be low, the driving capability may be small, and therefore the circuit area may be small, and the power consumption may be reduced.

A semiconductor integrated circuit according to a seventh aspect of the present invention includes a double data rate memory that operates with a first clock and a first data that operates with a second clock having the same frequency as the first clock to generate first test data. A test pattern generator, a second test pattern generator that operates with a second clock and generates second test data, and a first test pattern generator and a second test pattern generator that are output from the first and second test pattern generators, respectively. And a test data selecting unit for selectively outputting one of the first and second test data according to the signal value of the second clock and inputting it as third test data to the double data rate memory. Have.

According to this configuration, the first test pattern generation unit generates the first test data according to the second clock having the same frequency as the first clock supplied to the double data rate memory. Further, the second test data is generated by the second test pattern generator in accordance with the second clock. Then, one of the first and second test data is selected by the test data selection unit according to the signal value of the second clock, and is input to the double data rate memory as the third test data. Thus, even when the operation speeds of the first and second test pattern generation units and the test data selection unit are suppressed to the same as the operation speed of the double data rate memory, the test of the double data rate memory is performed at the actual operation speed. Can be. Since the operation speeds of the first and second test pattern generation units and the test data selection unit may be low, the driving capability may be small, and therefore the circuit area may be small, and the power consumption may be reduced.

A semiconductor integrated circuit according to an eighth aspect of the present invention provides a double data rate memory that operates with a first clock and a test pattern generation that operates with a second clock having the same frequency as the first clock to generate first test data. Unit, an LSB0 processing unit that adds a numerical value 0 as the least significant bit to the first test data generated by the test pattern generation unit to generate second test data, and a first LSB0 processing unit that is generated by the test pattern generation unit. LSB1 processing unit that generates a third test data by adding a numerical value 1 as the least significant bit to the test data, and one of the second and third test data output from the LSB0 processing unit and the LSB1 processing unit, respectively. One of the test data is selectively output according to the signal value of the second clock, and is input to the double data rate memory as the fourth test data. And a selection unit.

According to this configuration, the first test data is generated by the test pattern generator in accordance with the second clock having the same frequency as the first clock supplied to the double data rate memory. Further, the LSB0 processing unit adds a numerical value 0 as the least significant bit to the first test data to generate second test data, and the LSB1 processing unit adds a numerical value 1 as the least significant bit to the first test data. To generate third test data. Then, one of the second and third test data is selectively output by the test data selector in accordance with the signal value of the second clock. Thus, even when the operation speeds of the test pattern generation unit, the LSB0 processing unit, the LSB1 processing unit, and the test data selection unit are suppressed to the same as the operation speed of the double data rate memory, the test of the double data rate memory is performed at the actual operation speed. It can be carried out. Since the operation speeds of the test pattern generation unit, the LSB0 processing unit, the LSB1 processing unit and the test data selection unit may be low, the driving capability may be small, and therefore the circuit area may be small and the power consumption may be reduced. .

In the configuration of the eighth invention, a delay circuit that delays the second clock and provides the delayed clock to the test data selection unit may be provided.

According to this configuration, since the second clock is delayed, a hold time can be secured for the first clock, and a stable test pattern can be applied to the double data rate memory operating at high speed. it can.

A semiconductor integrated circuit according to a ninth aspect of the present invention is a double data rate memory that operates with a first clock and a test pattern generation that operates with a second clock having the same frequency as the first clock to generate first test data. Unit, an LSB0 processing unit that adds a numerical value 0 as the least significant bit to the first test data generated by the test pattern generation unit to generate second test data, and a first LSB0 processing unit that is generated by the test pattern generation unit. A LSB1 processing unit that adds a numerical value 1 as the least significant bit to the test data to generate third test data, and a clock selection unit that can select one of a second clock and an inverted clock of the second clock And one of the second and third test data output from the LSB0 processing unit and the LSB1 processing unit in response to the output of the clock selection unit. Selectively outputting Te, and a test data selecting section for inputting the double data rate memory as a fourth test data.

According to this configuration, one of the second clock and the inverted clock of the second clock is selected by the clock selection unit, and the second and third tests are performed by the test data selection unit in accordance with the selected clock. Since either one of the data is selected, the timing of selecting the second and third test data can be reversed by reversing the selection state of the clock selection unit. As a result, the quality of the test pattern is improved, and the increment and decrement of the address signal can be selectively performed when the address signal is provided as the test pattern. Others are the same as the eighth invention.

A semiconductor integrated circuit according to a tenth aspect is a semiconductor integrated circuit, comprising: a double data rate memory operated by a first clock; and a first output data output from the double data rate memory in synchronization with the first clock. A storage element which is fetched by a second clock having the same frequency as that of the second clock, a second output data which is operated by the second clock and is output from the storage element, and which is output from the double data rate memory immediately after the first output data And an expected value comparing unit for comparing the third output data with a predetermined expected value.

According to this configuration, the first output data output from the double data rate memory in synchronization with the first clock by the inverted clock of the second clock having the same frequency as the first clock applied to the double data rate memory Take in. Then, the expected value comparing section compares the second output data output from the storage element and the third output data output from the double data rate memory immediately after the first output data by the second clock. Each is compared with a predetermined expected value. Thus, the test of the double data rate memory can be performed at the actual operation speed even when the operation speed of the storage element and the expected value comparison unit is suppressed to the same as the operation speed of the double data rate memory. Since the operation speed of the storage element and the expected value comparison unit may be low, the driving capability may be small, and therefore, the circuit area may be small, and the power consumption may be reduced.

A memory test method according to an eleventh aspect of the present invention is a test method for a memory that operates with a first clock, in which first test data is generated with a second clock having a half frequency of the first clock. Generating second test data with a third clock which is an inverted clock of the second clock, and converting one of the first and second test data into a signal value of the second clock and a third clock. Selected according to any one of the above-mentioned signal values and input to the memory as the third test data.

According to this method, the test of the memory operated by the first clock can be executed by the second clock having a half frequency of the first clock. At this time, since the frequency of the second clock may be low, the driving capability of the circuit for performing the test may be small, and therefore, the circuit area may be small, and the power consumption for performing the test may be reduced.

A memory test method according to a twelfth aspect of the present invention is a test method for a memory that operates with a first clock, wherein first test data is generated with a second clock having a half frequency of the first clock, A second test data is generated by adding a numerical value 0 as the least significant bit to the first test data, and a third test data is generated by adding a numerical value 1 as the least significant bit to the first test data. , One of the second and third test data is selected in accordance with the signal value of the second clock and input to the memory.

According to this method, the same operation and effect as those of the eleventh invention can be obtained.

A memory test method according to a thirteenth aspect is a test method for a memory that operates on a first clock, wherein the first data output from the memory in synchronization with the first clock is set to one of the first clocks. / 2 is held as second data by a second clock having a frequency of / 2, and the second data and the third data output from the memory immediately after the first data in synchronization with the first clock are stored. , And a second clock, respectively.

According to this method, the same operation and effect as those of the eleventh invention can be obtained.

A memory test method according to a fourteenth aspect is a test method for a double data rate memory operating with a first clock, wherein first test data is generated with a second clock having the same frequency as the first clock. Generating second test data with a third clock which is an inverted clock of the second clock, and converting one of the first and second test data into a signal value of the second clock and a third clock. And input to the double data rate memory as the third test data.

According to this method, the test of the double data rate memory operating with the first clock can be executed with the second clock having the same frequency as the first clock. At this time, the frequency of the second clock does not need to be twice as high as that of the first clock, and the frequency of the second clock may be low. Therefore, the driving capability of the circuit for performing the test may be small. Therefore, the circuit area can be reduced, and the power consumption for performing the test can be reduced.

A test method for a memory according to a fifteenth invention is a test method for a double data rate memory operating with a first clock, wherein first test data is generated with a second clock having the same frequency as the first clock. Adding a numerical value 0 as the least significant bit to the first test data to generate second test data, and generating a third test data by adding a numerical value 1 as the least significant bit to the first test data Then, one of the second and third test data is selected in accordance with the signal value of the second clock and input to the double data rate memory.

According to this method, the same operation and effect as those of the fourteenth invention can be obtained.

A memory test method according to a sixteenth aspect of the present invention is a test method for a double data rate memory operating on a first clock, wherein first data output from the double data rate memory in synchronization with the first clock is: The second data is held as second data by a second clock having the same frequency as the first clock, and is output from the double data rate memory immediately after the second data and the first data in synchronization with the first clock. The third data is compared with predetermined expected values by the second clock.

According to this method, the same operation and effect as those of the fourteenth invention can be obtained.

In the first, second, sixth and seventh aspects of the present invention, a delay circuit for delaying the second clock and providing the delayed clock to the test data selector may be provided.

According to this configuration, since the second clock is delayed, a hold time can be secured for the first clock, and a stable test pattern can be applied to a memory that operates at high speed.

A semiconductor integrated circuit according to a seventeenth aspect of the present invention is a memory which operates with a first clock and a first which operates with a second clock having a frequency half of the first clock to generate first test data. A test pattern generator, a second test pattern generator that operates on a third clock that is an inverted clock of the second clock and generates second test data, and a second clock and a second clock. A clock selection unit that can select one of the inverted clocks, and one of the first and second test data output from the first test pattern generation unit and the second test pattern generation unit, respectively. A test data selection unit for selectively outputting the data in accordance with the output of the selection unit and inputting the third test data to the memory.

A semiconductor integrated circuit according to an eighteenth aspect of the present invention is a memory which operates with a first clock and a first which operates with a second clock having a half frequency of the first clock and generates first test data. A test pattern generation unit, a second test pattern generation unit that operates on the second clock and generates second test data, and selects one of the second clock and the inverted clock of the second clock A clock selection unit that selectively outputs one of the first and second test data output from the first test pattern generation unit and the second test pattern generation unit according to the output of the clock selection unit. And a test data selection unit for outputting the test data to the memory as third test data.

A semiconductor integrated circuit according to a nineteenth aspect of the present invention includes a double data rate memory that operates with a first clock, and a first data that operates with a second clock having the same frequency as the first clock to generate first test data. A test pattern generator, a second test pattern generator that operates on a third clock that is an inverted clock of the second clock and generates second test data, and a second clock and a second clock. A clock selection unit that can select one of the inverted clocks, and one of the first and second test data output from the first test pattern generation unit and the second test pattern generation unit, respectively. A test data selecting section for selectively outputting the third test data to the double data rate memory according to the output of the selecting section.

According to a twentieth aspect of the present invention, a semiconductor integrated circuit operates with a double data rate memory operating with a first clock and a first clock operating with a second clock having the same frequency as the first clock to generate first test data. A test pattern generation unit, a second test pattern generation unit that operates on the second clock and generates second test data, and selects one of the second clock and the inverted clock of the second clock A clock selection unit that selectively outputs one of the first and second test data output from the first test pattern generation unit and the second test pattern generation unit according to the output of the clock selection unit. And a test data selector for inputting the same as the third test data to the double data rate memory.

According to these configurations, one of the second clock and the inverted clock of the second clock is selected by the clock selection unit, and the first and second clocks are selected by the test data selection unit according to the selected clock. Since either one of the test data is selected, the timing of selecting the first and second test data can be reversed by reversing the selection state of the clock selection unit. As a result, the quality of the test pattern is improved, and the increment and decrement of the address signal can be selectively performed when the address signal is provided as the test pattern. Others are the same as the first, second, sixth or seventh invention.

In the above description, the memory means a memory having a normal data rate operating in synchronization with one of the rising edge and the falling edge of the clock, and the double data rate memory means the memory having the normal data rate. It means that it operates in synchronization with both falling edges.

According to the method for testing a semiconductor integrated circuit and a memory of the present invention, the above-described configuration enables a high-speed memory test to be performed at an actual operation speed even if the operation speed of the BIST circuit is suppressed.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a block diagram for describing a test method of a semiconductor integrated circuit and a memory according to the first embodiment of the present invention, and FIG. 2 is a timing chart of each unit in FIG.

In FIG. 1, reference numeral 101 denotes a first test pattern generator that operates in synchronization with the rising edge of the input clock. Reference numeral 102 denotes a second test pattern generator that operates in synchronization with the rising edge of the input clock. Reference numeral 103 denotes an inverter for generating an inverted clock. Reference numeral 104 denotes a test data selection unit. These constitute a BIST circuit. Reference numeral 105 denotes a memory having a normal data rate to be subjected to BIST, and operates in synchronization with a rising edge of an input clock.

(1) The first clock CK1 is a clock signal supplied to the memory 105. The second clock CK2 is a clock signal provided to the first test pattern generation unit 101, and has a frequency that is 1/2 of the first clock CK1. The third clock CK3 is a clock signal obtained by inverting the second clock CK2 by the inverter 103, and is a clock signal of the second test pattern generator 102.

As shown in the timing chart of FIG. 2, the first test pattern generation unit 101 synchronizes with the rising edge of the second clock CK2 to “000” at time t0, “010” at time t2, and “010” at time t4. The address signal TP1 of “100” and “110” is generated at time t6 as test data.

In addition, as shown in the timing chart of FIG. 2, the second test pattern generation unit 102 synchronizes with the rising edge of the third clock CK3 to “001” at time t1, “011” at time t3, and “011” at time t3. An address signal TP2 of “101” at t5 and “111” at time t7 is generated as test data.

The test data selection unit 104 converts the address signals TP1 and TP2 generated by the first test pattern generation unit 101 and the second test pattern generation unit 102 according to the logical value 0/1 of the second clock CK2. The test data is alternately selected and output as test data, that is, an address signal TP3. Note that the test data selection unit 104 may perform the selection operation according to the logical value 0/1 of the third clock CK3.

If the address signal TP1 is selected when the second clock CK2 has the logical value 1 and the address signal TP2 is selected when the second clock CK2 has the logical value 0, the address signal TP3 input as test data to the memory 105 at time t0 "000", "001" at time t1, "010" at time t2, "011" at time t3, "100" at time t4, "101" at time t5, "110" at time t6, and "110" at time t7. 111 ", and a test pattern (a series of address signals) can be generated in synchronization with the rising edge of the first clock CK1 of the memory 105.

As described above, according to the present embodiment, the first and second test pattern generation units 101 and 102 that operate respectively by the second clock CK2 and the third clock CK3 obtained by inverting the second clock CK2 are provided. And one of the outputs of the second test pattern generation units 101 and 102 is selected by the test data selection unit 104 in accordance with one of the states of the second and third clocks CK2 and CK3 and input to the memory 105. By employing such a configuration, it becomes possible to apply a test pattern to the memory 105 operating at twice the frequency of the first and second test pattern generation units 101 and 102 at the actual operation speed. That is, the memory 105 operating at a higher frequency can be tested without increasing the operating frequency of the first and second test pattern generators 101 and 102, which are BIST circuits. Therefore, the driving capability of the first and second test pattern generation units 101 and 102 for performing the BIST may be small, so that the circuit area may be small and the power consumption may be small.

When the memory 105 is a DDR memory, clock signals of the same frequency are input to the first clock CK1 applied to the DDR memory and the second clock CK2 applied to the BIST circuit, as shown in the timing chart of FIG. Thus, the test pattern can be input to the DDR memory in synchronization with both the rising edge and the falling edge of the clock CK1, and the same effect as in the present embodiment can be obtained. That is, the DDR memory can be tested without increasing the operating frequency of the first and second test pattern generation units, which are BIST circuits, twice. Therefore, the driving capability of the first and second test pattern generation units 101 and 102 for performing the BIST may be small, so that the circuit area may be small and the power consumption may be small.

Further, in the configuration of FIG. 1, the third clock CK3 obtained by inverting the second clock CK2 by the inverter 103 is supplied to the second test pattern generation unit 102. However, the second clock CK2 may be supplied as it is. , And the same address signal TP3 as when the third clock CK3 is supplied. In this case, the address signal TP2 is advanced by a half cycle of the second clock CK2 as compared with the timing of FIG.

(Embodiment 2)
FIG. 4 is a block diagram for explaining a method for testing a semiconductor integrated circuit and a memory according to the second embodiment of the present invention, and FIG. 5 is a timing chart.

Hereinafter, a method of testing a memory in the semiconductor integrated circuit shown in FIG. 4 will be described with reference to the flowchart of FIG.

In FIG. 4, reference numeral 201 denotes a test pattern generation unit that operates in synchronization with the rising edge of the input clock. Reference numeral 202 denotes an LSB0 processing unit, reference numeral 203 denotes an LSB1 processing unit, and reference numeral 204 denotes a test data selection unit. These constitute a BIST circuit. Reference numeral 205 denotes a memory having a normal data rate to be subjected to BIST, and operates in synchronization with a rising edge of an input clock.

(1) The first clock CK1 is a clock signal provided to the memory 205. The second clock CK2 is a clock signal provided to the test pattern generation unit 201, and has a frequency that is half that of the first clock CK1.

In FIG. 7, first, test pattern generation processing ST301 is performed. Test data is generated in the test pattern generation unit 201 in synchronization with the rising edge of the second clock CK2. Specifically, at time t0, {00} is generated as test data, that is, address signal TP0, at time t2, {01} is generated as address signal TP0, and at time t4, {10} is generated as address signal TP0. Is generated, and at time t6, {11} is generated as the address signal TP0.

Next, the LSB process ST302 is performed. That is, a process of adding the numerical value 0 or 1 as the least significant bit to the address signal TP0 generated by the test pattern generation unit 201 to generate the address signals TP1 and TP2 is performed.

{Specifically, the LSB0 processing unit 202 generates an address signal TP1 by adding a numerical value 0 as the least significant bit to the address signal TP0. Further, the LSB1 processing unit 203 generates an address signal TP2 by adding a numerical value 1 as the least significant bit to the address signal TP0. Here, the LSB0 processing unit 202 and the LSB1 processing unit 203 are not synchronized by a clock, but merely add a logical value “0” or “1” to the LSB of the output of the test pattern generation unit 201. . The description of verilog is as follows.

assign TP1 = {TP0,0};
assign TP2 = {TP0,1};
As shown in the timing chart of FIG. 5, at time t0, the LSB0 processing unit 202 adds a numerical value 0 as the least significant bit to the 2-bit address {00} generated as the address signal TP0, Address {000} is generated as address signal TP1. In the LSB1 processing unit 203, a numerical value 1 is added as the least significant bit to the address signal TP0, and a 3-bit address {001} is generated as the address signal TP2.

At time t2, the LSB0 processing unit 202 adds a numerical value 0 as the least significant bit to the 2-bit address {01} generated as the address signal TP0, and generates a 3-bit address {010} as the address signal TP1. Is done. In the LSB1 processing unit 203, a numerical value 1 is added as the least significant bit to the address signal TP0, and a 3-bit address {011} is generated as the address signal TP2.

At time t4, the LSB0 processing unit 202 adds a numerical value 0 as the least significant bit to the 2-bit address {10} generated as the address signal TP0, and generates a 3-bit address {100} as the address signal TP1. Is done. In the LSB1 processing unit 203, a numerical value 1 is added as the least significant bit to the address signal TP0, and a 3-bit address {101} is generated as the address signal TP2.

At time t6, LSB0 processing section 202 adds numerical value 0 as the least significant bit to 2-bit address {11} generated as address signal TP0, and generates 3-bit address {110} as address signal TP1. Is done. In the LSB1 processing unit 203, a numerical value 1 is added to the address signal TP0 as the least significant bit, and a 3-bit address {111} is generated as the address signal TP2.

Next, test data selection processing ST303 is performed. Here, the address signal TP1 which is the test data generated by the LSB0 processing unit 202 and the address signal TP2 which is the test data generated by the LSB1 processing unit 203 are converted into the address signal TP3 by the signal value of the second clock CK2. Is selectively output as

The test data selection unit 204 selects the address signal TP1 when the second clock CK2 has the logical value 1 and outputs it to the memory 205, and selects the address signal TP2 when the second clock CK2 has the logical value 0 and stores the address signal TP2 in the memory. Output to 205.

{From the time t0 to the time t1 in which the logical value of the second clock CK2 is 1 from the time t1 to the time t1, the test data selection unit 204 outputs {000} as the address signal TP3 as the test data. From time t1 to time t2 in which the logical value of the second clock CK2 is 0, {001} is output from the test data selection unit 204 as the address signal TP3.

{From the time t2 when the logic value of the second clock CK2 is 1 to the time t3, the test data selection unit 204 outputs {010} as the address signal TP3. From time t3 to time t4 when the logical value of the second clock CK2 is 0, {011} is output from the test data selection unit 204 as the address signal TP3.

{From the time t4 to the time t5 when the logical value of the second clock CK2 is 1, the test data selection unit 204 outputs {100} as the address signal TP3. From the time t5 to the time t6 when the logical value of the second clock CK2 is 0, {101} is output from the test data selection unit 204 as the address signal TP3.

{From the time t6 to the time t7 in which the logical value of the second clock CK2 is 1, the test data selection unit 204 outputs {110} as the address signal TP3. From time t7 to time t8 when the logic value of the second clock CK2 is 0, {111} is output from the test data selection unit 204 as the address signal TP3.

Next, test pattern application processing ST304 is performed. Here, the address signal TP3 output from the test data selection unit 204 is applied to the memory 205.

As described above, according to the present embodiment, the single test pattern generation unit 201 that operates by the second clock CK2 is provided, and the lowest-order address signal TP0 output from the test pattern generation unit 201 is output. An LSB0 processing unit 202 that adds a numerical value 0 as a bit and an LSB1 processing unit 203 that adds a numerical value 1 as the least significant bit are provided. Further, any one of the address signal TP1 of the LSB0 processing unit 202 and the address signal TP2 of the LSB1 processing unit 203 is provided. A test data selection unit 204 for selecting and outputting one of them is provided. This makes it possible to apply a test pattern to the memory 205 operating at twice the frequency of the test pattern generation unit 201 at the actual operation speed. That is, the memory 205 that operates at a high frequency can be tested without increasing the operating frequencies of the test pattern generating unit 201, the LSB0 processing unit 202, and the LSB1 processing unit 203, which are BIST circuits. Therefore, the driving capability of the test pattern generation unit 201, the LSB0 processing unit 202, and the LSB1 processing unit 203 for performing the BIST may be small, so that the circuit area and the power consumption can be reduced.

When the memory 205 is a DDR memory, clock signals of the same frequency are input to the first clock CK1 given to the DDR memory and the second clock CK2 given to the BIST circuit, as shown in the timing chart of FIG. By doing so, the test pattern can be input to the DDR memory in synchronization with both the rising edge and the falling edge of the clock CK1, and the same effect as in the present embodiment can be obtained. That is, the DDR memory can be tested without increasing the operating frequency of the test pattern generation unit 201, which is a BIST circuit, to twice. Therefore, the driving capability of the test pattern generation unit 201, the LSB0 processing unit 202, and the LSB1 processing unit 203 for performing the BIST may be small, so that the circuit area and the power consumption can be reduced.

(Embodiment 3)
FIG. 8 is a block diagram for explaining a method for testing a semiconductor integrated circuit and a memory according to the third embodiment of the present invention, and FIG. 9 is a timing chart.

Hereinafter, a method of testing a memory in the semiconductor integrated circuit shown in FIG. 8 will be described with reference to the flowchart of FIG.

4 is different from the semiconductor integrated circuit of FIG. 4 in that a delay circuit 206 for delaying the second clock CK2 to generate a delayed clock CK2 'is provided. As the delay circuit 206, for example, a circuit having a delay of a certain time by arranging a plurality of buffers and inverters in series, or a delay element capable of generating a delay of a certain time is used.

Hereinafter, the test data selection process ST303 and the test pattern application process ST304 in this embodiment will be described.

In the test data selection process ST303, one of the address signal TP1 generated by the LSB0 processing unit 202 and the address signal TP2 generated by the LSB1 processing unit 203 is delayed by the delay circuit 206 with respect to the second clock CK2. Selectively output by the delay clock CK2 '. The selection process is performed by the test data selection unit 204.

The test data selection unit 204 selects the address signal TP1 when the delay clock CK2 'has a logical value of 1, and selects the address signal TP2 when the clock CK2' has a logical value of 0.

From time t0 ′ to time t1 ′ in which the logical value of the delay clock CK2 ′ is 1, {000} is output as the address signal TP3 from the test data selecting unit 204, and the logical value of the delay clock CK2 ′ is From time t1 ′ to time t2 ′, which is a section of 0, {001} is output from test data selection unit 204 as address signal TP3.

From time t2 ′ to time t3 ′ where the logical value of the delay clock CK2 ′ is 1, {010} is output from the test data selection unit 204 as the address signal TP3, and the logical value of the delay clock CK2 ′ is From time t3 ′ to time t4 ′, which is a section of 0, {011} is output from the test data selection unit 204 as the address signal TP3.

From time t4 ′ to time t5 ′ in which the logical value of the delayed clock CK2 ′ is 1, {100} is output from the test data selecting unit 204 as the address signal TP3, and the logical value of the delayed clock CK2 ′ becomes From time t5 ′ to time t6 ′, which is a section of 0, {101} is output from test data selection section 204 as address signal TP3.

From time t6 ′ to time t7 ′ in which the logic value of the delay clock CK2 ′ is 1, {110} is output from the test data selection unit 204 as the address signal TP3, and the logic value of the delay clock CK2 ′ is From time t7 'to time t8', which is a section of 0, {111} is output from test data selection section 204 as address signal TP3.

In the test pattern application process ST304, the address signal TP3 output from the test data selection unit 204 is applied to the memory 205 that operates in synchronization with the rising edge of the first clock CK1.

As described above, according to the present embodiment, one of the address signal TP1 generated by the LSB0 processing unit 202 and the address signal TP2 generated by the LSB1 processing unit 203 is delayed by delaying the second clock CK2. The signal is selectively output by the delay clock CK2 ′ delayed by the circuit 206. As a result, the test data input to the memory 205, that is, the address signal TP3, is input with a certain delay value with respect to the clock CK1 of the memory 205, and the hold time can be secured for the clock CK1, and the memory that operates at high speed 205 can be applied with a stable test pattern.

Here, the hold time and the setup time will be described. The memory 205 operates in synchronization with the rising edge of the clock CK1. At this time, if the values of the address and data input signals to the memory 205 are not determined a predetermined time before the rising edge of the clock CK1, those data are not taken into the memory 205 at the rising of the clock CK1. This time is called setup time. Further, it is necessary to hold data for a certain time even after the clock CK1 rises. This time is called a hold time.

Further, the single test pattern generation unit 201 operated by the clock CK2 can apply the test pattern to the memory 205 operating at twice the frequency of the test pattern generation unit 201 at the actual operation speed. This is the same as the second embodiment.

Note that when the memory operates with the clock CK1 having a frequency twice as high as the clock CK2, the delay circuit 206 may have a flip-flop operating at the falling edge of the clock CK1 as shown in FIG. As shown, the same effect as in the present embodiment can be obtained by using a latch through which data passes during the high-level section of the clock CK1.

When the memory 205 is a DDR memory, as shown in the timing chart of FIG. 10, a clock signal of the same frequency is input to the clock CK1 to be given to the DDR memory and the clock CK2 to be given to the BIST circuit. , A test pattern can be input to the DDR memory in synchronization with both the rising edge and the falling edge, and the same effect as in the present embodiment can be obtained.

(Embodiment 4)
FIG. 13 is a block diagram for explaining a method for testing a semiconductor integrated circuit and a memory according to the fourth embodiment of the present invention, and FIG. 14 is a timing chart.

Hereinafter, a method for testing a memory in the semiconductor integrated circuit shown in FIG. 13 will be described with reference to the flowchart in FIG.

異 な る A difference from the semiconductor integrated circuit of FIG. 4 is that a clock selecting unit 207 is provided.

The clock selection unit 207 is a circuit that selects the second clock CK2 or an inverted signal of the second clock CK2 and outputs the selected signal as the clock CK4. The test data selection unit 204 selects one of the address signal TP1 generated by the LSB0 processing unit 202 and the address signal TP2 generated by the LSB1 processing unit 203 according to the signal value of the clock CK4 output from the clock selection unit 207. Either is selected.

A case where the clock selection unit 207 selects an inverted signal of the clock CK2 will be described.

(1) The first clock CK1 is a clock signal of the memory 205 that operates in synchronization with the rising edge of the input clock. The second clock CK2 is a clock signal of the test pattern generation unit 201 that operates in synchronization with the rising edge of the input clock, and has a frequency half that of the clock CK1.

In the test pattern generation process ST301, the test pattern generation unit 201 generates the address signal TP0 in synchronization with the rising edge of the clock CK2. Specifically, {11} is generated as the address signal TP0 at time t0, {10} is generated as the address signal TP0 at time t2, {01} is generated as the address signal TP0 at time t4, and at time t6. {00} is generated as the address signal TP0.

In the LSB process ST302, a process of adding a numerical value 0 or a numerical value 1 as the least significant bit to the address signal TP0 generated by the test pattern generation unit 201 is performed. The LSB0 processing unit 202 adds a numerical value 0 as the least significant bit to the address signal TP0 to generate an address signal TP1. In addition, the LSB1 processing unit 203 adds a numerical value 1 as the least significant bit to the address signal TP0 to generate an address signal TP2.

As shown in the timing chart of FIG. 14, at time t0, the LSB0 processing unit 202 adds a numerical value 0 as the least significant bit to the 2-bit address {11} generated as the address signal TP0, Address {110} is generated as address signal TP1. In the LSB1 processing unit 203, a numerical value 1 is added to the address signal TP0 as the least significant bit, and a 3-bit address {111} is generated as the address signal TP2.

At time t2, LSB0 processing section 202 adds numerical value 0 as the least significant bit to 2-bit address {10} generated as address signal TP0, and generates 3-bit address {100} as address signal TP1. Is done. In the LSB1 processing unit 203, a numerical value 1 is added as the least significant bit to the address signal TP0, and a 3-bit address {101} is generated as the address signal TP2.

At time t4, the LSB0 processing unit 202 adds a numerical value 0 as the least significant bit to the 2-bit address {01} generated as the address signal TP0, and generates a 3-bit address {010} as the address signal TP1. Is done. In the LSB1 processing unit 203, a numerical value 1 is added as the least significant bit to the address signal TP0, and a 3-bit address {011} is generated as the address signal TP2.

At time t6, the LSB0 processing unit 202 adds a numerical value 0 as the least significant bit to the 2-bit address {00} generated as the address signal TP0, and generates a 3-bit address {000} as the address signal TP1. Is done. In the LSB1 processing unit 203, a numerical value 1 is added as the least significant bit to the address signal TP0, and a 3-bit address {001} is generated as the address signal TP2.

The clock selection unit 207 selects and outputs the clock CK2 or the inverted signal of the clock CK2, and the test data selection unit 204 determines whether the LSB0 processing unit 202 responds to the signal value of the clock CK4 output from the clock selection unit 207. Either the generated address signal TP1 or the address signal TP2 generated by the LSB1 processing unit 203 is selected.

That is, in the test data selection process ST303, one of the address signal TP1 generated by the LSB0 processing unit 202 and the address signal TP2 generated by the LSB1 processing unit 203 is determined by the signal value of the clock CK4 of the clock selection unit 207. Selectively output.

(4) The test data selection unit 204 selects the address signal TP1 when the clock CK4 has the logical value 1, and selects the address signal TP2 when the clock CK4 has the logical value 0.

An inverted signal of the clock CK2 is selected as the output clock CK4 of the clock selection unit 207, and the test is performed from the time t0 to the time t1 in which the logical value of the clock CK2 is 1, that is, the logical value of the clock CK4 is 0. {111} is output from data selection section 204 as address signal TP3. In addition, during a period from time t1 to time t2 in which the logical value of the clock CK2 is 0, that is, the logical value of the clock CK4 is 1, {110} is output from the test data selecting unit 204 as the address signal TP3.

{From the time t2 to the time t3 in which the logical value of the clock CK2 is 1, that is, the logical value of the clock CK4 is 0, the test data selecting unit 204 generates {101} as the address signal TP3. Further, from the time t3 to the time t4 when the logical value of the clock CK2 is 0, that is, the logical value of the clock CK4 is 1, {100} is generated as the address signal TP3 from the test data selecting unit 204.

{From the time t4 to the time t5 when the logic value of the clock CK2 is 1, that is, the logic value of the clock CK4 is 0, {011} is generated from the test data selection unit 204 as the address signal TP3. In addition, during the period from time t5 to time t6 when the logical value of the clock CK2 is 0, that is, the logical value of the clock CK4 is 1, {010} is generated from the test data selecting unit 204 as the address signal TP3.

{From the time t6 to the time t7 in which the logical value of the clock CK2 is 1, that is, the logical value of the clock CK4 is 0, the test data selecting unit 204 generates {001} as the address signal TP3. Further, from time t7 to time t8 when the logic value of the clock CK2 is 0, that is, when the logic value of the clock CK4 is 1, {000} is generated from the test data selection unit 204 as the address signal TP3.

In the test pattern application process ST304, the address signal TP3 output from the test data selection unit 204 is applied to the memory 205.

As described above, according to the present embodiment, the single operation of the test pattern generator 201 operated by the clock CK2 causes the memory 205 operating at twice the frequency of the test pattern generator 201 to operate at the actual operation speed. It becomes possible to apply a test pattern. Other effects are similar to those of the second embodiment.

In the present embodiment, the clock selector 207 uses a circuit that selects the clock CK2 and a signal obtained by inverting the clock CK2 by the inverter 207a with the selector 207b. Instead, an exclusive OR circuit 208a is used as the clock selection unit 208 as shown in FIG. 16, and a circuit that can selectively output either the clock CK2 or the inverted signal of the clock CK2 is used. Even so, the same effect as in the present embodiment can be obtained.

Further, by providing the clock selection unit 207 or 208, the test data selection unit 204 separates a signal selected when the logical value of the clock CK2 is 0 and a signal selected when the clock CK2 is the logical value 1 of the clock CK2. You can switch. Therefore, when the logical value of the clock CK2 is 1, the even address is applied to the memory 205, and when the logical value of the clock CK2 is 0, not only the configuration where the odd address is applied to the memory 205, but also the logical value of the clock CK2. Is 1, the odd address is applied to the memory 205, and when the logical value of the clock CK2 is 0, the even address is applied to the memory 205. Therefore, the quality of the test pattern is improved, and the address can be incremented and decremented.

質 The quality of the test pattern refers to the following. That is, in the actual operation, when the clock CK2 is high (corresponding to the case where the clock CK1 is high in the case of a double data rate memory), even addresses and odd addresses should be accessed. In the test, the fact that only the even address can be accessed when the clock CK2 is high is not a good test. Since the test for accessing the odd address is not performed when the clock CK2 is high, the quality of the test pattern is expressed as poor. This time, it is described that the test can be performed at both the odd address and the even address, so that the quality of the test pattern is improved.

When the memory 205 is a DDR memory, as shown in the timing chart of FIG. 15, a clock having the same frequency is input to the clock CK1 to be given to the DDR memory and the clock CK2 to be given to the BIST circuit. A test pattern can be input in synchronization with both the rising edge and the falling edge of the clock CK1, and the same effect as in the present embodiment can be obtained.

(Embodiment 5)
FIG. 17 is a block diagram for describing a method for testing a semiconductor integrated circuit and a memory according to the fifth embodiment of the present invention, and FIG. 18 is a timing chart.

Hereinafter, a method for testing a memory in the semiconductor integrated circuit shown in FIG. 17 will be described with reference to the flowchart in FIG.

In FIG. 17, reference numeral 205 denotes a memory that operates in synchronization with the rising edge of the input clock. Reference numeral 601 denotes an expected value comparison unit that operates in synchronization with the rising edge of the input clock. Reference numeral 602 indicates a storage element that operates in synchronization with the falling edge of the input clock. This storage element 602 includes, for example, a flip-flop 602a.

The first clock CK1 is a clock signal of the memory 205. The second clock CK2 is a clock signal of the expected value comparison unit 601 and the clock signal of the storage element 602, and the frequency thereof is １ ／ of the clock CK1.

In the memory data output process ST701, a data signal 610 is output from the data output port DOUT of the memory 205 in synchronization with the rising edge of the clock CK1 at times t0, t1, t2, t3, t4, t5, t6, t7, and t8. You.

Data 610 output from the memory 205 in synchronization with the rising edge of the clock CK1 at time t0 is captured by the flip-flop 602a at time t1 in synchronization with the falling edge of the clock CK2 in the data temporary capture process ST702. Then, in the expected value comparison processing ST703 as the data signal 611, the expected value comparison unit 601 is entered and compared with the expected value at time t2.

{Data output from the memory 205 in synchronization with the rising edge of the clock CK1 at time t1 enters the expected value comparison unit 601 as a data signal 610, and is compared with the expected value at time t2.

Similarly, the data output from the memory 205 in synchronization with the rising edge of the clock CK1 at time t2 is supplied to the flip-flop 602a in synchronization with the falling edge of the clock CK2 in the data temporary capture process ST702, and at time t3. It is captured. Then, it enters the expected value comparison unit 601 as a data signal 611, and is compared with the expected value at time t4.

The data output from the memory 205 in synchronization with the rising edge of the clock CK1 at time t3 enters the expected value comparison unit 601 in the expected value comparison processing ST703 as a data signal 610, and compares the data with the expected value at time t4. Is done.

Data that is output from the memory 205 in synchronization with the rising edge of the clock CK1 at time t4 is captured by the flip-flop 602a at time t5 in synchronization with the falling edge of the clock CK2 in the data temporary capture process ST702. Then, it enters the expected value comparison unit 601 as the data signal 611, and is compared with the expected value at time t6.

The data output from the memory 205 in synchronization with the rising edge of the clock CK1 at time t5 enters the expected value comparison unit 601 in the expected value comparison processing ST703 as a data signal 610, and is compared with the expected value at time t6. Is done.

Data that is output from the memory 205 in synchronization with the rising edge of the clock CK1 at time t6 is captured by the flip-flop 602a at time t7 in synchronization with the falling edge of the clock CK2 in the data temporary capture process ST702. Then, it enters the expected value comparison unit 601 as the data signal 611, and is compared with the expected value at time t8.

The data output from the memory 205 in synchronization with the rising edge of the clock CK1 at time t7 enters the expected value comparison unit 601 as the data signal 610 in the expected value comparison processing ST703, and is compared with the expected value at time t8. You.

As described above, according to the present embodiment, the expected value is compared only in the rising edge of the clock CK2 in the expected value comparison process ST703, and the frequency is twice the frequency of the operation of the expected value comparison unit 601. It is possible to apply the test pattern to the memory 205 operating at the actual operation speed without changing the operation speed of the expected value comparison unit 601.

Although a flip-flop that operates at the falling edge of the clock CK2 is used as the storage element 602 in this embodiment, a latch that passes data in a high-level section of the clock CK2 may be used as in the present embodiment. The effect of is obtained.

When the memory 205 is a DDR memory, as shown in the timing chart of FIG. 19, a clock signal of the same frequency is input to the clock CK1 to be given to the DDR memory and the clock CK2 to be given to the BIST circuit. An effect similar to that of the present embodiment can be obtained only by comparing the expected value of the data signal of the memory 205 output in synchronization with both the rising edge and the falling edge of the clock CK1 at the rising timing of the clock CK2. Obtainable.

As described above, according to the semiconductor integrated circuit and the memory test method of the embodiment of the present invention, the BIST circuit is switched to the memory 205 by switching the input data according to the logical value of the clock of the BIST circuit. The test pattern can be applied at the actual operating speed of the memory 205 even when the memory 205 is operated at a clock frequency of の of the clock frequency.

In the expected value comparison, the data output of the memory 205 is held by using the storage element 602, and the data output to be output next is compared with the expected value, thereby reducing the clock frequency of the memory to 1/2. It is possible to compare the expected value of the memory at the actual operation speed by using the expected value comparing unit 601 operating at the clock frequency of.

Also, for a high-speed memory such as a DDR memory that operates in synchronization with both rising and falling edges of a clock, operating the BIST circuit at the same clock frequency as the clock frequency of the DDR memory allows the DDR memory to operate. Can be tested for the actual operating speed of the device.

(Embodiment 6)
FIG. 23 is a block diagram illustrating a method for testing a semiconductor integrated circuit and a memory according to the sixth embodiment of the present invention.

1 is different from the semiconductor integrated circuit of FIG. 1 in that a delay circuit 106 for delaying the second clock CK2 to generate a delayed clock CK2 'is provided. The configuration and operation of delay circuit 106 are similar to those of delay circuit 206 in the third embodiment. Therefore, by providing delay circuit 106, the same operation and effect as in the third embodiment can be obtained.

具体 A specific example of the delay circuit 106 is the same as that described in the third embodiment, and is shown in FIG. 24 or FIG.

(Embodiment 7)
FIG. 26 is a block diagram for illustrating a method for testing a semiconductor integrated circuit and a memory according to the seventh embodiment of the present invention.

異 な る A difference from the semiconductor integrated circuit of FIG. 1 is that a clock selecting unit 107 is provided. The configuration and operation of clock selecting section 107 are the same as those of clock selecting section 207 in the fourth embodiment. Therefore, the same operation and effect as in the fourth embodiment can be obtained by providing the clock selection unit 107.

ク ロ ッ ク Instead of the clock selection unit 107, a clock selection unit 108 as shown in FIG. 27 may be used. This clock selection unit 108 is the same as that described in the fourth embodiment.

The semiconductor integrated circuit according to the present invention has an effect that a high-speed memory test can be performed at an actual operation speed even if the operation speed of the BIST circuit is suppressed, and is useful as a semiconductor integrated circuit that performs a memory test by a built-in self test. It is.

FIG. 1 is a block diagram illustrating a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. 5 is a time chart for explaining the operation of the semiconductor integrated circuit according to the first embodiment of the present invention. 5 is a time chart for explaining the operation of the semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 9 is a block diagram illustrating a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention. 9 is a time chart for explaining an operation of the semiconductor integrated circuit according to the second embodiment of the present invention. 9 is a time chart for explaining an operation of the semiconductor integrated circuit according to the second embodiment of the present invention. 9 is a flowchart illustrating a memory test method according to the first, second, third, and fourth embodiments. FIG. 13 is a block diagram illustrating a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention. 13 is a time chart for explaining an operation of the semiconductor integrated circuit according to the third embodiment of the present invention. 13 is a time chart for explaining an operation of the semiconductor integrated circuit according to the third embodiment of the present invention. FIG. 14 is a block diagram showing a first specific example of a delay circuit of a semiconductor integrated circuit according to a third embodiment of the present invention. FIG. 14 is a block diagram showing a second specific example of the delay circuit of the semiconductor integrated circuit according to the third embodiment of the present invention. FIG. 14 is a block diagram illustrating a configuration of a semiconductor integrated circuit according to a fourth embodiment of the present invention. 13 is a time chart for explaining an operation of the semiconductor integrated circuit according to the fourth embodiment of the present invention. 13 is a time chart for explaining an operation of the semiconductor integrated circuit according to the fourth embodiment of the present invention. FIG. 14 is a block diagram showing another configuration of the clock selection unit of the semiconductor integrated circuit according to the fourth embodiment of the present invention. FIG. 15 is a block diagram illustrating a configuration of a semiconductor integrated circuit according to a fifth embodiment of the present invention. 16 is a time chart for explaining an operation of the semiconductor integrated circuit according to the fifth embodiment of the present invention. 16 is a time chart for explaining an operation of the semiconductor integrated circuit according to the fifth embodiment of the present invention. 15 is a flowchart illustrating a memory test method according to the fifth embodiment of the present invention. It is a block diagram which shows a prior art. 9 is a time chart showing the operation of the prior art. FIG. 15 is a block diagram illustrating a configuration of a semiconductor integrated circuit according to a sixth embodiment of the present invention. FIG. 15 is a block diagram showing a first specific example of a delay circuit of a semiconductor integrated circuit according to a sixth embodiment of the present invention. FIG. 21 is a block diagram showing a second specific example of the delay circuit of the semiconductor integrated circuit according to the sixth embodiment of the present invention. FIG. 15 is a block diagram illustrating a configuration of a semiconductor integrated circuit according to a seventh embodiment of the present invention. FIG. 21 is a block diagram showing another configuration of the clock selection unit of the semiconductor integrated circuit according to the seventh embodiment of the present invention.

Explanation of reference numerals

Reference Signs List 101 first test pattern generation unit 102 second test pattern generation unit 103 inverter 104 test data selection unit 105 memory 201 test pattern generation unit 202 LSB0 processing unit 203 LSB1 processing unit 204 test data selection unit 205 memory 206 delay circuit 207, 208 Clock selection unit 601 Expected value comparison unit 602 Storage element

Claims (26)

A memory that operates on a first clock;
A first test pattern generation unit that operates with a second clock having a frequency half of the first clock and generates first test data;
A second test pattern generator that operates on a third clock that is an inverted clock of the second clock and generates second test data;
One of the first and second test data output from the first test pattern generation unit and the second test pattern generation unit, respectively, is used as the signal value of the second clock and the third test data. And a test data selecting unit for selectively outputting the third test data to the memory in accordance with one of clock signal values. A memory that operates on a first clock;
A first test pattern generation unit that operates with a second clock having a frequency half of the first clock and generates first test data;
A second test pattern generator that operates on the second clock and generates second test data;
One of the first and second test data output from the first test pattern generator and the second test pattern generator is selectively selected according to the signal value of the second clock. And a test data selection unit for outputting the test data to the memory as third test data. A memory that operates on a first clock;
A test pattern generation unit that operates with a second clock having a frequency half the frequency of the first clock and generates first test data;
An LSB0 processing unit that generates a second test data by adding a numerical value 0 as a least significant bit to the first test data generated by the test pattern generation unit;
An LSB1 processing unit that adds a numerical value 1 as the least significant bit to the first test data generated by the test pattern generation unit to generate third test data;
One of the second and third test data output from the LSB0 processing unit and the LSB1 processing unit is selectively output according to the signal value of the second clock, and the fourth test data is output to the memory. And a test data selection unit for inputting the test data as test data. 4. The semiconductor integrated circuit according to claim 3, further comprising a delay circuit that delays the second clock and supplies the delayed clock to the test data selector. A memory that operates on a first clock;
A test pattern generation unit that operates with a second clock having a frequency half the frequency of the first clock and generates first test data;
An LSB0 processing unit that generates a second test data by adding a numerical value 0 as a least significant bit to the first test data generated by the test pattern generation unit;
An LSB1 processing unit that adds a numerical value 1 as the least significant bit to the first test data generated by the test pattern generation unit to generate third test data;
A clock selection unit that can select one of the second clock and an inverted clock of the second clock;
One of the second and third test data output from the LSB0 processing unit and the LSB1 processing unit is selectively output according to the output of the clock selection unit, and the fourth test data is output to the memory. A semiconductor integrated circuit including a test data selection unit for inputting data as data. A memory that operates on a first clock;
A storage element that captures first output data output from the memory in synchronization with the first clock with a second clock having a frequency half of the first clock;
The second output data, which is operated by the second clock and is output from the storage element, and the third output data output from the memory immediately after the first output data are set to predetermined expectations. A semiconductor integrated circuit comprising an expected value comparison unit for comparing a value with an expected value. A double data rate memory operating on a first clock;
A first test pattern generation unit that operates with a second clock having the same frequency as the first clock and generates first test data;
A second test pattern generator that operates on a third clock that is an inverted clock of the second clock and generates second test data;
One of the first and second test data output from the first test pattern generation unit and the second test pattern generation unit, respectively, is used as the signal value of the second clock and the third test data. A test data selection unit for selectively outputting a signal in accordance with one of clock signal values and inputting the data as third test data to the double data rate memory. A double data rate memory operating on a first clock;
A first test pattern generation unit that operates with a second clock having the same frequency as the first clock and generates first test data;
A second test pattern generator that operates on the second clock and generates second test data;
One of the first and second test data output from the first test pattern generator and the second test pattern generator is selectively selected according to the signal value of the second clock. And a test data selection unit for outputting the test data to the double data rate memory as third test data. A double data rate memory operating on a first clock;
A test pattern generation unit that operates with a second clock having the same frequency as the first clock and generates first test data;
An LSB0 processing unit that generates a second test data by adding a numerical value 0 as a least significant bit to the first test data generated by the test pattern generation unit;
An LSB1 processing unit that adds a numerical value 1 as the least significant bit to the first test data generated by the test pattern generation unit to generate third test data;
The double data rate memory selectively outputs one of the second and third test data respectively output from the LSB0 processing unit and the LSB1 processing unit in accordance with the signal value of the second clock. And a test data selection unit for inputting the test data as fourth test data to the semiconductor integrated circuit. 10. The semiconductor integrated circuit according to claim 9, further comprising a delay circuit that delays the second clock and supplies the delayed clock to the test data selection unit. A double data rate memory operating on a first clock;
A test pattern generation unit that operates with a second clock having the same frequency as the first clock and generates first test data;
An LSB0 processing unit that generates a second test data by adding a numerical value 0 as a least significant bit to the first test data generated by the test pattern generation unit;
An LSB1 processing unit that adds a numerical value 1 as the least significant bit to the first test data generated by the test pattern generation unit to generate third test data;
A clock selection unit that can select one of the second clock and an inverted clock of the second clock;
One of the second and third test data respectively output from the LSB0 processing unit and the LSB1 processing unit is selectively output in accordance with the output of the clock selection unit, and is output to the double data rate memory. And a test data selection unit for inputting the test data as test data. A double data rate memory operating on a first clock;
A storage element that captures first output data output from the double data rate memory in synchronization with the first clock with a second clock having the same frequency as the first clock;
The second output data, which is operated by the second clock and is output from the storage element, and the third output data output from the double data rate memory immediately after the first output data, A semiconductor integrated circuit comprising: an expected value comparison unit that compares a predetermined expected value. A method for testing a memory operating with a first clock, comprising:
The first test data is generated by a second clock having a half frequency of the first clock, and the second test data is generated by a third clock which is an inverted clock of the second clock. , One of the first and second test data is selected in accordance with one of the signal value of the second clock and the signal value of the third clock, and a third test is performed on the memory. A memory test method characterized by being input as data. A method for testing a memory operating with a first clock, comprising:
First test data is generated with a second clock having a frequency half of the first clock, and a numerical value 0 is added as the least significant bit to the first test data to generate second test data. At the same time, a numerical value 1 is added as the least significant bit to the first test data to generate third test data, and one of the second and third test data is converted to a signal of the second clock. A method for testing a memory, wherein the memory is selected according to a value and input to the memory. A method for testing a memory operating with a first clock, comprising:
First data output from the memory in synchronization with the first clock is held as second data by a second clock having a frequency half of the first clock, and the second data and And comparing the third data output from the memory in synchronization with the first clock immediately after the first data with a predetermined expected value by the second clock. How to test memory. A test method for a double data rate memory operating with a first clock,
The first test data is generated by a second clock having the same frequency as the first clock, and the second test data is generated by a third clock that is an inverted clock of the second clock. One of the first and second test data is selected according to one of the signal value of the second clock and the signal value of the third clock, and a third test is performed to the double data rate memory. A memory test method characterized by being input as data. A test method for a double data rate memory operating with a first clock,
Generating first test data with a second clock having the same frequency as the first clock, adding a numerical value 0 as the least significant bit to the first test data to generate second test data, A third test data is generated by adding a numerical value 1 as the least significant bit to the first test data, and one of the second and third test data is determined according to the signal value of the second clock. And selecting and inputting the data to the double data rate memory. A test method for a double data rate memory operating with a first clock,
First data output from the double data rate memory in synchronization with the first clock is held as second data by a second clock having the same frequency as the first clock, and the second data is Comparing the third data outputted from the double data rate memory in synchronization with the first clock immediately after the first data with a predetermined expected value by the second clock, respectively. Characteristic memory testing method. 2. The semiconductor integrated circuit according to claim 1, further comprising a delay circuit that delays the second clock and supplies the delayed clock to the test data selection unit. 3. The semiconductor integrated circuit according to claim 2, further comprising a delay circuit that delays the second clock and supplies the delayed clock to the test data selection unit. 8. The semiconductor integrated circuit according to claim 7, further comprising a delay circuit that delays the second clock and supplies the delayed clock to the test data selection unit. 9. The semiconductor integrated circuit according to claim 8, further comprising a delay circuit for delaying the second clock and providing the delayed clock to the test data selection unit. A memory that operates on a first clock;
A first test pattern generation unit that operates with a second clock having a frequency half of the first clock and generates first test data;
A second test pattern generator that operates on a third clock that is an inverted clock of the second clock and generates second test data;
A clock selection unit that can select one of the second clock and an inverted clock of the second clock;
One of the first and second test data output from the first test pattern generator and the second test pattern generator is selectively output according to the output of the clock selector. A test data selecting unit for inputting the test data to the memory as third test data. A memory that operates on a first clock;
A first test pattern generation unit that operates with a second clock having a frequency half of the first clock and generates first test data;
A second test pattern generator that operates on the second clock and generates second test data;
A clock selection unit that can select one of the second clock and an inverted clock of the second clock;
One of the first and second test data output from the first test pattern generator and the second test pattern generator is selectively output according to the output of the clock selector. A test data selecting unit for inputting the test data to the memory as third test data. A double data rate memory operating on a first clock;
A first test pattern generation unit that operates with a second clock having the same frequency as the first clock and generates first test data;
A second test pattern generator that operates on a third clock that is an inverted clock of the second clock and generates second test data;
A clock selection unit that can select one of the second clock and an inverted clock of the second clock;
One of the first and second test data output from the first test pattern generator and the second test pattern generator is selectively output according to the output of the clock selector. A test data selection unit for inputting the third test data to the double data rate memory. A double data rate memory operating on a first clock;
A first test pattern generation unit that operates with a second clock having the same frequency as the first clock and generates first test data;
A second test pattern generator that operates on the second clock and generates second test data;
A clock selection unit that can select one of the second clock and an inverted clock of the second clock;
One of the first and second test data output from the first test pattern generator and the second test pattern generator is selectively output according to the output of the clock selector. A test data selection unit for inputting the third test data to the double data rate memory.

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