JP2004361098A - Semiconductor integrated circuit, and semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for reducing the development man-hours of a test program for inspecting AC characteristics and reducing the test time of AC characteristic inspection. <P>SOLUTION: A three-input selector is provided at the data of a flip-flop at an initial stage for receiving signals for ensuring AC characteristics. Input 1, input 2, and input 3 of the selector are set to be data in the normal case, data via the delay of set-up time from the reference clock of AC characteristics, and data via the delay of hold time from the reference clock of AC characteristics, respectively. Then, an output data compressor 20, an expectation value storage register 21, and a comparator 22 are provided to the output of an initial stage flip-flop 16, and the self-inspection of the semiconductor integrated circuit can be made. The development period of the test program, and test time can be greatly reduced by the self inspection. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit and a semiconductor integrated circuit device, and more particularly to a test circuit for a semiconductor integrated circuit.
[0002]
[Prior art]
When testing the setup time and hold time of the AC characteristics of the semiconductor integrated circuit, the actual operation pattern of the semiconductor integrated circuit is processed in accordance with the standard of the AC characteristics of the semiconductor integrated circuit, and the result of the operation is used. , PASS / FAIL.
There is also a patent for performing a self-test (BIST: Built In Self Test) on the AC characteristics of a built-in memory of a semiconductor integrated circuit (for example, see Patent Document 1).
[0003]
[Patent Document 1]
JP-A-11-317096 (page 1-2, FIG. 1)
[0004]
[Problems to be solved by the invention]
However, in the above-described conventional technology, the actual operation pattern is processed in accordance with the standard of the AC characteristics, so that the number of test program development steps is increased, and the test time is increased because the actual operation pattern is used. There was a problem of becoming long.
[0005]
Further, the self-test method disclosed in Japanese Patent Application Laid-Open No. 11-317096 is specialized in self-test (BIST) of the AC characteristics of the built-in memory, and therefore cannot be used for other AC characteristics. there were.
[0006]
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described conventional problems, and provides a semiconductor integrated circuit capable of reducing the number of steps for developing an AC characteristic inspection test program and shortening the AC characteristic inspection test time. The purpose is to provide.
[0007]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, it is sufficient to confirm that the first-stage flip-flop receiving the data operates normally in order to guarantee the setup time and the hold time of the AC characteristics. In such a semiconductor integrated circuit, a delay cell for setting up a setup time and a delay cell for setting a hold time, which are synchronized with a reference clock in advance, are built in the semiconductor integrated circuit. This makes it easy to set data input.
[0008]
That is, the semiconductor integrated circuit according to claim 1 of the present invention is a semiconductor integrated circuit that performs a test for guaranteeing the setup time of the AC characteristics, and inputs a clock that is a reference for the setup time of the AC characteristics. It has a setup time setting delay cell for delaying the clock by the setup time. This facilitates setting of a waveform in consideration of the setup time, reduces the number of test program development man-hours for setup time inspection, and shortens the test time for setup time inspection.
[0009]
A semiconductor integrated circuit according to a second aspect of the present invention is a semiconductor integrated circuit for performing a test for guaranteeing a hold time of an AC characteristic. A delay cell for hold time setting for delaying by a hold time. This makes it easy to set the waveform in consideration of the hold time, reduces the number of test steps for developing the test program for the hold time inspection, and shortens the test time for the hold time inspection.
[0010]
A semiconductor integrated circuit according to a third aspect of the present invention is a semiconductor integrated circuit that performs a test for guaranteeing a setup time and a hold time of an AC characteristic, and serves as a reference for the setup time and the hold time of the AC characteristic. A setup time delay cell for inputting a clock and delaying the clock by the setup time, and a hold time setting for inputting a clock serving as a reference for the setup time and the hold time of the AC characteristics and delaying the clock by the hold time A delay cell for use, and a selector capable of switching between a test for a setup time and a test for a hold time. As a result, it is possible to automatically switch the inspection of the setup time and the inspection of the hold time.
[0011]
According to a fourth aspect of the present invention, in the semiconductor integrated circuit according to the third aspect, an output data compressor for compressing output data of the semiconductor integrated circuit is output as an output of the semiconductor integrated circuit. An expected value storage register for storing an expected value expected to be obtained, a comparator for comparing a result of the output data compressor with an expected value stored in the expected value storage register, and switching of the selector. And a self-inspection of the semiconductor integrated circuit. As a result, the self-test of the setup time and the hold time becomes possible, and as a result, the test program development period can be further reduced.
[0012]
A semiconductor integrated circuit device according to a fifth aspect of the present invention includes a plurality of the semiconductor integrated circuits according to the fourth aspect (hereinafter referred to as ACBIST_UNIT), and further includes a BIST control unit that controls an operation of the plurality of ACBIST_UNITs; A BIST determination unit that determines a result of the self-inspection of the plurality of ACBIST_UNITs. As a result, the self-test of the setup time and the hold time of a plurality of AC characteristics becomes possible, and as a result, the test program development period can be further reduced.
[0013]
In the semiconductor integrated circuit device according to a sixth aspect of the present invention, in the semiconductor integrated circuit device according to the fifth aspect, the BIST control unit arbitrarily sets a parallel test mode for simultaneously testing the ACBIST_UNITs and a diagnosis of the ACBIST_UNITs. And a function of switching between diagnostic modes that can be performed in this order. As a result, it is possible to analyze which AC characteristic test failed.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment 1)
FIG. 1 is a diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention.
In the figure, reference numeral 1 denotes a clock serving as a reference for a setup time and a hold time of AC characteristics. The clock 1 input from the outside passes through the input buffer 3 of the I / O cell 2 and is connected to the CK terminal 18 of the first-stage flip-flop 16.
[0015]
The input data 4 to be set and held is connected to the input A terminal 7 of the selector 6 in the I / O cell 5. One of two signal lines derived from the clock 1 is connected to the input B terminal 9 of the selector 6 via the setup time adjustment delay adjustment cell 8, and the other is connected to the hold time adjustment delay adjustment cell 10 via the setup time adjustment delay adjustment cell 8. The selector 6 is connected to the input C terminal 11.
[0016]
The signal output from the select signal control unit 13 is a select signal connected to the S terminal 14 of the selector 6. The select signal selects one of the input A terminal 7, the input B terminal 9, and the input C terminal 11 of the selector 6. In the normal operation, the input A terminal 7 is selected, the input B terminal 9 is selected when the setup time is checked, and the input C terminal 11 is selected when the hold time is checked. You.
[0017]
The signal output from the output Y terminal 12 of the selector 6 passes through the input buffer 15 and is input to the data D terminal 17 of the first-stage flip-flop 16. The signal output from the output Q terminal 19 of the first-stage flip-flop 16 is subjected to data compression by an output data compressor 20, and then a comparator 22 makes a comparison determination with an expected value 21 of an expected value storage register. .
[0018]
Next, the operation of the semiconductor integrated circuit according to the first embodiment will be described.
FIG. 2 is an operation waveform diagram of the first-stage flip-flop when the setup time of the AC characteristics is inspected. When checking the setup time, the selector 6 in FIG. 1 selects the input B terminal 9, and the waveform whose clock is delayed by the delay amount of the setup delay cell is input to the D terminal of the first stage flip-flop. At this time, the phase difference between the waveforms of the CK terminal and the D terminal of the first-stage flip-flop is a standardized setup time. If the Q terminal of the first-stage flip-flop is High, it means that the data has been normally captured, and if the Q terminal of the first-stage flip-flop is Low, it means that the data of one cycle before has been taken, and it is determined as FAIL. be able to.
[0019]
FIG. 3 is an operation waveform diagram of the first-stage flip-flop when the hold time of the AC characteristic is similarly inspected. When checking the hold time, the selector 6 in FIG. 1 selects the input C terminal 11, and the waveform whose clock is delayed by the delay amount of the hold delay cell enters the D terminal of the first stage flip-flop. At this time, the phase difference between the waveforms of the CK terminal and the D terminal of the first-stage flip-flop is the standard value of the hold time. If the output of the first-stage flip-flop is High, it means that the data has been normally captured, and if the output of the first-stage flip-flop is Low, it means that the data of one cycle before has been fetched. it can.
[0020]
In the semiconductor integrated circuit according to the first embodiment as described above, the self-test of the setup time and the hold time for the clock can be performed by the above configuration. Moreover, in order to guarantee the setup time and the hold time of the AC characteristics, it is confirmed that the first stage flip-flop receiving the data operates normally. Therefore, the actual operation pattern is processed in accordance with the standard of the AC characteristics. This eliminates the need to perform the test, thereby greatly reducing the number of steps for developing the test program for the AC characteristics inspection, and since the actual operation pattern is not used, the test time for the AC characteristics inspection can be greatly reduced.
[0021]
(Embodiment 2)
FIG. 4 is a diagram showing a semiconductor integrated circuit device according to a second embodiment of the present invention.
In the figure, ACBIST (1) 30, ACBIST (2) 31, and ACBIST (N) 32 are N pieces of self-tests for each AC characteristic having the components of the semiconductor integrated circuit of the first embodiment. UNIT. 33 is a clock CLK (1) serving as a reference for the ACBIST (1) 30, 34 is a clock CLK (2) serving as a reference for the ACBIST (2) 31, and 35 is a clock serving as a reference for the ACBIST (N) 32. CLK (N) and 36 are BIST control units for controlling the ACBIST (1) 30 to ACBIST (N) 32, and 37 is a BIST_ENABLE signal for controlling execution / non-execution of the AC characteristic self-test. Reference numeral 38 denotes a BIST determination unit that receives a determination result of each self-test circuit, performs a PASS / FAIL determination of the entire AC characteristic test, and outputs a BIST result determination signal 39. Reference numeral 40 denotes a test end signal output at the end of the test.
[0022]
Next, the operation of the semiconductor integrated circuit device according to the second embodiment will be described.
FIG. 5 is an operation waveform diagram showing a judgment operation of each ACBIST_UNIT and a judgment operation of the entire AC characteristic when each ACBIST_UNIT is inspected in parallel.
[0023]
In each ACBIST_UNIT, the input B terminal is selected from the three inputs of the selector 6 in FIG. 1 at the first clock of the CLK (1) after the BIST_ENABLE signal becomes High, and the PASS / FAIL judgment of the setup is performed at the third clock. The input C terminal is selected from the three inputs of the selector 6 at the fourth clock, the PASS / FAIL judgment of the hold is performed at the sixth clock, and the comparison judgment by the comparator is performed at the seventh clock. If both the setup and hold inspections are PASS, High is output. The other ACBIST_UNIT performs the same operation. After the operation of all ACBIST_UNITs is completed, a test end signal is output, and the AND result of the determination signals of the comparators of each ACBIST_UNIT is output as a BIST result determination signal. If the BIST result determination signal is High, it means that the entire test has been PASSed.
[0024]
According to the semiconductor integrated circuit device according to the second embodiment as described above, since the configuration is as described above, a plurality of AC characteristics of each ACBIST UNIT can be self-tested. The development man-hours of the test program for use can be greatly reduced, and the test time for the AC characteristic inspection can be greatly reduced. Furthermore, in the second embodiment, by providing the parallel test / diagnosis mode switching signal 41, it is possible to perform parallel tests from ACBIST (1) to ACBIST (N) simultaneously, thereby reducing the test time. It can be greatly reduced.
[0025]
In the diagnostic mode, any unit can be diagnosed in any order, so that it is possible to analyze which AC test resulted in FAIL.
[0026]
【The invention's effect】
As described above, according to the semiconductor integrated circuit of the first aspect of the present invention, there is provided a semiconductor integrated circuit for performing an inspection for guaranteeing a setup time of an AC characteristic, wherein a clock serving as a reference of the setup time of the AC characteristic And a setup time delay cell for delaying the clock by the setup time, so that setting of the waveform in consideration of the setup time is facilitated, and the number of test program development steps for setup time inspection is reduced. In addition, the test time of the setup time inspection can be shortened.
[0027]
According to the semiconductor integrated circuit of the second aspect of the present invention, there is provided a semiconductor integrated circuit for performing a test for guaranteeing a hold time of an AC characteristic. Since it has a delay cell for hold time setting that delays the clock by the hold time, it is easy to set the waveform considering the hold time, reduce the number of test program development steps for hold time inspection, and hold time inspection This has the effect of reducing the test time of the test.
[0028]
According to a third aspect of the present invention, there is provided a semiconductor integrated circuit for performing a test for guaranteeing a setup time and a hold time of an AC characteristic, wherein a reference of the setup time and the hold time of the AC characteristic is provided. And a delay cell for setting the setup time for delaying the clock by the setup time, and a clock for inputting the reference clock for the setup time and the hold time of the AC characteristics and delaying the clock by the hold time It has a delay cell for time setting, and a selector that can switch between the test of the setup time and the test of the hold time, so that the test of the setup time and the test of the hold time can be automatically switched. The following effect can be obtained.
[0029]
According to the semiconductor integrated circuit of claim 4 of the present invention, in the semiconductor integrated circuit of claim 3, an output data compressor for compressing output data of the semiconductor integrated circuit, and an output as an output of the semiconductor integrated circuit An expected value storage register for storing an expected value expected to be performed; a comparator for comparing a result of the output data compressor with an expected value stored in the expected value storage register; And a control circuit for controlling the switching, and the self-inspection of the semiconductor integrated circuit is made possible.Thus, the self-inspection of the setup time and the hold time becomes possible. As a result, the test program development period is further increased. The effect of reduction can be obtained.
[0030]
According to a semiconductor integrated circuit device according to a fifth aspect of the present invention, there is provided a BIST control unit having a plurality of the semiconductor integrated circuits according to the fourth aspect (hereinafter referred to as ACBIST_UNIT), and further controlling the operation of the plurality of ACBIST_UNITs. And a BIST determination unit that determines the result of the self-test of the plurality of ACBIST_UNITs. Therefore, a plurality of AC characteristic tests can be performed simultaneously in parallel, and the effect of greatly reducing the test time can be obtained. .
[0031]
According to the semiconductor integrated circuit device of claim 6 of the present invention, in the semiconductor integrated circuit device of claim 5, the BIST control unit performs a parallel test mode for simultaneously testing each of the ACBIST_UNITs and a diagnosis of each of the ACBIST_UNITs. Has a function of switching between diagnostic modes that can be performed in an arbitrary order, so that each ACBIST_UNIT can be inspected at the same time, the inspection time can be reduced, and each self-inspection circuit can determine which AC characteristic The effect of being able to analyze whether the test has failed is obtained.
[Brief description of the drawings]
FIG. 1 is a diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention.
FIG. 2 is an operation waveform diagram when a setup time is inspected according to the first embodiment of the present invention.
FIG. 3 is an operation waveform diagram when a hold time is inspected according to the first embodiment of the present invention.
FIG. 4 is a diagram showing a semiconductor integrated circuit device according to a second embodiment of the present invention.
FIG. 5 is an operation waveform diagram according to the second embodiment of the present invention.
[Explanation of symbols]
1 clock 2, 5 I / O cell 3, 15 input buffer 4 input data 6 selector 7 selector input A terminal 8 setup time adjustment delay adjustment cell 9 selector input B terminal 10 hold time adjustment delay adjustment cell 11 selector Input C terminal 12 Selector output Y terminal 13 Select signal control unit 14 Selector S terminal 16 First stage flip-flop 17 First stage flip-flop data D terminal 18 First stage flip-flop clock terminal 19 First stage flip-flop output Q terminal 20 Output data compression Device 21 expected value storage register 22 comparator 30 ACBIST (1)
31 ACBIST (2)
32 ACBIST (N)
33 Clock CLK (1) serving as reference for ACBIST (1)
34 Clock CLK (2) serving as reference for ACBIST (2)
35 Clock CLK (N) serving as reference for ACBIST (N)
36 BIST control unit 37 BIST_ENABLE signal 38 BIST determination unit 39 BIST result determination signal 40 Test end signal 41 Parallel inspection / diagnosis mode switching signal

Claims (6)

A semiconductor integrated circuit for performing a test for guaranteeing a setup time of AC characteristics,
It has a setup time setting delay cell that inputs a clock serving as a reference for the setup time of the AC characteristics and delays the clock by the setup time.
A semiconductor integrated circuit characterized by the above-mentioned. A semiconductor integrated circuit for performing a test for guaranteeing a hold time of AC characteristics,
A hold time setting delay cell for inputting a clock serving as a reference for the hold time of the AC characteristics and delaying the clock by the hold time;
A semiconductor integrated circuit characterized by the above-mentioned. A semiconductor integrated circuit for performing a test for guaranteeing a setup time and a hold time of AC characteristics,
A setup time setting delay cell for inputting a clock serving as a reference for a setup time and a hold time of AC characteristics and delaying the clock by the setup time;
A hold time setting delay cell for inputting a clock serving as a reference for the setup time and the hold time of the AC characteristics and delaying the clock by the hold time;
Inspection of setup time, having a selector that can switch between inspection of hold time,
A semiconductor integrated circuit characterized by the above-mentioned. The semiconductor integrated circuit according to claim 3,
An output data compressor for compressing output data of the semiconductor integrated circuit;
An expected value storage register for storing an expected value expected to be output as an output of the semiconductor integrated circuit;
A comparator for comparing the result of the output data compressor with an expected value stored in the expected value storage register;
A control circuit for controlling switching of the selector,
Enabled self-inspection of the semiconductor integrated circuit,
A semiconductor integrated circuit characterized by the above-mentioned. A plurality of semiconductor integrated circuits according to claim 4 (hereinafter, referred to as ACBIST_UNIT),
A BIST control unit that controls operations of the plurality of ACBIST_UNITs;
A BIST determination unit that determines a result of the self-test of the plurality of ACBIST_UNITs.
A semiconductor integrated circuit device characterized by the above-mentioned. The semiconductor integrated circuit device according to claim 5,
The BIST control unit has a function of switching between a parallel test mode for simultaneously testing the ACBIST_UNITs and a diagnostic mode for performing a diagnosis of the ACBIST_UNITs in an arbitrary order.
A semiconductor integrated circuit device characterized by the above-mentioned.

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