CN110033819B - SRAM establishment holding time test circuit - Google Patents

SRAM establishment holding time test circuit Download PDF

Info

Publication number
CN110033819B
CN110033819B CN201810027540.7A CN201810027540A CN110033819B CN 110033819 B CN110033819 B CN 110033819B CN 201810027540 A CN201810027540 A CN 201810027540A CN 110033819 B CN110033819 B CN 110033819B
Authority
CN
China
Prior art keywords
data
coupled
sram
circuit
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810027540.7A
Other languages
Chinese (zh)
Other versions
CN110033819A (en
Inventor
张静
方伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201810027540.7A priority Critical patent/CN110033819B/en
Publication of CN110033819A publication Critical patent/CN110033819A/en
Application granted granted Critical
Publication of CN110033819B publication Critical patent/CN110033819B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Pulse Circuits (AREA)

Abstract

An SRAM setup hold time test circuit comprising: the data signal delay circuit is coupled with the data signal input end of the multi-path multi-phase selector and is suitable for carrying out delay processing on the input data signal; the clock signal delay circuit is coupled with the clock signal input end of the multi-path multi-phase selector and is suitable for carrying out delay processing on the input clock signal; and the multi-path multi-phase selector is coupled with the SRAM, is suitable for carrying out multi-path multi-phase processing on the input data signals and the clock signals to obtain data signals and clock signals with different paths and different phases, and outputs the data signals and the clock signals to the SRAM through the data signal and clock signal output ends. The scheme can accurately acquire the SRAM establishment holding time.

Description

SRAM establishment holding time test circuit
Technical Field
The embodiment of the invention relates to the field of circuits, in particular to a circuit for testing the establishment and retention time of an SRAM (static random access memory).
Background
Establishing a hold time (setup/hold time), including a setup time and a hold time, wherein: the setup time refers to the time when data is stable and unchangeable before the rising edge of a clock signal of the trigger arrives; the hold time refers to the time when data is stable after the rising edge of the clock signal of the flip-flop.
In a System On Chip (SoC), if the setup and hold time of a Static Random Access Memory (SRAM) cannot be satisfied, a metastable state phenomenon may occur, resulting in an error in reading and writing the SRAM.
When the set-up holding time of the SRAM is large, the operating frequency of the chip is lowered. Therefore, in practical applications, testing is required to obtain accurate SRAM setup retention time.
Disclosure of Invention
The embodiment of the invention solves the problem of accurately acquiring the SRAM establishment holding time.
To solve the above technical problem, an embodiment of the present invention provides a circuit for testing an SRAM setup holding time, including: the data signal delay circuit is coupled with the data signal input end of the multi-path multi-phase selector and is suitable for carrying out delay processing on the input data signal; the clock signal delay circuit is coupled with the clock signal input end of the multi-path multi-phase selector and is suitable for carrying out delay processing on the input clock signal; and the multi-path multi-phase selector is coupled with the SRAM and is suitable for carrying out multi-path multi-phase processing on the input data signals to obtain data signals with different paths and different phases and outputting the data signals to the SRAM.
Optionally, a data signal output terminal of the multi-path multi-phase selector is coupled to a data signal input terminal of the SRAM; the multi-path multi-phase selector includes: a data multi-path multi-phase circuit; the data multi-path multi-phase circuit comprises an input end and an output end; the input end of the data multi-path multi-phase circuit is coupled with the output end of the data signal delay circuit, and the output end of the data multi-path multi-phase circuit is coupled with the data signal input end of the SRAM and is suitable for outputting data signals with different paths and different phases.
Optionally, the data multiplexing multi-phase circuit includes: a first inverter having an input coupled to the output of the data signal delay circuit and an output coupled to the first input of the first data selector; a second input end of the first data selector is coupled with an output end of the data signal delay circuit, an output end of the first data selector is coupled with a data signal input end of the SRAM, and an enable signal input end of the first data selector inputs an enable signal; the first data selector is suitable for selecting and outputting a corresponding signal from the input signals of the two input ends according to different enabling signals.
Optionally, the multi-path multi-phase selector includes a clock signal output terminal; the clock signal output end of the multi-path multi-phase selector is coupled with the clock signal input end of the SRAM; the multi-path multi-phase selector further comprises: a clocked multi-phase circuit; the clock multi-path multi-phase circuit comprises an input end and an output end; the input end of the clock multi-phase circuit is coupled with the output end of the clock signal delay circuit, and the output end of the clock multi-phase circuit is coupled with the clock signal input end of the SRAM and is suitable for outputting clock signals with different paths and different phases.
Optionally, the clock multiplexing multi-phase circuit includes: the input end of the second inverter is coupled with the output end of the clock signal delay circuit, and the output end of the second inverter is coupled with the first input end of the second data selector; a second input end of the second data selector is coupled with an output end of the clock signal delay circuit, an output end of the second data selector is coupled with a clock signal input end of the SRAM, and an enable signal input end of the second data selector inputs an enable signal; the second data selector is suitable for selecting and outputting a corresponding signal from the input signals of the two input ends according to different enabling signals.
Optionally, a data signal output end of the multi-path multi-phase selector is coupled to a clock signal input end of the SRAM; the multi-path multi-phase selector includes: a data multi-path multi-phase circuit; the data multi-path multi-phase circuit comprises an input end and an output end; the input end of the data multi-path multi-phase circuit is coupled with the output end of the data signal delay circuit, and the output end of the data multi-path multi-phase circuit is coupled with the clock signal input end of the SRAM and is suitable for outputting data signals with different paths and different phases.
Optionally, the data multiplexing multi-phase circuit includes: a first inverter having an input coupled to the output of the data signal delay circuit and an output coupled to the first input of the first data selector; a second input end of the first data selector is coupled with an output end of the data signal delay circuit, an output end of the first data selector is coupled with a data signal input end of the SRAM, and an enable signal input end of the first data selector inputs an enable signal; the first data selector is suitable for selecting and outputting a corresponding signal from the input signals of the two input ends according to different enabling signals.
Optionally, the multi-path multi-phase selector includes a clock signal output terminal; the clock signal output end of the multi-path multi-phase selector is coupled with the data signal input end of the SRAM; the multi-path multi-phase selector further comprises: a clocked multi-phase circuit; the clock multi-path multi-phase circuit comprises an input end and an output end; the input end of the clock multi-path multi-phase circuit is coupled with the output end of the clock signal delay circuit, the output end of the clock multi-path multi-phase circuit is coupled with the data signal input end of the SRAM, and the clock multi-path multi-phase circuit is suitable for outputting clock signals with different paths and different phases.
Optionally, the clock multiplexing multi-phase circuit includes: the input end of the second inverter is coupled with the output end of the clock signal delay circuit, and the output end of the second inverter is coupled with the first input end of the second data selector; a second input end of the second data selector is coupled with an output end of the clock signal delay circuit, an output end of the second data selector is coupled with a clock signal input end of the SRAM, and an enable signal input end of the second data selector inputs an enable signal; the second data selector is suitable for selecting and outputting a corresponding signal from the input signals of the two input ends according to different enabling signals.
Optionally, the data signal delay circuit includes: a D flip-flop and a first delay circuit, wherein: the D end of the D trigger inputs the data signal, the clock signal input end inputs the clock signal, and the output end is coupled with the data signal input end of the first delay circuit; and the output end of the first delay circuit is coupled with the data signal input end of the multi-path multi-phase selector, and the control end of the first delay circuit is suitable for inputting a first delay control signal.
Optionally, the clock signal delay circuit includes: a delay matching circuit and a second delay circuit, wherein: the clock signal input end of the delay matching circuit inputs the clock signal, and the output end of the delay matching circuit is coupled with the clock signal input end of the second delay circuit and is suitable for synchronizing the rising edge of the clock signal with the rising edge of the output signal of the D trigger; and the output end of the second delay circuit is coupled with the clock signal input end of the multi-path multi-phase selector, and the control end of the second delay circuit is suitable for inputting a second delay control signal.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
and carrying out multi-path and multi-phase processing on the data signals output by the data signal delay circuit to obtain data signals of different paths and different phases, and outputting the data signals of different paths and different phases to the SRAM. And obtaining a critical value of test passing and test failing according to the output signal of the SRAM, and obtaining the delay time corresponding to the data signal delay circuit and the delay time corresponding to the clock signal delay circuit, thereby obtaining the SRAM establishment holding time. The SRAM setup holding time is obtained through the threshold value of the test failure according to the output signal obtaining test of the SRAM, the delay time corresponding to the data signal delay circuit and the delay time corresponding to the clock signal delay circuit can be accurately determined, and therefore the SRAM setup holding time can be accurately obtained.
Furthermore, the clock signal output by the clock signal delay circuit is subjected to multi-path and multi-phase processing to obtain clock signals with different paths and different phases, and the clock signals with different paths and different phases are output to the SRAM. When the threshold values of the pass and fail tests are obtained according to the output signals of the SRAM, the establishment and holding time of the SRAM can be determined according to clock signals of different paths and different phases, data signals of different paths and different paths, and the establishment and holding time of the SRAM with higher precision can be obtained.
In addition, the output end of the clock signal delay circuit is connected with the data signal input end of the SRAM, and the output end of the data signal delay circuit is connected with the clock signal input end of the SRAM, so that more combinations of clock signals and data signals can be obtained, and the SRAM establishment holding time can be further prolonged.
Drawings
FIG. 1 is a schematic structural diagram of an SRAM setup hold time test circuit in an embodiment of the present invention;
FIG. 2 is a schematic diagram of a data multiplexing multiphase circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a clocked multi-phase circuit according to an embodiment of the invention;
fig. 4 is a schematic diagram of another multi-path multi-phase selector according to an embodiment of the present invention.
Detailed Description
In a System On Chip (SoC), when the setup/hold time (setup/hold time) of the SRAM is large, the operating frequency of the Chip is reduced. Therefore, in practical applications, testing is required to obtain accurate SRAM setup retention time.
In the prior art, static timing analysis methods are used to test SRAM setup retention times. However, when the static timing analysis method is used, the rising edge and the falling edge of the data signal are not distinguished, so that the accuracy of the built and maintained time of the tested SRAM is poor.
In the implementation of the present invention, the data signals output by the data signal delay circuit are subjected to multi-path and multi-phase processing to obtain data signals of different paths and different phases, and the data signals of different paths and different phases are output to the SRAM. And obtaining a critical value of test passing and test failing according to the output signal of the SRAM, and obtaining the delay time corresponding to the data signal delay circuit and the delay time corresponding to the clock signal delay circuit, thereby obtaining the SRAM establishment holding time. The SRAM setup holding time is obtained through the threshold value of the test failure according to the output signal obtaining test of the SRAM, the delay time corresponding to the data signal delay circuit and the delay time corresponding to the clock signal delay circuit can be accurately determined, and therefore the SRAM setup holding time can be accurately obtained.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 1, an embodiment of the present invention provides a SRAM setup hold time test circuit, including: a data signal delay circuit 11, a clock signal delay circuit 12, and a multi-way multi-phase selector 13, wherein:
a DATA signal delay circuit 11, coupled to a DATA signal input terminal of the multi-path multi-phase selector 13, and adapted to delay the input DATA signal DATA;
a clock signal delay circuit 12 coupled to a clock signal input terminal of the multi-path multi-phase selector 13 and adapted to delay an input clock signal CLK;
and a multi-path multi-phase selector 13, coupled to the SRAM 14, adapted to perform multi-path multi-phase processing on the input data signals to obtain data signals with different paths and different phases, and output the data signals to the SRAM 14 via the data signal output terminal.
The SRAM setup hold time test circuit in fig. 1 is explained in detail below.
In a specific implementation, the data signal delay circuit 11 may include: a data signal input terminal and a data signal output terminal. The DATA signal delay circuit 11 has a DATA signal input terminal to which the DATA signal DATA is input and a DATA signal output terminal coupled to a DATA signal input terminal of the multi-path multi-phase selector 13. The DATA signal DATA input is subjected to delay processing by the DATA signal delay circuit 11, and the DATA signal subjected to delay processing is output to a DATA signal input terminal of the multi-path multi-phase selector 13.
Accordingly, the clock signal delay circuit 12 may include: a clock signal input terminal and a clock signal output terminal. The clock signal input terminal of the clock signal delay circuit 12 receives the clock signal CLK, and the clock signal output terminal is coupled to the clock signal input terminal of the multi-phase selector 13. The clock signal delay circuit 12 delays the input clock signal CLK, and outputs the delayed clock signal to the clock signal input terminal of the multi-path multi-phase selector 13.
That is, the data signal input terminals of the multi-path multi-phase selector 13 are inputted with: the data signal after being delayed by the data signal delay circuit 11; the clock signal input of the multi-path multi-phase selector 13 is as follows: the clock signal after the delay processing by the clock signal delay circuit 12.
Referring to fig. 1, in an embodiment of the present invention, the data signal delay circuit 11 may include: a D flip-flop 111 and a first delay circuit 112, wherein: a DATA signal DATA is input to a D terminal of the D flip-flop 111, a clock signal CLK is input to a clock signal input terminal CLK of the D flip-flop, and an output terminal of the D flip-flop 111 is coupled to a DATA signal input terminal of the first delay circuit 112; an output terminal of the first delay circuit 112 is coupled to a data signal input terminal of the multi-way multi-phase selector 13, and a control terminal ctr1 of the first delay circuit 112 is adapted to input a first delay control signal.
In a specific implementation, a tester may input a first delay control signal at the control terminal ctr1 of the first delay circuit 112, which characterizes different delay times. The first delay control circuit 112 performs corresponding delay processing on the data signal according to the input different first delay control signals.
The clock signal delay circuit 12 may include a delay matching circuit 121 and a second delay circuit 122, in which: the clock signal CLK is input to the clock signal input terminal of the delay matching circuit 121, and the output terminal of the delay matching circuit 121 is coupled to the clock signal input terminal of the second delay circuit 122; the output terminal 122 of the second delay circuit is coupled to the clock signal input terminal of the multi-way multi-phase selector 13, and the control terminal ctr2 of the second delay circuit is adapted to input a second delay control signal. In the embodiment of the present invention, the rising edge of the input clock signal CLK can be synchronized with the rising edge of the output signal of the D flip-flop 111 by the delay matching circuit 121.
In a specific implementation, a tester may input a second delay control signal representing different delay times at the control terminal ctr2 of the second delay circuit 122, and the second delay circuit 122 performs corresponding delay processing on the clock signal according to the input different second delay control signal.
In practical applications, the first delay circuit 112 and the second delay circuit 122 can be 32-bit delay circuits.
In a specific implementation, the data signal output terminal of the multi-way multi-phase selector 13 may be coupled to the data signal input terminal of the SRAM 14, and may also be coupled to the clock signal input terminal of the SRAM 14. Accordingly, when the data signal output terminal of the multi-path multi-phase selector 13 is coupled to the data signal input terminal of the SRAM 14, the clock signal output terminal of the multi-path multi-phase selector 13 is coupled to the clock signal input terminal of the SRAM 14; when the data signal output terminal of the multi-way multi-phase selector 13 is coupled to the clock signal input terminal of the SRAM 14, the clock signal output terminal of the multi-way multi-phase selector 13 is coupled to the data signal input terminal of the SRAM 14. The above-described scenarios are explained below.
In the embodiment of the present invention, when the data signal output terminal of the multi-way multi-phase selector 13 is coupled to the data signal input terminal of the SRAM 14, the clock signal output terminal of the multi-way multi-phase selector 13 is coupled to the clock signal input terminal of the SRAM 14.
The multi-path multi-phase selector 13 may include: a data multiplexing multiphase circuit. In an embodiment of the present invention, a data multiplexing multiphase circuit may include an input terminal and an output terminal. When the data signal output terminal of the multiplexer 13 is coupled to the data signal input terminal of the SRAM 14, the input terminal of the data multiplexer is coupled to the output terminal of the data signal delay circuit 11, and the output terminal of the data multiplexer is coupled to the data signal input terminal of the SRAM 14.
The data multi-path multi-phase circuit inputs the data signals delayed by the data signal delay circuit 11, performs multi-path multi-phase processing on the delayed data signals to obtain data signals of different paths and different phases, and inputs the data signals to the data signal input end of the SRAM 14.
For example, the DATA signal input to the DATA signal delay circuit 11 is DATA. After the DATA is processed by the DATA signal delay circuit 11, a delayed DATA signal DATA _ delay is obtained. At this time, the DATA signal input to the DATA multi-phase circuit is DATA _ delay. The DATA multi-phase circuit processes the DATA _ delay to obtain DATA signals with different paths and different phases.
In a specific implementation, a data multiplexing multiphase circuit may include: a first inverter and a first data selector, wherein: the input terminal of the first inverter is coupled to the output terminal of the data signal delay circuit 11, and the output terminal of the first inverter is coupled to the first input terminal of the first data selector; the second input terminal of the first data selector is coupled to the output terminal of the data signal delay circuit 11, and the output terminal of the first data selector is coupled to the data signal input terminal of the SRAM; the enable signal input terminal of the first data selector may input different enable signals, and the first data selector selects and outputs a corresponding one of the input signals from the two input terminals according to the input enable signal.
For example, when the enable signal input from the enable signal input terminal is 0, the first data selector selects the data signal input from the first input terminal as an output; when the enable signal input by the enable signal input terminal is 1, the first data selector selects the data signal input by the second input terminal as an output.
Referring to fig. 2, a schematic diagram of a data multiplexing multiphase circuit according to an embodiment of the present invention is shown.
In fig. 2, a first input terminal of the first data selector 132 is coupled to the output terminal of the first inverter 131, and a second input terminal of the first data selector 132 is coupled to the output terminal of the data signal delay circuit 11; an input terminal of the first inverter 131 is coupled to an output terminal of the data signal delay circuit 11.
The operation principle of the SRAM setup hold time test circuit provided in the above embodiment of the present invention is described below with reference to fig. 1 and fig. 2.
When the SRAM setup hold time test is performed, a tester may input a first delay control signal at the control terminal of the first delay circuit and a second delay control signal at the control terminal of the second delay circuit. The first delay time corresponding to the first delay control signal and the second delay time corresponding to the second delay control signal may be the same or different.
The input terminal of the multi-path multi-phase selector 13 inputs the data signal passing through the first delay duration, and the output terminal outputs a plurality of data signals of different paths and different phases to the SRAM. At this time, the output signals of the SRAM are the same as the number of data signals output from the multi-path multi-phase selector 13. According to different data signals output by the multi-path multi-phase selector 13, threshold values corresponding to SRAM test pass and SRAM test fail are obtained, and a first delay time and a second delay time are obtained according to the threshold values, so that SRAM establishment holding time is obtained. That is, the setup holding time of the SRAM is obtained from the data signals of a plurality of different paths and different phases, so that the delay time corresponding to the data signal delay circuit and the delay time corresponding to the clock signal delay circuit 12 can be accurately determined, and the setup holding time of the SRAM can be accurately obtained.
In an implementation, the multi-phase selector 13 may further include a clock multi-phase circuit. The input terminal of the clock multi-phase circuit is coupled to the output terminal of the clock signal delay circuit 12, and the output terminal of the clock multi-phase circuit is coupled to the clock signal input terminal of the SRAM
The clock multi-phase circuit inputs the clock signal delayed by the clock signal delay circuit 12, and performs multi-phase processing on the delayed clock signal to obtain clock signals of different paths and different phases, and inputs the clock signals to the clock signal input terminal of the SRAM.
For example, the clock signal input to the clock signal delay circuit 12 is CLK. After the CLK is processed by the clock signal delay circuit 12, a delayed clock signal CLK _ delay is obtained. At this time, the clock signal input to the clock multi-phase circuit is CLK _ delay. The clock multi-path and multi-phase circuit processes the CLK _ delay to obtain clock signals with different paths and different phases.
In a specific implementation, a clocked multi-phase circuit may include: a second inverter and a second data selector, wherein: the input terminal of the second inverter is coupled to the output terminal of the clock signal delay circuit 12, and the output terminal of the second inverter is coupled to the first input terminal of the second data selector; a second input terminal of the second data selector is coupled to the output terminal of the clock signal delay circuit 12, and an output terminal of the second data selector is coupled to the clock signal input terminal of the SRAM; the enable signal input end of the second data selector can input different enable signals, and the second data selector selects and outputs a corresponding clock signal from the input signals of the two input ends according to the input enable signals.
For example, when the enable signal input from the enable signal input terminal is 0, the second data selector selects the clock signal input from the first input terminal as an output; when the enable signal input by the enable signal input terminal is 1, the second data selector selects the clock signal input by the second input terminal as an output.
Referring to fig. 3, a schematic diagram of a clock multiplexing multi-phase circuit according to an embodiment of the present invention is shown.
In fig. 3, a first input terminal of the second data selector 134 is coupled to the output terminal of the second inverter 133, and a second input terminal of the second data selector 134 is coupled to the output terminal of the clock signal delay circuit; an input of the second inverter 133 is coupled to an output of the clock signal delay circuit.
In the embodiment of the invention, the clock signals output by the clock signal delay circuit are subjected to multi-path and multi-phase processing to obtain clock signals with different paths and different phases, and the clock signals with different paths and different phases are output to the SRAM. When the threshold values of the pass and fail tests are obtained according to the output signals of the SRAM, the establishment and holding time of the SRAM can be determined according to clock signals of different paths and different phases, data signals of different paths and different paths, and the establishment and holding time of the SRAM with higher precision can be obtained.
In the embodiment of the present invention, when the data signal output terminal of the multi-way multi-phase selector 13 is coupled to the clock signal input terminal of the SRAM, the clock signal output terminal of the multi-way multi-phase selector 13 may be coupled to the data signal input terminal of the SRAM.
When the data signal output end of the multi-path multi-phase selector is coupled with the clock signal input end of the SRAM, the input end of the data multi-path multi-phase circuit is coupled with the output end of the data signal delay circuit, and the output end of the data multi-path multi-phase circuit is coupled with the clock signal input end of the SRAM, so that the data signal delay circuit is suitable for outputting data signals of different paths and different phases. At this time, the structure of the multi-way multi-phase selector may remain unchanged, that is: the structure of the data multi-phase circuit is the same as that of the data multi-phase circuit when the data signal output end of the multi-phase selector is coupled with the data signal input end of the SRAM. However, the output of the multi-way multi-phase selector is coupled to the clock signal input of the SRAM instead of the data signal input of the SRAM.
Specifically, the multi-way multi-phase selector may include a data multi-way multi-phase circuit when a data signal output terminal of the multi-way multi-phase selector is coupled to a clock signal input terminal of the SRAM. The input end of the data multi-phase circuit can be coupled with the output end of the data signal delay circuit, and the output end of the data multi-phase circuit can be coupled with the clock signal input end of the SRAM and is suitable for outputting data signals with different paths and different phases.
When the data signal output terminal of the multi-way multi-phase selector is coupled to the clock signal input terminal of the SRAM, the multi-way multi-phase selector may include a first inverter and a first data selector, wherein: the input end of the first inverter is coupled with the output end of the data signal delay circuit, and the output end of the first inverter is coupled with the first input end of the first data selector; the second input terminal of the first data selector is coupled to the output terminal of the data signal delay circuit, and the output terminal is coupled to the clock signal input terminal of the SRAM.
In the embodiment of the present invention, when the data signal output terminal of the multi-phase selector is coupled to the clock signal input terminal of the SRAM, the structure of the data multi-phase circuit can be as shown in fig. 2, except that the corresponding output terminal is coupled to the clock signal input terminal of the SRAM.
Accordingly, the multi-way multi-phase selector may further include a clocked multi-phase circuit when the clock signal output of the multi-way multi-phase selector is coupled to the data signal input of the SRAM. The clocked multi-phase circuit may include: a second inverter and a second data selector, wherein: the input end of the second inverter is coupled with the output end of the clock signal delay circuit, and the output end of the second inverter is coupled with the first input end of the second data selector; the second input terminal of the second data selector is coupled to the output terminal of the clock signal delay circuit, and the output terminal is coupled to the data signal input terminal of the SRAM.
In the embodiment of the present invention, when the data signal output terminal of the multi-phase selector is coupled to the clock signal input terminal of the SRAM, the structure of the clock multi-phase circuit can be as shown in fig. 2, except that the corresponding output terminal is coupled to the data signal input terminal of the SRAM.
In one embodiment, the multi-phase selector may include only a data multi-phase circuit, or may include both a data multi-phase circuit and a clock multi-phase circuit.
In the embodiment of the invention, the output end of the clock signal delay circuit is connected with the data signal input end of the SRAM, and the output end of the data signal delay circuit is connected with the clock signal input end of the SRAM, so that more combinations of clock signals and data signals can be obtained, and the SRAM establishment holding time can be further improved.
Referring to fig. 4, a schematic diagram of a multi-path multi-phase selector according to an embodiment of the present invention is shown. In fig. 4, the DATA signal input to the DATA signal input terminal of the multi-path multi-phase selector 13 is DATA _ delay, and the clock signal input to the clock signal input terminal is CLK _ delay. DATA _ delay is an output signal of the first delay circuit, and CLK _ delay is an output signal of the second delay circuit.
In fig. 4, the multi-path multi-phase selector includes: a data multi-phase circuit and a clock multi-phase circuit. The data multiplexing multiphase circuit includes: a first inverter 131 and a first data selector 132, wherein: the input terminal of the first inverter 131 inputs DATA _ delay, and the output terminal is coupled to a first input terminal of the first DATA selector 132; the second input terminal of the first DATA selector 132 inputs DATA _ delay, and the enable signal input terminal EN may input different enable signals, thereby selecting one between the DATA _ delay and the inverted signal of the DATA _ delay as an output.
The clock multiplexing multiphase circuit includes: a second inverter 133 and a second data selector 134, wherein: the input terminal of the second inverter 133 is inputted CLK _ delay, and the output terminal is coupled to the first input terminal of the second data selector 134; the second input terminal of the second data selector 134 inputs CLK _ delay, and the enable signal input terminal EN may input different enable signals, thereby selecting one between CLK _ delay and the inverse sign of CLK _ delay as an output.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (11)

1. An SRAM setup hold time test circuit, comprising:
the data signal delay circuit is coupled with the data signal input end of the multi-path multi-phase selector and is suitable for carrying out delay processing on the input data signal;
the clock signal delay circuit is coupled with the clock signal input end of the multi-path multi-phase selector and is suitable for carrying out delay processing on the input clock signal;
and the multi-path multi-phase selector is coupled with the SRAM, is suitable for carrying out multi-path multi-phase processing on one input data signal to obtain a plurality of data signals with different paths and different phases, and selects one data signal from the plurality of data signals with different paths and different phases to output to the SRAM.
2. The SRAM setup hold time test circuit of claim 1, wherein a data signal output of the multi-way multi-phase selector is coupled to a data signal input of the SRAM; the multi-path multi-phase selector includes: a data multi-path multi-phase circuit;
the data multi-path multi-phase circuit comprises an input end and an output end; the input end of the data multi-path multi-phase circuit is coupled with the output end of the data signal delay circuit, and the output end of the data multi-path multi-phase circuit is coupled with the data signal input end of the SRAM and is suitable for outputting data signals with different paths and different phases.
3. The SRAM setup hold time test circuit of claim 2, wherein the data muxing multi-phase circuit comprises:
a first inverter having an input coupled to the output of the data signal delay circuit and an output coupled to the first input of the first data selector;
a second input end of the first data selector is coupled with an output end of the data signal delay circuit, an output end of the first data selector is coupled with a data signal input end of the SRAM, and an enable signal input end of the first data selector inputs an enable signal; the first data selector is suitable for selecting and outputting a corresponding signal from the input signals of the two input ends according to different enabling signals.
4. The SRAM setup hold time test circuit of claim 2, wherein the multi-way multi-phase selector comprises a clock signal output; the clock signal output end of the multi-path multi-phase selector is coupled with the clock signal input end of the SRAM; the multi-path multi-phase selector further comprises: a clocked multi-phase circuit;
the clock multi-path multi-phase circuit comprises an input end and an output end; the input end of the clock multi-phase circuit is coupled with the output end of the clock signal delay circuit, and the output end of the clock multi-phase circuit is coupled with the clock signal input end of the SRAM and is suitable for outputting clock signals with different paths and different phases.
5. The SRAM setup hold time test circuit of claim 4, wherein the clock multiplexing multi-phase circuit comprises:
the input end of the second inverter is coupled with the output end of the clock signal delay circuit, and the output end of the second inverter is coupled with the first input end of the second data selector;
a second input end of the second data selector is coupled with an output end of the clock signal delay circuit, an output end of the second data selector is coupled with a clock signal input end of the SRAM, and an enable signal input end of the second data selector inputs an enable signal; the second data selector is suitable for selecting and outputting a corresponding signal from the input signals of the two input ends according to different enabling signals.
6. The SRAM setup hold time test circuit of claim 1, wherein a data signal output of the multi-way multi-phase selector is coupled to a clock signal input of the SRAM; the multi-path multi-phase selector includes: a data multi-path multi-phase circuit;
the data multi-path multi-phase circuit comprises an input end and an output end; the input end of the data multi-path multi-phase circuit is coupled with the output end of the data signal delay circuit, and the output end of the data multi-path multi-phase circuit is coupled with the clock signal input end of the SRAM and is suitable for outputting data signals with different paths and different phases.
7. The SRAM setup hold time test circuit of claim 6, wherein the data muxing multi-phase circuit comprises:
a first inverter having an input coupled to the output of the data signal delay circuit and an output coupled to the first input of the first data selector;
a second input end of the first data selector is coupled with an output end of the data signal delay circuit, an output end of the first data selector is coupled with a data signal input end of the SRAM, and an enable signal input end of the first data selector inputs an enable signal; the first data selector is suitable for selecting and outputting a corresponding signal from the input signals of the two input ends according to different enabling signals.
8. The SRAM setup hold time test circuit of claim 6, wherein the multi-way multi-phase selector comprises a clock signal output; the clock signal output end of the multi-path multi-phase selector is coupled with the data signal input end of the SRAM; the multi-path multi-phase selector further comprises: a clocked multi-phase circuit;
the clock multi-path multi-phase circuit comprises an input end and an output end; the input end of the clock multi-path multi-phase circuit is coupled with the output end of the clock signal delay circuit, the output end of the clock multi-path multi-phase circuit is coupled with the data signal input end of the SRAM, and the clock multi-path multi-phase circuit is suitable for outputting clock signals with different paths and different phases.
9. The SRAM setup hold time test circuit of claim 8, wherein the clock-multiplexed multi-phase circuit comprises:
the input end of the second inverter is coupled with the output end of the clock signal delay circuit, and the output end of the second inverter is coupled with the first input end of the second data selector;
a second input end of the second data selector is coupled with an output end of the clock signal delay circuit, an output end of the second data selector is coupled with a clock signal input end of the SRAM, and an enable signal input end of the second data selector inputs an enable signal; the second data selector is suitable for selecting and outputting a corresponding signal from the input signals of the two input ends according to different enabling signals.
10. The SRAM setup hold time test circuit of any one of claims 1 to 9, wherein the data signal delay circuit comprises: a D flip-flop and a first delay circuit, wherein:
the D end of the D trigger inputs the data signal, the clock signal input end inputs the clock signal, and the output end is coupled with the data signal input end of the first delay circuit;
and the output end of the first delay circuit is coupled with the data signal input end of the multi-path multi-phase selector, and the control end of the first delay circuit is suitable for inputting a first delay control signal.
11. The SRAM setup hold time test circuit of claim 10, wherein the clock signal delay circuit comprises: a delay matching circuit and a second delay circuit, wherein:
the clock signal input end of the delay matching circuit inputs the clock signal, and the output end of the delay matching circuit is coupled with the clock signal input end of the second delay circuit and is suitable for synchronizing the rising edge of the clock signal with the rising edge of the output signal of the D trigger;
and the output end of the second delay circuit is coupled with the clock signal input end of the multi-path multi-phase selector, and the control end of the second delay circuit is suitable for inputting a second delay control signal.
CN201810027540.7A 2018-01-11 2018-01-11 SRAM establishment holding time test circuit Active CN110033819B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810027540.7A CN110033819B (en) 2018-01-11 2018-01-11 SRAM establishment holding time test circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810027540.7A CN110033819B (en) 2018-01-11 2018-01-11 SRAM establishment holding time test circuit

Publications (2)

Publication Number Publication Date
CN110033819A CN110033819A (en) 2019-07-19
CN110033819B true CN110033819B (en) 2021-03-09

Family

ID=67234302

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810027540.7A Active CN110033819B (en) 2018-01-11 2018-01-11 SRAM establishment holding time test circuit

Country Status (1)

Country Link
CN (1) CN110033819B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113589152B (en) * 2020-04-30 2024-02-27 中芯国际集成电路制造(上海)有限公司 Test circuit
CN113740717A (en) * 2020-05-29 2021-12-03 深圳市中兴微电子技术有限公司 Method and circuit for measuring retention time of time sequence unit
CN113740718A (en) * 2020-05-29 2021-12-03 深圳市中兴微电子技术有限公司 Method and circuit for measuring time sequence unit establishing time
CN113884865B (en) * 2020-07-01 2023-12-01 复旦大学 Test circuit and test method of D trigger

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05259832A (en) * 1992-01-13 1993-10-08 Hitachi Ltd Hold type latch circuit and semiconductor storage device
JPH10228779A (en) * 1997-02-18 1998-08-25 Toshiba Corp Semiconductor integrated circuit and semiconductor memory
JP2001006400A (en) * 1999-06-18 2001-01-12 Fujitsu Ltd Memory device
US6424198B1 (en) * 2001-08-09 2002-07-23 International Business Machines Corporation Memory clock generation with configurable phase advance and delay capability
JP4208127B2 (en) * 2003-06-02 2009-01-14 パナソニック株式会社 Semiconductor integrated circuit device
KR20090008663A (en) * 2007-07-18 2009-01-22 (주)태터 앤 컴퍼니 Method and device for providing service of accessing to anonymous others located near place through network
FR2901362B1 (en) * 2006-05-19 2011-03-11 St Microelectronics Sa CIRCUIT FOR QUALIFYING AND CHARACTERIZING A MEMORY EMBARKED IN A SEMICONDUCTOR PRODUCT
CN105262464A (en) * 2015-11-16 2016-01-20 西安华芯半导体有限公司 Circuit and method for reducing required retention time at chip input port
CN105759195A (en) * 2016-02-24 2016-07-13 复旦大学 Setup-hold time test system and setup-hold time test method based on fine phase modulation
CN106448744A (en) * 2016-09-22 2017-02-22 广东威创视讯科技股份有限公司 DDR time sequence analysis method, device and system

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4301680B2 (en) * 2000-02-29 2009-07-22 株式会社ルネサステクノロジ Semiconductor integrated circuit device
KR100356806B1 (en) * 2000-12-28 2002-10-18 주식회사 하이닉스반도체 Dq comparator for built in self test of sdram
JP2003100100A (en) * 2001-07-19 2003-04-04 Mitsubishi Electric Corp Semiconductor integrated circuit device
KR100403635B1 (en) * 2001-11-06 2003-10-30 삼성전자주식회사 Data input circuit and data input method for synchronous semiconductor memory device
TWI459360B (en) * 2011-08-09 2014-11-01 Raydium Semiconductor Corp Source driver with automatic de-skew capability

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05259832A (en) * 1992-01-13 1993-10-08 Hitachi Ltd Hold type latch circuit and semiconductor storage device
JPH10228779A (en) * 1997-02-18 1998-08-25 Toshiba Corp Semiconductor integrated circuit and semiconductor memory
JP2001006400A (en) * 1999-06-18 2001-01-12 Fujitsu Ltd Memory device
US6424198B1 (en) * 2001-08-09 2002-07-23 International Business Machines Corporation Memory clock generation with configurable phase advance and delay capability
JP4208127B2 (en) * 2003-06-02 2009-01-14 パナソニック株式会社 Semiconductor integrated circuit device
FR2901362B1 (en) * 2006-05-19 2011-03-11 St Microelectronics Sa CIRCUIT FOR QUALIFYING AND CHARACTERIZING A MEMORY EMBARKED IN A SEMICONDUCTOR PRODUCT
KR20090008663A (en) * 2007-07-18 2009-01-22 (주)태터 앤 컴퍼니 Method and device for providing service of accessing to anonymous others located near place through network
CN105262464A (en) * 2015-11-16 2016-01-20 西安华芯半导体有限公司 Circuit and method for reducing required retention time at chip input port
CN105759195A (en) * 2016-02-24 2016-07-13 复旦大学 Setup-hold time test system and setup-hold time test method based on fine phase modulation
CN106448744A (en) * 2016-09-22 2017-02-22 广东威创视讯科技股份有限公司 DDR time sequence analysis method, device and system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
一种基于全数字锁相环的SRAM实速测试方案;张立军等;《微电子学》;20120228;第1-3部分及附图2-4 *

Also Published As

Publication number Publication date
CN110033819A (en) 2019-07-19

Similar Documents

Publication Publication Date Title
CN110033819B (en) SRAM establishment holding time test circuit
US7038494B2 (en) Scan chain element and associated method
EP1890234B1 (en) Microcomputer and method for testing the same
US8841952B1 (en) Data retention flip-flop
JP2007108172A (en) Apparatus for measuring on-chip characteristics of semiconductor circuit, and method therefor
CN115856590B (en) Test circuit, zero period same-edge sampling circuit, test method and electronic equipment
CN107068192B (en) Local clock signal generation circuit for timing measurement of memory
CN116384306A (en) Time sequence simulation verification method, verification device, electronic equipment and readable storage medium
US7080302B2 (en) Semiconductor device and test system therefor
US20090302917A1 (en) Delay circuit and test method for delay circuit
US7421634B2 (en) Sequential scan based techniques to test interface between modules designed to operate at different frequencies
US9599673B2 (en) Structural testing of integrated circuits
US20140140159A1 (en) Short asynchronous glitch
US20090063086A1 (en) Apparatus for testing semiconductor integrated circuit and method for testing semiconductor integrated circuit
US11493553B2 (en) Extended JTAG controller and method for functional reset using the extended JTAG controller
KR20060052957A (en) Test device
US6182255B1 (en) IC tester
US8008935B1 (en) Tester and a method for testing an integrated circuit
KR100294718B1 (en) Linear Feedback Shift Registers and Semiconductor Integrated Circuit Devices
KR20000038589A (en) Tester for semiconductor device
CN112666444B (en) Chip FT test method and system
US20230384362A1 (en) Speed detection circuit and associated chip
US20110145644A1 (en) Protocol sequence generator
CN115389857B (en) Signal cable delay detection system based on symmetrical circuit
US20050240846A1 (en) Accurate Generation of Scan Enable Signal when Testing Integrated Circuits Using Sequential Scanning Techniques

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant