CN110033819A - SRAM establishes retention time test circuit - Google Patents
SRAM establishes retention time test circuit Download PDFInfo
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- CN110033819A CN110033819A CN201810027540.7A CN201810027540A CN110033819A CN 110033819 A CN110033819 A CN 110033819A CN 201810027540 A CN201810027540 A CN 201810027540A CN 110033819 A CN110033819 A CN 110033819A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
Abstract
A kind of SRAM establishes retention time test circuit, comprising: data-signal delay circuit is coupled with the data signal input of multichannel multiphase selector, suitable for carrying out delay disposal to the data-signal of input；Clock signal delay circuit is coupled with the clock signal input terminal of the multichannel multiphase selector, suitable for carrying out delay disposal to the clock signal of input；Multichannel multiphase selector, it is coupled with SRAM, suitable for input data-signal and clock signal carry out the processing of multichannel multiphase, obtain the data-signal in different paths and out of phase and clock signal and export via the data-signal and clock signal output terminal to the SRAM.Above scheme can accurately acquire SRAM and establish the retention time.
Description
Technical field
The present embodiments relate to circuit fields more particularly to a kind of SRAM to establish retention time test circuit.
Background technique
Establish the retention time (setup/hold time), including settling time and retention time, in which: settling time is
Refer to before the rising edge clock signal of trigger arrives, the data stabilization constant time；Retention time refers in trigger
After rising edge clock signal arrives, the data stabilization constant time.
In system on chip (System On Chip, SoC), if being unable to satisfy static random access memory (Static
Random Access Memory, SRAM) establish the retention time, then may generating metastable phenomenon, cause SRAM to read and write
Error.
When SRAM establish the retention time it is larger when, will lead to chip working frequency reduce.Therefore, in practical application
In, it needs test to obtain accurate SRAM and establishes the retention time.
Summary of the invention
What the embodiment of the present invention solved is how to accurately acquire SRAM to establish the retention time.
In order to solve the above technical problems, the embodiment of the present invention, which provides a kind of SRAM, establishes retention time test circuit, comprising:
Data-signal delay circuit is coupled with the data signal input of multichannel multiphase selector, suitable for the data-signal to input into
Row delay disposal；Clock signal delay circuit couples with the clock signal input terminal of the multichannel multiphase selector, is suitable for defeated
The clock signal entered carries out delay disposal；Multichannel multiphase selector is coupled with SRAM, more suitable for carrying out to the data-signal of input
Multiphase processing in road obtains the data-signal in different paths and out of phase and exports to the SRAM.
Optionally, the data signal input coupling of the data signal output of the multichannel multiphase selector and the SRAM
It connects；The multichannel multiphase selector includes: data multiplex polyphase circuit；The data multiplex polyphase circuit, including input terminal with
And output end；The output end of the input terminal of the data multiplex polyphase circuit and the data-signal delay circuit couples, described
The data signal input of the output end of data multiplex polyphase circuit and the SRAM couple, suitable for the different paths of output and not
The data-signal of same-phase.
Optionally, the data multiplex polyphase circuit includes: the first phase inverter, input terminal and the data-signal deferred telegram
The output end on road couples, and the first input end of output end and the first data selector couples；First data selector, second
The output end of input terminal and the data-signal delay circuit couples, the data signal input coupling of output end and the SRAM
It connects, enable signal input terminal inputs enable signal；First data selector is suitable for according to different enable signals, from two
A corresponding signal is selected in the input signal of input terminal and is exported.
Optionally, the multichannel multiphase selector includes clock signal output terminal；The clock of the multichannel multiphase selector
The clock signal input terminal of signal output end and the SRAM couple；The multichannel multiphase selector, further includes: clock multichannel is more
Circuitry phase；The clock multichannel polyphase circuit, including input terminal and output end；The input terminal of the clock multichannel polyphase circuit
Coupled with the output end of the clock signal delay circuit, the output end of the clock multichannel polyphase circuit and the SRAM when
Clock signal input part coupling, suitable for exporting the clock signal in different paths and out of phase.
Optionally, the clock multichannel polyphase circuit includes: the second phase inverter, input terminal and clock signal delay electricity
The output end on road couples, and the first input end of output end and the second data selector couples；Second data selector, second
The output end of input terminal and the clock signal delay circuit couples, the clock signal input terminal coupling of output end and the SRAM
It connects, enable signal input terminal inputs enable signal；Second data selector is suitable for according to different enable signals, from two
A corresponding signal is selected in the input signal of input terminal and is exported.
Optionally, the clock signal input terminal coupling of the data signal output of the multichannel multiphase selector and the SRAM
It connects；The multichannel multiphase selector includes: data multiplex polyphase circuit；The data multiplex polyphase circuit, including input terminal with
And output end；The output end of the input terminal of the data multiplex polyphase circuit and the data-signal delay circuit couples, described
The clock signal input terminal of the output end of data multiplex polyphase circuit and the SRAM couple, suitable for the different paths of output and not
The data-signal of same-phase.
Optionally, the data multiplex polyphase circuit includes: the first phase inverter, input terminal and the data-signal deferred telegram
The output end on road couples, and the first input end of output end and the first data selector couples；First data selector, second
The output end of input terminal and the data-signal delay circuit couples, the data signal input coupling of output end and the SRAM
It connects, enable signal input terminal inputs enable signal；First data selector is suitable for according to different enable signals, from two
A corresponding signal is selected in the input signal of input terminal and is exported.
Optionally, the multichannel multiphase selector includes clock signal output terminal；The clock of the multichannel multiphase selector
The data signal input of signal output end and the SRAM couple；The multichannel multiphase selector, further includes: clock multichannel is more
Circuitry phase；The clock multichannel polyphase circuit, including input terminal and output end；The input terminal of the clock multichannel polyphase circuit
It is coupled with the output end of the clock signal delay circuit, the output end of the clock multichannel polyphase circuit and the number of the SRAM
It is coupled according to signal input part, suitable for exporting the clock signal in different paths and out of phase.
Optionally, the clock multichannel polyphase circuit, comprising: the second phase inverter, input terminal and the clock signal delay
The output end of circuit couples, and the first input end of output end and the second data selector couples；Second data selector, the
The output end of two input terminals and the clock signal delay circuit couples, the clock signal input terminal coupling of output end and the SRAM
It connects, enable signal input terminal inputs enable signal；Second data selector is suitable for according to different enable signals, from two
A corresponding signal is selected in the input signal of input terminal and is exported.
Optionally, the data-signal delay circuit, comprising: d type flip flop and the first delay circuit, in which: the D touching
Device is sent out, the end D inputs the data-signal, and clock signal input terminal inputs the clock signal, output end and first delay
The data signal input of circuit couples；The data of first delay circuit, output end and the multichannel multiphase selector are believed
The coupling of number input terminal, control terminal are suitable for the first delayed control signal of input.
Optionally, the clock signal delay circuit, comprising: delay matching circuit and the second delay circuit, in which: institute
Delay matching circuit is stated, clock signal input terminal inputs the clock signal, the clock of output end and second delay circuit
Signal input part coupling, suitable for by the rising edge synch of the rising edge of the clock signal and the output signal of the d type flip flop；
The clock signal input terminal of second delay circuit, output end and the multichannel multiphase selector couples, and control terminal is suitable for defeated
Enter the second delayed control signal.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
The processing of multichannel multiphase is carried out to the data-signal of data-signal delay circuit output, obtains different paths and difference
The data-signal of phase, and the data-signal in different paths and out of phase is exported to SRAM.Believed according to the output of SRAM
Number obtaining test passes through the critical value with test crash, obtains data-signal delay circuit corresponding delay time, clock signal
Delay circuit corresponding delay time, to know that SRAM establishes the retention time.It is logical that test is obtained according to the output signal of SRAM
It crosses and establishes the retention time with the critical value of test crash to obtain SRAM, it is corresponding that data-signal delay circuit can be accurately determined
Delay time, clock signal delay circuit corresponding delay time, therefore SRAM can be accurately acquired and establish the retention time.
Further, the processing of multichannel multiphase is carried out to the clock signal of clock signal delay circuit output, obtains different paths
And the clock signal of out of phase, and the clock signal in different paths and out of phase is exported to SRAM.In basis
It, can be according to different paths and out of phase when the output signal of SRAM obtains test by critical value with test crash
The data-signal of clock signal, different paths and different paths determines establishing the retention time for SRAM, available more high-precision
The SRAM of degree establishes the retention time.
In addition, the data signal input of the output end of clock signal delay circuit and SRAM are connected, by data-signal
The output end of delay circuit and the clock signal input terminal of SRAM connect, available more kinds of clock signals and data-signal
Combination, establish the retention time so as to further increase SRAM.
Detailed description of the invention
Fig. 1 is the structural schematic diagram that one of embodiment of the present invention SRAM establishes retention time test circuit；
Fig. 2 is the structural schematic diagram of one of embodiment of the present invention data multiplex polyphase circuit；
Fig. 3 is the structural schematic diagram of one of embodiment of the present invention clock multichannel polyphase circuit；
Fig. 4 is the structural schematic diagram of another multichannel multiphase selector in the embodiment of the present invention.
Specific embodiment
In system on chip (System On Chip, SoC), (setup/hold is established the retention time as SRAM
Time when) larger, the working frequency that will lead to chip is reduced.Therefore, in practical applications, need to test and obtain accurate SRAM
Establish the retention time.
In the prior art, the retention time is established to test SRAM using Static Timing Analysis Methodology.However, using quiet
When state Time Series Analysis Method, the rising edge of data-signal and failing edge are not distinguished, the SRAM for causing test to obtain is built
Vertical retention time precision is poor.
In the present invention is implemented, the processing of multichannel multiphase is carried out to the data-signal of data-signal delay circuit output, obtained
The data-signal of different paths and out of phase, and the data-signal in different paths and out of phase is exported to SRAM.
Test is obtained by the critical value with test crash according to the output signal of SRAM, obtains that data-signal delay circuit is corresponding to be prolonged
Slow time, clock signal delay circuit corresponding delay time, to know that SRAM establishes the retention time.According to the output of SRAM
Signal acquisition test establishes the retention time by the critical value with test crash to obtain SRAM, can be accurately determined data letter
Number delay circuit corresponding delay time, clock signal delay circuit corresponding delay time, therefore SRAM can be accurately acquired
Establish the retention time.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Referring to Fig.1, the embodiment of the invention provides a kind of SRAM to establish retention time test circuit, comprising: data-signal
Delay circuit 11, clock signal delay circuit 12 and multichannel multiphase selector 13, in which:
Data-signal delay circuit 11 couples with the data signal input of multichannel multiphase selector 13, is suitable for input
Data-signal DATA carry out delay disposal；
Clock signal delay circuit 12 couples with the clock signal input terminal of multichannel multiphase selector 13, is suitable for input
Clock signal clk carry out delay disposal；
Multichannel multiphase selector 13 is coupled with SRAM 14, suitable for carrying out the processing of multichannel multiphase to the data-signal of input,
It obtains the data-signal in different paths and out of phase and exports via the data signal output to the SRAM 14.
Retention time test circuit is established to the SRAM in Fig. 1 below to be described in detail.
In specific implementation, data-signal delay circuit 11 may include: that data signal input and data-signal are defeated
Outlet.The data signal input input data signal DATA of data-signal delay circuit 11, data signal output and multichannel
The data signal input of multiphase selector 13 couples.By 11 pairs of data-signal delay circuit input data-signal DATA into
Row delay disposal, and the data-signal after delay disposal is exported to the data signal input of multichannel multiphase selector 13.
Correspondingly, clock signal delay circuit 12 may include: clock signal input terminal and clock signal output terminal.When
The clock signal input terminal input clock signal CLK of clock signal delay circuit 12, clock signal output terminal and multichannel multiphase select
The clock signal input terminal of device 13 couples.The clock signal clk inputted by 12 Duis of clock signal delay circuit carries out at delay
Reason, and the clock signal after delay disposal is exported to the clock signal input terminal of multichannel multiphase selector 13.
That is, the data signal input of multichannel multiphase selector 13 inputs: passing through data-signal deferred telegram
Data-signal after 11 delay disposal of road；The clock signal input terminal of multichannel multiphase selector 13 inputs: through oversampling clock
Clock signal after 12 delay disposal of signal delay circuit.
Referring to Fig.1, in embodiments of the present invention, data-signal delay circuit 11 may include: d type flip flop 111 and
One delay circuit 112, in which: the end the D input data signal DATA of d type flip flop 111, the clock signal input terminal clk of d type flip flop
The data signal input of input clock signal CLK, the output end of d type flip flop 111 and the first delay circuit 112 couples；First
The output end of delay circuit 112 and the data signal input of multichannel multiphase selector 13 couple, the control of the first delay circuit 112
End ctr1 processed is suitable for the first delayed control signal of input.
In specific implementation, it is not co-extensive can to input characterization in the control terminal ctr1 of the first delay circuit 112 by tester
The first delayed control signal of slow time.First delay control circuit 112 according to the first different delayed control signals of input,
Corresponding delay disposal is carried out to data-signal.
Clock signal delay circuit 12 may include delay matching circuit 121 and the second delay circuit 122, in which: prolong
The clock signal input terminal input clock signal CLK of slow match circuit 121, the output end of delay matching circuit 121 prolong with second
The clock signal input terminal coupling of slow circuit 122；122 output ends of the second delay circuit and the clock of multichannel multiphase selector 13
Signal input part coupling, the control terminal ctr2 of the second delay circuit are suitable for the second delayed control signal of input.Implement in the present invention
In example, by delay matching circuit 121, the output of the rising edge of the clock signal clk of input and d type flip flop 111 can be believed
Number rising edge synch.
In specific implementation, it is not co-extensive can to input characterization in the control terminal ctr2 of the second delay circuit 122 by tester
The second delayed control signal of slow time, the second delay control circuit 122 according to the second different delayed control signals of input,
Corresponding delay disposal is carried out to clock signal.
In practical applications, the first delay circuit 112 and the second delay circuit 122 all can be 32 delay circuits.
In specific implementation, the data signal output of multichannel multiphase selector 13 can be with the data-signal of SRAM 14
Input terminal coupling, can also couple with the clock signal input terminal of SRAM 14.Correspondingly, when the number of multichannel multiphase selector 13
When being coupled according to the data signal input of signal output end and SRAM 14, the clock signal output terminal of multichannel multiphase selector 13
It is coupled with the clock signal input terminal of SRAM 14；When the data signal output of multichannel multiphase selector 13 and SRAM 14 when
When clock signal input part couples, the clock signal output terminal of multichannel multiphase selector 13 and the data signal input of SRAM 14
Coupling.Above-mentioned scene is illustrated separately below.
In embodiments of the present invention, the data-signal of the data signal output of multichannel multiphase selector 13 and SRAM 14
When input terminal couples, the clock signal output terminal of multichannel multiphase selector 13 and the clock signal input terminal of SRAM 14 are coupled.
Multichannel multiphase selector 13 may include: data multiplex polyphase circuit.In embodiments of the present invention, data multiplex is more
Circuitry phase may include input terminal and output end.When the data signal output of multichannel multiphase selector 13 is with SRAM's 14
When data signal input couples, the input terminal of data multiplex polyphase circuit and the output end coupling of data-signal delay circuit 11
It connects, the output end of data multiplex polyphase circuit and the data signal input of SRAM 14 couple.
Data multiplex polyphase circuit inputs the data-signal after 11 delay disposal of data-signal delay circuit, and to warp
Data-signal after crossing delay disposal carries out the processing of multichannel multiphase, obtains the data-signal in different paths and out of phase and defeated
Enter to the data signal input of SRAM 14.
For example, the data-signal for being input to data-signal delay circuit 11 is DATA.DATA passes through data-signal deferred telegram
After road 11 is handled, the data-signal DATA_delay after being postponed.At this point, being input to the data of data multiplex polyphase circuit
Signal is DATA_delay.Data multiplex polyphase circuit handles DATA_delay, obtains different paths and different phases
The data-signal of position.
In specific implementation, data multiplex polyphase circuit may include: the first phase inverter and the first data selector,
In: the output end of the input terminal of the first phase inverter and data-signal delay circuit 11 couples, the output end of the first phase inverter and the
The first input end of one data selector couples；Second input terminal of the first data selector and data-signal delay circuit 11
Output end coupling, the output end of the first data selector and the data signal input of SRAM couple；First data selector
Enable signal input terminal can input different enable signals, and according to the enable signal of input, the first data selector is from two
A corresponding data-signal is selected in the input signal of input terminal and is exported.
For example, first data selector selects first input end when the enable signal of enable signal input terminal input is 0
The data-signal of input is as output；When the enable signal of enable signal input terminal input is 1, the selection of the first data selector
The data-signal of second input terminal input is as output.
Referring to Fig. 2, the structural schematic diagram of one of embodiment of the present invention data multiplex polyphase circuit is given.
In Fig. 2, the output end of the first input end of the first data selector 132 and the first phase inverter 131 is coupled, the first number
It is coupled according to the second input terminal of selector 132 and the output end of data-signal delay circuit 11；The input terminal of first phase inverter 131
It is coupled with the output end of data-signal delay circuit 11.
Below with reference to Fig. 1 and Fig. 2, retention time test circuit is established to the SRAM provided in the above embodiment of the present invention
Working principle be illustrated.
When carrying out SRAM and establishing retention time test, tester can input the in the control terminal of the first delay circuit
One delayed control signal inputs the second delayed control signal in the control terminal of the second delay circuit.First delayed control signal pair
The first delay duration the second delay time corresponding with the second delayed control signal answered may be the same or different.
Data-signal of the input terminal input of multichannel multiphase selector 13 by the first delay duration, output end output are multiple
The data-signal of different paths and out of phase is to SRAM.At this point, the output signal of SRAM and multichannel multiphase selector 13 are defeated
The number of data-signal out is identical.According to the different data-signals that multichannel multiphase selector 13 exports, SRAM is therefrom obtained
Test passes through and the corresponding critical value of SRAM test crash, and obtains the first delay duration and the second delay according to critical value
Duration, and then obtain SRAM and establish the retention time.That is, SRAM establish the retention time be according to multiple and different paths with
And the data-signal of out of phase obtains, therefore can be accurately determined data-signal delay circuit corresponding delay time,
The corresponding delay time of clock signal delay circuit 12, therefore SRAM can be accurately acquired and establish the retention time.
It in specific implementation, can also include clock multichannel polyphase circuit in multichannel multiphase selector 13.Clock multichannel is more
The input terminal of circuitry phase and the output end of clock signal delay circuit 12 couple, the output end and SRAM of clock multichannel polyphase circuit
Clock signal input terminal coupling
Clock multichannel polyphase circuit inputs the clock signal after 12 delay disposal of clock signal delay circuit, and to warp
Clock signal after crossing delay disposal carries out the processing of multichannel multiphase, obtains the clock signal in different paths and out of phase and defeated
Enter to the clock input terminal of SRAM.
For example, the clock signal for being input to clock signal delay circuit 12 is CLK.CLK passes through clock signal delay circuit
After 12 processing, clock signal clk _ delay after being postponed.At this point, being input to the clock letter of clock multichannel polyphase circuit
Number be CLK_delay.Clock multichannel polyphase circuit handles CLK_delay, obtains different paths and out of phase
Clock signal.
In specific implementation, clock multichannel polyphase circuit may include: the second phase inverter and the second data selector,
In: the output end of the input terminal of the second phase inverter and clock signal delay circuit 12 couples, the output end of the second phase inverter and the
The first input end of two data selectors couples；Second input terminal of the second data selector and clock signal delay circuit 12
Output end coupling, the output end of the second data selector and the clock signal input terminal of SRAM couple；Second data selector
Enable signal input terminal can input different enable signals, and according to the enable signal of input, the second data selector is from two
A corresponding clock signal is selected in the input signal of input terminal and is exported.
For example, second data selector selects first input end when the enable signal of enable signal input terminal input is 0
The clock signal of input is as output；When the enable signal of enable signal input terminal input is 1, the selection of the second data selector
The clock signal of second input terminal input is as output.
Referring to Fig. 3, the structural schematic diagram of one of embodiment of the present invention clock multichannel polyphase circuit is given.
In Fig. 3, the output end of the first input end of the second data selector 134 and the second phase inverter 133 is coupled, the second number
It is coupled according to the second input terminal of selector 134 and the output end of clock signal delay circuit；The input terminal of second phase inverter 133 with
The output end of clock signal delay circuit couples.
In embodiments of the present invention, the processing of multichannel multiphase is carried out to the clock signal of clock signal delay circuit output, obtained
To different paths and the clock signal of out of phase, and by the clock signal in different paths and out of phase export to
SRAM.When obtaining test by critical value with test crash according to the output signal of SRAM, can according to different paths with
And clock signal, different paths and the data-signal in different paths of out of phase determine that SRAM's establishes the retention time, it can
The retention time is established to obtain the SRAM of higher precision.
In embodiments of the present invention, when the data signal output of multichannel multiphase selector 13 and the clock signal of SRAM are defeated
When entering end coupling, the clock signal output terminal of multichannel multiphase selector 13 can be coupled with the data signal input of SRAM.
When the coupling of the clock signal input terminal of the data signal output of multichannel multiphase selector and SRAM, data multiplex
The input terminal of polyphase circuit and the output end of data-signal delay circuit couple, the output end and SRAM of data multiplex polyphase circuit
Clock signal input terminal coupling, suitable for exporting the data-signal in different paths and out of phase.At this point, multichannel multiphase selects
The structure of device can remain unchanged, namely: it is defeated with the data signal output of multichannel multiphase selector and the data-signal of SRAM
The structure for entering the data multiplex polyphase circuit when coupling of end is identical.But the output end of multichannel multiphase selector at this time be with
The clock signal input terminal of SRAM couples, rather than couples with the data signal input of SRAM.
Specifically, when the data signal output of multichannel multiphase selector and the clock signal input terminal of SRAM couple
When, multichannel multiphase selector may include data multiplex polyphase circuit.The input terminal of data multiplex polyphase circuit can be with data
The output end of signal delay circuit couples, and the output end of data multiplex polyphase circuit can be with the clock signal input terminal coupling of SRAM
It connects, suitable for exporting the data-signal in different paths and out of phase.
When the coupling of the clock signal input terminal of the data signal output of multichannel multiphase selector and SRAM, multichannel multiphase
Selector may include the first phase inverter and the first data selector, in which: the input terminal and data-signal of the first phase inverter
The output end of delay circuit couples, and the first input end of the output end of the first phase inverter and the first data selector couples；First
Second input terminal of data selector and the output end of data-signal delay circuit couple, and the clock signal of output end and SRAM are defeated
Enter end coupling.
In embodiments of the present invention, when the data signal output of multichannel multiphase selector and the clock signal input of SRAM
When the coupling of end, the structure of data multiplex polyphase circuit is referred to shown in Fig. 2, and only the clock of corresponding output end and SRAM are believed
The coupling of number input terminal.
Correspondingly, when the data signal input of the clock signal output terminal of multichannel multiphase selector and SRAM couple,
Multichannel multiphase selector can also include clock multichannel polyphase circuit.Clock multichannel polyphase circuit may include: the second phase inverter
And second data selector, in which: the output end of the second phase inverter, input terminal and clock signal delay circuit couples, output
End and the first input end of the second data selector couple；The second input terminal and the clock signal delay electricity of second data selector
The output end on road couples, and the data signal input of output end and SRAM couple.
In embodiments of the present invention, when the data signal output of multichannel multiphase selector and the clock signal input of SRAM
When the coupling of end, the structure of clock multichannel polyphase circuit is referred to shown in Fig. 2, and only the data of corresponding output end and SRAM are believed
The coupling of number input terminal.
In specific implementation, multichannel multiphase selector can only include data multiplex polyphase circuit, can also include simultaneously
Data multiplex polyphase circuit and clock multichannel polyphase circuit.
In embodiments of the present invention, the data signal input of the output end of clock signal delay circuit and SRAM are connected
It connects, the clock signal input terminal of the output end of data-signal delay circuit and SRAM is connected, available more kinds of clock letters
Number and data-signal combination, establish the retention time so as to further increase SRAM.
Referring to Fig. 4, the structural schematic diagram of one of embodiment of the present invention multichannel multiphase selector is given.It is more in Fig. 4
The data-signal of the data signal input input of road multiphase selector 13 is DATA_delay, clock signal input terminal input
Clock signal is CLK_delay.DATA_delay is the output signal of the first delay circuit, and CLK_delay is the second deferred telegram
The output signal on road.
In Fig. 4, multichannel multiphase selector includes: data multiplex polyphase circuit and clock multichannel polyphase circuit.Data are more
Road polyphase circuit includes: the first phase inverter 131 and the first data selector 132, in which: the input terminal of the first phase inverter 131
Input DATA_delay, the first input end coupling of output end and the first data selector 132；First data selector 132
Second input terminal inputs DATA_delay, and enable signal input terminal EN can input different enable signals, thus in DATA_
Selected between delay and the inversion signal of DATA_delay one as output.
Clock multichannel polyphase circuit includes: the second phase inverter 133 and the second data selector 134, in which: the second reverse phase
The input terminal of device 133 inputs CLK_delay, the first input end coupling of output end and the second data selector 134；Second data
Second input terminal of selector 134 inputs CLK_delay, and enable signal input terminal EN can input different enable signals, from
And selected between CLK_delay and the reverse phase number of CLK_delay one as output.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (11)
1. a kind of SRAM establishes retention time test circuit characterized by comprising
Data-signal delay circuit is coupled with the data signal input of multichannel multiphase selector, suitable for the data letter to input
Number carry out delay disposal；
Clock signal delay circuit is coupled with the clock signal input terminal of the multichannel multiphase selector, suitable for input when
Clock signal carries out delay disposal；
Multichannel multiphase selector is coupled with SRAM, suitable for carrying out the processing of multichannel multiphase to the data-signal of input, is not gone the same way
Diameter and the data-signal of out of phase are simultaneously exported to the SRAM.
2. SRAM as described in claim 1 establishes retention time test circuit, which is characterized in that the multichannel multiphase selector
Data signal output and the SRAM data signal input couple；The multichannel multiphase selector includes: that data are more
Road polyphase circuit；
The data multiplex polyphase circuit, including input terminal and output end；The input terminal of the data multiplex polyphase circuit with
The output end of the data-signal delay circuit couples, the output end of the data multiplex polyphase circuit and the data of the SRAM
Signal input part coupling, suitable for exporting the data-signal in different paths and out of phase.
3. SRAM as claimed in claim 2 establishes retention time test circuit, which is characterized in that the data multiplex multiphase electricity
Road includes:
The output end of first phase inverter, input terminal and the data-signal delay circuit couples, and output end and the first data select
The first input end of device couples；
The output end of first data selector, the second input terminal and the data-signal delay circuit couples, output end with
The data signal input of the SRAM couples, and enable signal input terminal inputs enable signal；First data selector is suitable
According to different enable signals, a corresponding signal is selected from the input signal of two input terminals and is exported.
4. SRAM as claimed in claim 2 establishes retention time test circuit, which is characterized in that the multichannel multiphase selector
Including clock signal output terminal；The clock signal output terminal of the multichannel multiphase selector and the clock signal input of the SRAM
End coupling；The multichannel multiphase selector, further includes: clock multichannel polyphase circuit；
The clock multichannel polyphase circuit, including input terminal and output end；The input terminal of the clock multichannel polyphase circuit with
The output end of the clock signal delay circuit couples, the output end of the clock multichannel polyphase circuit and the clock of the SRAM
Signal input part coupling, suitable for exporting the clock signal in different paths and out of phase.
5. SRAM as claimed in claim 4 establishes retention time test circuit, which is characterized in that the clock multichannel multiphase electricity
Road includes:
The output end of second phase inverter, input terminal and the clock signal delay circuit couples, and output end and the second data select
The first input end of device couples；
The output end of second data selector, the second input terminal and the clock signal delay circuit couples, output end with
The clock signal input terminal of the SRAM couples, and enable signal input terminal inputs enable signal；Second data selector is suitable
According to different enable signals, a corresponding signal is selected from the input signal of two input terminals and is exported.
6. SRAM as described in claim 1 establishes retention time test circuit, which is characterized in that the multichannel multiphase selector
Data signal output and the SRAM clock signal input terminal couple；The multichannel multiphase selector includes: that data are more
Road polyphase circuit；
The data multiplex polyphase circuit, including input terminal and output end；The input terminal of the data multiplex polyphase circuit with
The output end of the data-signal delay circuit couples, the output end of the data multiplex polyphase circuit and the clock of the SRAM
Signal input part coupling, suitable for exporting the data-signal in different paths and out of phase.
7. SRAM as claimed in claim 6 establishes retention time test circuit, which is characterized in that the data multiplex multiphase electricity
Road includes:
The output end of first phase inverter, input terminal and the data-signal delay circuit couples, and output end and the first data select
The first input end of device couples；
The output end of first data selector, the second input terminal and the data-signal delay circuit couples, output end with
The data signal input of the SRAM couples, and enable signal input terminal inputs enable signal；First data selector is suitable
According to different enable signals, a corresponding signal is selected from the input signal of two input terminals and is exported.
8. SRAM as claimed in claim 6 establishes retention time test circuit, which is characterized in that the multichannel multiphase selector
Including clock signal output terminal；The clock signal output terminal of the multichannel multiphase selector and the data-signal of the SRAM input
End coupling；The multichannel multiphase selector, further includes: clock multichannel polyphase circuit；
The clock multichannel polyphase circuit, including input terminal and output end；The input terminal of the clock multichannel polyphase circuit with
The output end of the clock signal delay circuit couples, the output end of the clock multichannel polyphase circuit and the data of the SRAM
Signal input part coupling, suitable for exporting the clock signal in different paths and out of phase.
9. SRAM as claimed in claim 8 establishes retention time test circuit, which is characterized in that the clock multichannel multiphase electricity
Road, comprising:
The output end of second phase inverter, input terminal and the clock signal delay circuit couples, and output end and the second data select
The first input end of device couples；
The output end of second data selector, the second input terminal and the clock signal delay circuit couples, output end with
The clock signal input terminal of the SRAM couples, and enable signal input terminal inputs enable signal；Second data selector is suitable
According to different enable signals, a corresponding signal is selected from the input signal of two input terminals and is exported.
10. SRAM as described in any one of claims 1 to 9 establishes retention time test circuit, which is characterized in that the data
Signal delay circuit, comprising: d type flip flop and the first delay circuit, in which:
The d type flip flop, the end D input the data-signal, and clock signal input terminal inputs the clock signal, output end and institute
State the data signal input coupling of the first delay circuit；
The data signal input of first delay circuit, output end and the multichannel multiphase selector couples, and control terminal is suitable
In inputting the first delayed control signal.
11. SRAM as claimed in claim 10 establishes retention time test circuit, which is characterized in that the clock signal delay
Circuit, comprising: delay matching circuit and the second delay circuit, in which:
The delay matching circuit, clock signal input terminal input the clock signal, output end and second delay circuit
Clock signal input terminal coupling, suitable for by the rising of the rising edge of the clock signal and the output signal of the d type flip flop
Along synchronous；
The clock signal input terminal of second delay circuit, output end and the multichannel multiphase selector couples, and control terminal is suitable
In inputting the second delayed control signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810027540.7A CN110033819B (en) | 2018-01-11 | 2018-01-11 | SRAM establishment holding time test circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810027540.7A CN110033819B (en) | 2018-01-11 | 2018-01-11 | SRAM establishment holding time test circuit |
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| CN110033819A true CN110033819A (en) | 2019-07-19 |
| CN110033819B CN110033819B (en) | 2021-03-09 |
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| CN113589152A (en) * | 2020-04-30 | 2021-11-02 | 中芯国际集成电路制造(上海)有限公司 | Test circuit |
| WO2021238838A1 (en) * | 2020-05-29 | 2021-12-02 | 中兴通讯股份有限公司 | Method and circuit for measuring retention time of time sequence unit |
| WO2021238829A1 (en) * | 2020-05-29 | 2021-12-02 | 中兴通讯股份有限公司 | Timing unit establishing time measuring method and measuring circuit |
| CN113884865A (en) * | 2020-07-01 | 2022-01-04 | 复旦大学 | Test circuit and test method of D flip-flop |
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