CN105845179A - Measuring circuit and measuring method for data establishing time of storage - Google Patents
Measuring circuit and measuring method for data establishing time of storage Download PDFInfo
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- CN105845179A CN105845179A CN201610242235.0A CN201610242235A CN105845179A CN 105845179 A CN105845179 A CN 105845179A CN 201610242235 A CN201610242235 A CN 201610242235A CN 105845179 A CN105845179 A CN 105845179A
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- clock signal
- data
- memorizer
- clock
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
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- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The invention discloses a measuring circuit for data establishing time of storage. The measuring circuit comprises a first D trigger, wherein an output data is sent to a data input end of the storage under the control of the first clock signal; a data output end of the storage is connected with the data input end of a second D trigger and is used for outputting under the control of a third clock signal; a second clock signal is connected with a clock input end of the storage; the third clock signal is connected with the clock input end of the second D trigger; multistage buffers are serially connected into a buffer serial circuit which is used for outputting the first, second and third clock signals and adjusting deviation values among the first, second and third clock signals; the data establishing time of the storage can be acquired by gradually approaching the magnitude setting of the deviation values of the first, second and third clock signals. The invention also discloses a measuring circuit for the data establishing time of the storage. According to the method provided by the invention, the measuring precision can be increased.
Description
Technical field
The present invention relates to semiconductor integrated circuit field, particularly relate to the data setup time of a kind of memorizer
(Setup) measuring circuit；The invention still further relates to the measuring method of the data setup time of a kind of memorizer.
Background technology
As it is shown in figure 1, be the schematic diagram of the data setup time of memorizer；The data input pin of memorizer connects data
Input signal Data, input end of clock connects clock input signal CLK, at the rising edge of clock input signal CLK,
Memorizer outfan output data.The condition that memorizer to realize correctly exporting is data input signal Data
Must be maintained for stable, at clock before a data setup time of the rising edge of distance clock input signal CLK
In data setup time before the rising edge of input signal CLK, the signal of change will not be output.
Setup is time delay between two dotted lines in FIG, as shown in Figure 1, as shown in Figure 1, when data input letter
When number Data width more than the setup time before the rising edge of clock input signal CLK all keeps constant,
At this moment output signal is correct；And when data input signal Data is before the rising edge of clock input signal CLK
The Setup time width in when just changing, at this moment output signal is by incorrect.
The method of the Setup value of existing test memorizer is defeated by board additional data input signal Data and clock
Enter signal CLK, approach data input signal Data and clock input signal CLK rising edge to test Setup value.
Existing method of testing is by board, the impact of the factors such as probe card (probe card) and test line, precision
Not high enough.
Summary of the invention
The technical problem to be solved is to provide the measuring circuit of the data setup time of a kind of memorizer, can carry
High measuring accuracy.To this end, the present invention also provides for the measuring method of the data setup time of a kind of memorizer.
For solving above-mentioned technical problem, the measuring circuit of the data setup time of the memorizer that the present invention provides includes:
First d type flip flop, its data output end is connected to the data input pin of memorizer；Described first d type flip flop
Data input pin connects input data, and the input end of clock of described first d type flip flop connects the first clock signal.
Second d type flip flop, the data output end of described memorizer connects the data input pin of the second d type flip flop；Described
The data output end output data of the second d type flip flop.
Second clock signal is connected to the input end of clock of described memorizer.
3rd clock signal is connected to the input end of clock of described second d type flip flop.
Buffer series circuit, is formed by multi-stage buffer series connection, the previous stage buffering in described buffer series circuit
The outfan of device is connected to the input of rear stage buffer, prolonging of the buffers at different levels in described buffer series circuit
Shi Xiangtong.
Clock input signal is connected to the input of the first order buffer of described buffer series circuit, when described first
Clock signal, described second clock signal and described 3rd clock signal are by the corresponding progression of described buffer series circuit
Buffer exports, and the frequency of described first clock signal, described second clock signal and described 3rd clock signal joint is all
Equal to the frequency of described clock input signal, when described first clock signal, described second clock signal and the described 3rd
The deviant of the rising edge between clock signal is multiplied by the time delay of first-level buffer device corresponding to the progression difference between buffer.
Described input data are latched in described first d type flip flop, described at the rising edge of described first clock signal
During input data variation, the rising edge of described first clock signal is made to be ahead of the inclined of described second clock signal rising edge
Shifting value is the first deviant, and the rising edge of described second clock signal is ahead of the inclined of described 3rd rising edge clock signal
Shifting value is the second deviant, and described second deviant is set greater than the data setup time of described second d type flip flop,
The data setup time of described memorizer is obtained by regulating the size Step wise approximation of described first deviant, described first
When deviant is more than or equal to the data setup time of described memorizer, described output data are correct；Described first deviant
During less than the data setup time of described memorizer, described output data are incorrect.
Further improving and be, the buffers at different levels of described buffer series circuit include 3 outfans the most respectively, 3
Individual outfan is defeated respectively as described first clock signal, described second clock signal and described 3rd clock signal joint
Going out end, each outfan includes a switch, by the first clock signal described in described on-off control, described the
Two clock signals and the output of described 3rd clock signal joint.
Further improving is that described second clock signal is connected to described storage by a d type flip flop delay cell
The input end of clock of device.
Further improving is that described 3rd clock signal is connected to described second by a d type flip flop delay cell
The input end of clock of d type flip flop.
For solving above-mentioned technical problem, the measuring method of the data setup time of the memorizer that the present invention provides includes as follows
Step:
Step one, add described clock input signal to described buffer series circuit, from described buffer series circuit
Export described first clock signal, described second clock signal and described 3rd clock signal.
The data input pin of described first d type flip flop is input data into described in step 2, addition.
Step 3, being changed described input data, described second deviant is set greater than described 2nd D and triggers
The data setup time of device, obtains the data of described memorizer by regulating the size Step wise approximation of described first deviant
Setting up the time, when described first deviant is more than or equal to the data setup time of described memorizer, described output data are just
Really；When described first deviant is less than the data setup time of described memorizer, described output data are incorrect.
Further improving and be, the buffers at different levels of described buffer series circuit include 3 outfans the most respectively, 3
Individual outfan is defeated respectively as described first clock signal, described second clock signal and described 3rd clock signal joint
Going out end, each outfan includes a switch, by the first clock signal described in described on-off control, described the
Two clock signals and the output of described 3rd clock signal joint.
The present invention test circuit peripheral clock input signal and input data be not directly connected to memorizer time
Clock input and data input pin, but believed by the inside formed after clock input signal is changed with multiple buffers
Number realize the test of the data setup time to memorizer, therefore it is outside to eliminate board, probe card and test line etc.
The factor impact on test result, so the present invention can improve measuring accuracy.
Accompanying drawing explanation
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings:
Fig. 1 is the schematic diagram of the data setup time of memorizer；
Fig. 2 is the measuring circuit figure of the data setup time of memorizer.
Detailed description of the invention
As in figure 2 it is shown, be the measuring circuit figure of the data setup time of memorizer 2, embodiment of the present invention memorizer 2
The measuring circuit of data setup time include:
First d type flip flop 1, its data output end i.e. D end is connected to the data input pin i.e. A end of memorizer 2, the
One d type flip flop 1 represents with DFF1 in fig. 2, and memorizer Mem represents；The number of described first d type flip flop 1
Connecting input data A according to input, the input end of clock i.e. CLK end of described first d type flip flop 1 connects the first clock
Signal CLKI.
Second d type flip flop 3, the second d type flip flop 3 represents with DFF2 in fig. 2, and the data of described memorizer 2 are defeated
Go out end i.e. Q end and connect the data input pin i.e. D end of the second d type flip flop 3；The data of described second d type flip flop 3 are defeated
Go out end i.e. Q end output data Q.
Second clock signal CLKM is connected to the input end of clock i.e. CLK end of described memorizer 2.Preferably, second
Clock signal clk M is connected to the input end of clock i.e. CLK of described memorizer 2 by a d type flip flop delay cell 4
End, d type flip flop delay cell represents with DFFD in fig. 2.
3rd clock signal clk O is connected to the input end of clock i.e. CLK end of described second d type flip flop 3.Preferably,
3rd clock signal clk O is connected to the clock of described second d type flip flop 3 by a d type flip flop delay cell 5
Input i.e. CLK end.
Buffer series circuit, is connected by multi-stage buffer 6 and is formed, and the previous stage in described buffer series circuit is delayed
The outfan rushing device 6 is connected to the input of rear stage buffer 6, the bufferings at different levels in described buffer series circuit
The time delay of device 6 is identical.
Clock input signal CLK is connected to the input of the first order buffer 6 of described buffer series circuit, described
First clock signal clk I, described second clock signal CLKM and described 3rd clock signal clk O are by described buffer
The buffer 6 of the corresponding progression of series circuit exports, described first clock signal clk I, described second clock signal
The frequency of CLKM and described 3rd clock signal clk O joint is equal to the frequency of described clock input signal CLK, described
First clock signal clk I, rising edge between described second clock signal CLKM and described 3rd clock signal clk O
Deviant i.e. phase contrast be multiplied by the time delay of first-level buffer device 6 corresponding to the progression difference between buffer 6.
Described input data A are latched into described first d type flip flop 1 at the rising edge of described first clock signal clk I
In, when described input data A change, make the rising edge of described first clock signal clk I be ahead of described second
The deviant of clock signal clk M rising edge is the first deviant, and the rising edge of described second clock signal CLKM is advanced
Deviant in described 3rd clock signal clk O rising edge is the second deviant, and described second deviant is set to greatly
In the data setup time of described second d type flip flop 3, obtain by regulating the size Step wise approximation of described first deviant
To the data setup time of described memorizer 2, described first deviant is set up more than or equal to the data of described memorizer 2
During the time, described output data are correct；When described first deviant is less than the data setup time of described memorizer 2,
Described output data are incorrect.
The buffers at different levels 6 of described buffer series circuit include that 3 outfans, 3 outfans are made respectively the most respectively
For described first clock signal clk I, described second clock signal CLKM and described 3rd clock signal clk O joint defeated
Go out end, each outfan include one switch 7, by described switch 7 control described first clock signal clk I,
Described second clock signal CLKM and the output of described 3rd clock signal clk O joint.
The measuring method of the data setup time of embodiment of the present invention memorizer comprises the steps:
Step one, add described clock input signal CLK to described buffer series circuit, connect from described buffer
Circuit output described first clock signal clk I, described second clock signal CLKM and described 3rd clock signal clk O.
Step 2, add the described input data A data input pin to described first d type flip flop 1.
Step 3, being changed described input data A, described second deviant is set greater than described 2nd D and touches
Send out the data setup time of device 3, obtain described memorizer 2 by regulating the size Step wise approximation of described first deviant
Data setup time, when described first deviant is more than or equal to the data setup time of described memorizer 2, described defeated
Go out data correct；When described first deviant is less than the data setup time of described memorizer 2, described output data are not
Correctly.
Understand as shown in Figure 2, the clock input signal CLK of embodiment of the present invention test circuit peripheral and input data
A is not directly connected to input end of clock and the data input pin of memorizer 2, but by by clock input signal CLK
The internal signal formed after changing with multiple buffers 6 realizes the test of the data setup time to memorizer 2, i.e.
The output signal of clock signal clk I, CLKM and CLKO and the first d type flip flop 1 is all internal signal, can eliminate
The external factor impacts on test result such as board, probe card and test line, so the embodiment of the present invention can improve survey
Examination precision.
Above by specific embodiment, the present invention is described in detail, but these have not constituted the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art it may also be made that many deformation and improves, this
Also should be regarded as protection scope of the present invention a bit.
Claims (6)
1. the measuring circuit of the data setup time of a memorizer, it is characterised in that including:
First d type flip flop, its data output end is connected to the data input pin of memorizer；Described first d type flip flop
Data input pin connects input data, and the input end of clock of described first d type flip flop connects the first clock signal；
Second d type flip flop, the data output end of described memorizer connects the data input pin of the second d type flip flop；Described
The data output end output data of the second d type flip flop；
Second clock signal is connected to the input end of clock of described memorizer；
3rd clock signal is connected to the input end of clock of described second d type flip flop；
Buffer series circuit, is formed by multi-stage buffer series connection, the previous stage buffering in described buffer series circuit
The outfan of device is connected to the input of rear stage buffer, prolonging of the buffers at different levels in described buffer series circuit
Shi Xiangtong；
Clock input signal is connected to the input of the first order buffer of described buffer series circuit, when described first
Clock signal, described second clock signal and described 3rd clock signal are by the corresponding progression of described buffer series circuit
Buffer exports, and the frequency of described first clock signal, described second clock signal and described 3rd clock signal joint is all
Equal to the frequency of described clock input signal, when described first clock signal, described second clock signal and the described 3rd
The deviant of the rising edge between clock signal is multiplied by the time delay of first-level buffer device corresponding to the progression difference between buffer；
Described input data are latched in described first d type flip flop, described at the rising edge of described first clock signal
During input data variation, the rising edge of described first clock signal is made to be ahead of the inclined of described second clock signal rising edge
Shifting value is the first deviant, and the rising edge of described second clock signal is ahead of the inclined of described 3rd rising edge clock signal
Shifting value is the second deviant, and described second deviant is set greater than the data setup time of described second d type flip flop,
The data setup time of described memorizer is obtained by regulating the size Step wise approximation of described first deviant, described first
When deviant is more than or equal to the data setup time of described memorizer, described output data are correct；Described first deviant
During less than the data setup time of described memorizer, described output data are incorrect.
2. the measuring circuit of the data setup time of memorizer as claimed in claim 1, it is characterised in that: described
The buffers at different levels of buffer series circuit include 3 outfans the most respectively, and 3 outfans are respectively as described first
Clock signal, described second clock signal and the outfan of described 3rd clock signal joint, each outfan includes
One switch, by the first clock signal, described second clock signal and described 3rd clock described in described on-off control
The output of signal joint.
3. the measuring circuit of the data setup time of memorizer as claimed in claim 1, it is characterised in that: described
Second clock signal is connected to the input end of clock of described memorizer by a d type flip flop delay cell.
4. the measuring circuit of the data setup time of memorizer as claimed in claim 1, it is characterised in that: described
3rd clock signal is connected to the input end of clock of described second d type flip flop by a d type flip flop delay cell.
5. use the method that the measuring circuit of the data setup time of memorizer as claimed in claim 1 measures,
It is characterized in that, comprise the steps:
Step one, add described clock input signal to described buffer series circuit, from described buffer series circuit
Export described first clock signal, described second clock signal and described 3rd clock signal；
The data input pin of described first d type flip flop is input data into described in step 2, addition；
Step 3, being changed described input data, described second deviant is set greater than described 2nd D and triggers
The data setup time of device, obtains the data of described memorizer by regulating the size Step wise approximation of described first deviant
Setting up the time, when described first deviant is more than or equal to the data setup time of described memorizer, described output data are just
Really；When described first deviant is less than the data setup time of described memorizer, described output data are incorrect.
6. method as claimed in claim 5, it is characterised in that: the buffers at different levels of described buffer series circuit
Including 3 outfans the most respectively, 3 outfans are respectively as described first clock signal, described second clock signal
With the outfan of described 3rd clock signal joint, each outfan includes a switch, by described on-off control
Described first clock signal, described second clock signal and the output of described 3rd clock signal joint.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610242235.0A CN105845179B (en) | 2016-04-19 | 2016-04-19 | The measuring circuit and measurement method of the data setup time of memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610242235.0A CN105845179B (en) | 2016-04-19 | 2016-04-19 | The measuring circuit and measurement method of the data setup time of memory |
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| CN105845179B CN105845179B (en) | 2019-10-11 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107068192A (en) * | 2017-03-31 | 2017-08-18 | 上海华虹宏力半导体制造有限公司 | Local clock pulses generation circuit for the time-ordered measurement of memory |
| CN109300500A (en) * | 2017-07-25 | 2019-02-01 | 旺宏电子股份有限公司 | The data managing method and system of memory device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101131864A (en) * | 2006-08-22 | 2008-02-27 | 奇梦达北美公司 | Method and circuit for transmitting a memory clock signal |
| US20090323447A1 (en) * | 2008-06-27 | 2009-12-31 | Hynix Semiconductor Inc. | Apparatus for measuring data setup/hold time |
-
2016
- 2016-04-19 CN CN201610242235.0A patent/CN105845179B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101131864A (en) * | 2006-08-22 | 2008-02-27 | 奇梦达北美公司 | Method and circuit for transmitting a memory clock signal |
| US20090323447A1 (en) * | 2008-06-27 | 2009-12-31 | Hynix Semiconductor Inc. | Apparatus for measuring data setup/hold time |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107068192A (en) * | 2017-03-31 | 2017-08-18 | 上海华虹宏力半导体制造有限公司 | Local clock pulses generation circuit for the time-ordered measurement of memory |
| CN109300500A (en) * | 2017-07-25 | 2019-02-01 | 旺宏电子股份有限公司 | The data managing method and system of memory device |
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| Publication number | Publication date |
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| CN105845179B (en) | 2019-10-11 |
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