CN105845179B - The measuring circuit and measurement method of the data setup time of memory - Google Patents
The measuring circuit and measurement method of the data setup time of memory Download PDFInfo
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- CN105845179B CN105845179B CN201610242235.0A CN201610242235A CN105845179B CN 105845179 B CN105845179 B CN 105845179B CN 201610242235 A CN201610242235 A CN 201610242235A CN 105845179 B CN105845179 B CN 105845179B
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- clock signal
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
Abstract
The invention discloses a kind of measuring circuits of the data setup time of memory, comprising: the first d type flip flop passes through the data input pin of the first clock signal control output data to memory；The data output end of memory connects the data input pin of the second d type flip flop and exports under the control of third clock signal；Second clock is signally attached to the input end of clock of memory；Third clock signal is connected to the input end of clock of the second d type flip flop；It is connected by multi-stage buffer and forms the deviant on above-mentioned edge that buffer series circuit exports the first to three clock signal and is adjustable between the first to three clock signal；Step wise approximation is set by the size of the deviant to the first to three clock signal and obtains the data setup time of memory.The invention also discloses a kind of measurement methods of the data setup time of memory.The present invention can improve measuring accuracy.
Description
Technical field
The present invention relates to semiconductor integrated circuit fields, more particularly to a kind of data setup time of memory
(Setup) measuring circuit；The invention further relates to a kind of measurement methods of the data setup time of memory.
Background technique
As shown in Figure 1, being the schematic diagram of the data setup time of memory；The data input pin connection data of memory are defeated
Entering signal Data, input end of clock connects clock input signal CLK, in the rising edge of clock input signal CLK, memory
Output end output data.Memory will realize that the condition correctly exported is that data input signal Data must be apart from clock
It is maintained for stablizing before one data setup time of the rising edge of input signal CLK, in the rising edge of clock input signal CLK
The signal changed in data setup time before will not be exported.
It in Setup in Fig. 1 is delayed between two dotted lines, as shown in Figure 1, as shown in Figure 1, as data input signal Data
When being more than that the width of setup time all remains unchanged before the rising edge of clock input signal CLK, at this moment output signal is
Correctly；And when data input signal Data in the width of the Setup time before the rising edge of clock input signal CLK just
When variation, at this moment output signal will be incorrect.
The method of the Setup value of existing test memory is inputted by the additional data input signal Data of board and clock
Signal CLK approaches data input signal Data and clock input signal CLK rising edge to test Setup value.
For existing test method by board, probe card (probe card) and the influence for testing the factors such as line, precision is inadequate
It is high.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of measuring circuits of the data setup time of memory, can mention
High measuring accuracy.For this purpose, the present invention also provides a kind of measurement methods of the data setup time of memory.
In order to solve the above technical problems, the measuring circuit of the data setup time of memory provided by the invention includes:
First d type flip flop, data output end are connected to the data input pin of memory；The number of first d type flip flop
Input data is connected according to input terminal, the input end of clock of first d type flip flop connects the first clock signal.
Second d type flip flop, the data output end of the memory connect the data input pin of the second d type flip flop；Described
The data output end output data of 2-D trigger.
Second clock signal is connected to the input end of clock of the memory.
Third clock signal is connected to the input end of clock of second d type flip flop.
Buffer series circuit, is connected by multi-stage buffer and is formed, the previous stage buffering in the buffer series circuit
The output end of device is connected to the input terminal of rear stage buffer, the delay phase of the buffers at different levels in the buffer series circuit
Together.
Clock input signal is connected to the input terminal of the first order buffer of the buffer series circuit, when described first
Clock signal, the second clock signal and the third clock signal by the buffer series circuit correspondence series buffering
Device output, the frequency of first clock signal, the second clock signal and the third clock signal section are equal to described
The frequency of clock input signal, between first clock signal, the second clock signal and the third clock signal
The deviant of rising edge corresponds to the series difference between buffer multiplied by the delay of first-level buffer device.
The input data is latched into first d type flip flop in the rising edge of first clock signal, described
When input data changes, the rising edge of first clock signal is enabled to be ahead of the deviant of the second clock signal rising edge
For the first deviant, the deviant that the rising edge of the second clock signal is ahead of the third rising edge clock signal is the
Two deviants, second deviant are set greater than the data setup time of second d type flip flop, by adjusting described the
The size Step wise approximation of one deviant obtains the data setup time of the memory, and first deviant is more than or equal to described
When the data setup time of memory, the output data is correct；The data that first deviant is less than the memory are built
When between immediately, the output data is incorrect.
A further improvement is that the buffers at different levels of the buffer series circuit all respectively include 3 output ends, 3
Output end respectively as first clock signal, the output end of the second clock signal and the third clock signal section,
Each output end includes a switch, passes through the first clock signal described in the switch control, the second clock signal
With the output of the third clock signal section.
A further improvement is that the second clock signal is connected to the storage by a d type flip flop delay cell
The input end of clock of device.
A further improvement is that the third clock signal is connected to the 2nd D by a d type flip flop delay cell
The input end of clock of trigger.
In order to solve the above technical problems, the measurement method of the data setup time of memory provided by the invention includes as follows
Step:
Step 1: the clock input signal is added to the buffer series circuit, from the buffer series circuit
Export first clock signal, the second clock signal and the third clock signal.
Step 2: inputting data into the data input pin of first d type flip flop described in being added.
Step 3: being changed to the input data, second deviant is set greater than second d type flip flop
Data setup time, when the data that the size Step wise approximation by adjusting first deviant obtains the memory are established
Between, when first deviant is more than or equal to the data setup time of the memory, the output data is correct；Described first
When deviant is less than the data setup time of the memory, the output data is incorrect.
A further improvement is that the buffers at different levels of the buffer series circuit all respectively include 3 output ends, 3
Output end respectively as first clock signal, the output end of the second clock signal and the third clock signal section,
Each output end includes a switch, passes through the first clock signal described in the switch control, the second clock signal
With the output of the third clock signal section.
The present invention test clock input signal and input data external in circuit be not directly connected to memory when
Clock input terminal and data input pin, but by will clock input signal converted with multiple buffers after the internal signal that is formed come
It realizes the test to the data setup time of memory, therefore the external factor such as board, probe card and test line can be eliminated to survey
The influence of test result, so the present invention can improve measuring accuracy.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the schematic diagram of the data setup time of memory；
Fig. 2 is the measuring circuit figure of the data setup time of memory.
Specific embodiment
As shown in Fig. 2, being the measuring circuit figure of the data setup time of memory 2, the number of memory of the embodiment of the present invention 2
Include: according to the measuring circuit of settling time
First d type flip flop 1, data output end, that is, end D are connected to the data input pin i.e. end A of memory 2, the first D touching
Hair device 1 indicates that memory is indicated with Mem in Fig. 2 with DFF1；The data input pin connection input number of first d type flip flop 1
According to A, input end of clock, that is, end CLK of first d type flip flop 1 connects the first clock signal clk I.
Second d type flip flop 3, the second d type flip flop 3 indicate in Fig. 2 with DFF2, data output end, that is, Q of the memory 2
Data input pin, that is, end D of the second d type flip flop 3 of end connection；The data output end of the second d type flip flop 3, that is, end Q output data
Q。
Second clock signal CLKM is connected to the input end of clock i.e. end CLK of the memory 2.Preferably, second clock
Signal CLKM is connected to the input end of clock i.e. end CLK of the memory 2, d type flip flop by a d type flip flop delay cell 4
Delay cell is indicated in Fig. 2 with DFFD.
Third clock signal clk O is connected to the input end of clock i.e. end CLK of second d type flip flop 3.Preferably, third
Clock signal clk O is connected to the input end of clock i.e. CLK of second d type flip flop 3 by a d type flip flop delay cell 5
End.
Buffer series circuit is formed by the series connection of multi-stage buffer 6, the previous stage buffering in the buffer series circuit
The output end of device 6 is connected to the input terminal of rear stage buffer 6, and the buffers at different levels 6 in the buffer series circuit prolong
Shi Xiangtong.
Clock input signal CLK is connected to the input terminal of the first order buffer 6 of the buffer series circuit, and described
One clock signal CLKI, the second clock signal CLKM and the third clock signal clk O are by the buffer series circuit
The buffer 6 of correspondence series export, when the first clock signal clk I, the second clock signal CLKM and the third
The frequency of clock signal CLKO section is equal to the frequency of the clock input signal CLK, the first clock signal clk I, described the
Deviant, that is, phase difference of rising edge between two clock signal clk M and the third clock signal clk O corresponds to buffer 6
Between series difference multiplied by first-level buffer device 6 delay.
Rising edge of the input data A in the first clock signal clk I is latched into first d type flip flop 1,
In input data A variation, the rising edge of the first clock signal clk I is enabled to be ahead of the second clock signal
The deviant of CLKM rising edge is the first deviant, and the rising edge of the second clock signal CLKM is ahead of the third clock
The deviant of signal CLKO rising edge is the second deviant, and second deviant is set greater than second d type flip flop 3
Data setup time, when the data that the size Step wise approximation by adjusting first deviant obtains the memory 2 are established
Between, when first deviant is more than or equal to the data setup time of the memory 2, the output data is correct；Described
When one deviant is less than the data setup time of the memory 2, the output data is incorrect.
The buffers at different levels 6 of the buffer series circuit all respectively include 3 output ends, 3 output ends respectively as
The output end of the first clock signal clk I, the second clock signal CLKM and third clock signal clk O section, often
One output end all includes a switch 7, controls the first clock signal clk I, the second clock by the switch 7
The output of signal CLKM and third clock signal clk O section.
The measurement method of the data setup time of memory of the embodiment of the present invention includes the following steps:
Step 1: the clock input signal CLK is added to the buffer series circuit, from the buffer series electrical
Road exports the first clock signal clk I, the second clock signal CLKM and the third clock signal clk O.
Step 2: be added the input data A to first d type flip flop 1 data input pin.
Step 3: being changed to the input data A, second deviant is set greater than the 2nd D triggering
The data setup time of device 3, the data that the size Step wise approximation by adjusting first deviant obtains the memory 2 are built
Between immediately, when first deviant is more than or equal to the data setup time of the memory 2, the output data is correct；Institute
When stating data setup time of first deviant less than the memory 2, the output data is incorrect.
As shown in Figure 2 it is found that clock input signal CLK and input data A external in test circuit of the embodiment of the present invention
Be not directly connected to the input end of clock and data input pin of memory 2, but by by clock input signal CLK with multiple
The internal signal that is formed realizes the test of the data setup time to memory 2, i.e. clock signal after buffer 6 is converted
The output signal of CLKI, CLKM and CLKO and the first d type flip flop 1 is all internal signal, can eliminate board, probe card and test
Influence of the external factor such as line to test result, so the embodiment of the present invention can improve measuring accuracy.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (6)
1. a kind of measuring circuit of the data setup time of memory characterized by comprising
First d type flip flop, data output end are connected to the data input pin of memory；The data of first d type flip flop are defeated
Enter end connection input data, the input end of clock of first d type flip flop connects the first clock signal；
Second d type flip flop, the data output end of the memory connect the data input pin of the second d type flip flop；The 2nd D touching
Send out the data output end output data of device；
Second clock is signally attached to the input end of clock of the memory；
Third clock signal is connected to the input end of clock of second d type flip flop；
Buffer series circuit, is connected by multi-stage buffer and is formed, the previous stage buffer in the buffer series circuit
Output end is connected to the input terminal of rear stage buffer, and the delay of the buffers at different levels in the buffer series circuit is identical；
Clock input signal is connected to the input terminal of the first order buffer of the buffer series circuit, the first clock letter
Number, the second clock signal and the third clock signal it is defeated by the buffer of the correspondence series of the buffer series circuit
Out, it is defeated to be equal to the clock for the frequency of first clock signal, the second clock signal and the third clock signal
Enter the frequency of signal, the rising edge between first clock signal, the second clock signal and the third clock signal
Deviant correspond to buffer between series difference multiplied by first-level buffer device delay；
The input data is latched into first d type flip flop in the rising edge of first clock signal, in the input
When data variation, enabling the rising edge of first clock signal be ahead of the deviant of the second clock signal rising edge is the
One deviant, the deviant that the rising edge of the second clock signal is ahead of the third rising edge clock signal is second inclined
Shifting value, second deviant are set greater than the data setup time of second d type flip flop, by adjusting described first partially
The size Step wise approximation of shifting value obtains the data setup time of the memory, and first deviant is more than or equal to the storage
When the data setup time of device, the output data is correct；When the data that first deviant is less than the memory are established
Between when, the output data is incorrect.
2. the measuring circuit of the data setup time of memory as described in claim 1, it is characterised in that: the buffer string
The buffers at different levels of connection circuit all respectively include 3 output ends, and 3 output ends are respectively as first clock signal, described
The output end of second clock signal and the third clock signal, each output end include a switch, are opened by described
Close the output for controlling first clock signal, the second clock signal and the third clock signal.
3. the measuring circuit of the data setup time of memory as described in claim 1, it is characterised in that: the second clock
Signal is connected to the input end of clock of the memory by a d type flip flop delay cell.
4. the measuring circuit of the data setup time of memory as described in claim 1, it is characterised in that: the third clock
Signal is connected to the input end of clock of second d type flip flop by a d type flip flop delay cell.
5. the method measured using the measuring circuit of the data setup time of memory as described in claim 1, special
Sign is, includes the following steps:
Step 1: the clock input signal is added to the buffer series circuit, exported from the buffer series circuit
First clock signal, the second clock signal and the third clock signal；
Step 2: inputting data into the data input pin of first d type flip flop described in being added；
Step 3: being changed to the input data, second deviant is set greater than the number of second d type flip flop
According to settling time, the size Step wise approximation by adjusting first deviant obtains the data setup time of the memory,
When first deviant is more than or equal to the data setup time of the memory, the output data is correct；Described first partially
When shifting value is less than the data setup time of the memory, the output data is incorrect.
6. method as claimed in claim 5, it is characterised in that: the buffers at different levels of the buffer series circuit all wrap respectively
3 output ends are included, 3 output ends are respectively as first clock signal, the second clock signal and the third clock
The output end of signal, each output end includes a switch, by the first clock signal described in the switch control, described
The output of second clock signal and the third clock signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610242235.0A CN105845179B (en) | 2016-04-19 | 2016-04-19 | The measuring circuit and measurement method of the data setup time of memory |
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| CN201610242235.0A CN105845179B (en) | 2016-04-19 | 2016-04-19 | The measuring circuit and measurement method of the data setup time of memory |
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| CN105845179B true CN105845179B (en) | 2019-10-11 |
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| CN107068192B (en) * | 2017-03-31 | 2020-02-07 | 上海华虹宏力半导体制造有限公司 | Local clock signal generation circuit for timing measurement of memory |
| CN109300500B (en) * | 2017-07-25 | 2020-06-16 | 旺宏电子股份有限公司 | Data management method and system for memory device |
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| US7886122B2 (en) * | 2006-08-22 | 2011-02-08 | Qimonda North America Corp. | Method and circuit for transmitting a memory clock signal |
| KR100950483B1 (en) * | 2008-06-27 | 2010-03-31 | 주식회사 하이닉스반도체 | Data setup/hold time measurement device |
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