CN206993091U - A kind of clock data recovery device - Google Patents
A kind of clock data recovery device Download PDFInfo
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- CN206993091U CN206993091U CN201720937563.2U CN201720937563U CN206993091U CN 206993091 U CN206993091 U CN 206993091U CN 201720937563 U CN201720937563 U CN 201720937563U CN 206993091 U CN206993091 U CN 206993091U
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Abstract
A kind of clock data recovery device, the clock data recovery device include：Clock generating device, for receiving the input data for including clock information, clock signal is produced based on the input data；Delay adjusting apparatus, input data is postponed for relation of the clock in the samples edges and input data according to one of clock signal between so that the samples edges of one of described clock signal are fallen into the range of the clock sampling of input data；And sampling apparatus, for carrying out data recovery to the input data after delay according to the clock signal, obtain output data.Input data is postponed by relation of the clock in the samples edges and input data according to one of clock signal between, realizes the adaptive adjustment to data delay, the sampling degree of accuracy is improved, has saved cost.
Description
Technical field
A kind of this disclosure relates to technical field of integrated circuits, and in particular to clock data recovery device.
Background technology
In integrated circuit (IC) technical field, IC technical fields are particularly driven, clock and data recovery is important one
Point.Generally, clock and data recovery using clock generator from the extracting data clock signal containing clock information, and root
Data recovery is carried out to data according to clock signal.But clock by clock generator when can produce delay, in order to ensure when
The correct sampling of clock data signal is, it is necessary to carry out delay compensation.Conventional method uses (OTP, One Time
Programmable) One Time Programmable mode, by manually adjusting delay size with clock phase relation by observing data.
But traditional OTP circuit areas are larger, it is necessary to debug repeatedly to determine optimal value, increase testing time and design cost.
The content of the invention
In view of this, present disclose provides a kind of clock data recovery device, including：Clock generating device, for receiving
Input data comprising clock information, clock signal is produced based on the input data；Delay adjusting apparatus, filled with clock
Put and be connected with sampling apparatus, for relation of the clock in the samples edges and input data according to one of clock signal between
To postpone to input data so that the samples edges of one of described clock signal fall into the clock sampling scope of input data
It is interior；Sampling apparatus, be connected with clock generating device and delay adjusting apparatus, for according to the clock signal to defeated after delay
Enter data and carry out data recovery, obtain output data.
Preferably, the delay adjusting apparatus includes：Data delay module, is connected with sampling apparatus, for inputting number
According to the different delay of progress to produce the input data after multiple delays, and the multiple prolong is selected under control of the control signal
One of input data to lag is supplied to sampling apparatus；Control module is selected, with clock generating device and data Postponement module phase
Even, for the clock in the input data after the samples edges according to one of the clock signal and the multiple delay between
Relation produce control signal.
Preferably, the data delay module includes：Multiple data delay devices, it is respectively used to carry out difference to input data
Delay to produce the input data after multiple delays；Selector, with selection control module, sampling apparatus and the multiple data
Delayer is connected, for selecting one of input data after the multiple delay to be supplied to sampling cartridge under control of the control signal
Put.
Preferably, the selection control module includes：Clock delay device, is connected with clock generating device, for clock
Clock in signal with input data is postponed along adjacent clock signal, with the clock signal after being postponed；Triggering is single
Member, be connected with the clock delay device, for respectively according to the samples edges of the clock signal after the delay with it is the multiple
The relation of the clock of input data after delay between provides multiple trigger signals；Logic judgment unit, it is and the multiple
Trigger element is connected, for producing control signal according to the multiple trigger signal.
Preferably, the multiple data delay device includes the first data delay device, the second data delay device ..., Nth data
Delayer, it is respectively used to input data postponing delay1, delay1+ Δs T, delay1+2 Δ T, delay1+3 Δ T ...,
Delay1+ (N-1) Δ T, wherein N are the integer more than 1, and delay1 represented for the first default delay period, and Δ T represents unit delay
Time；And the trigger element includes：N-2 unit delay device, it is respectively used to input data by delay1 is delayed again
Postpone Δ T, 2 Δ T ..., (N-2) Δ T；First trigger, the second trigger ..., N-1 triggers, wherein the first trigger
First input end be connected to the output end of the first data delay device, second to N-1 triggers first input end connects respectively
The output end of N-2 unit delay device is connected to, first to N-1 triggers the second output end is all connected to clock delay device
Output end, and first to N-1 triggers output end provide respectively the first trigger signal, the second trigger signal ... N-1
Trigger signal.
Preferably, the multiple data delay device includes the first data delay device, the second data delay device ..., Nth data
Delayer, it is respectively used to input data postponing delay1, delay1+ Δs T, delay1+2 Δ T, delay1+3 Δ T ...,
Delay1+ (N-1) Δ T, wherein N are the integer more than 1, and delay1 represented for the first default delay period, and Δ T represents unit delay
Time；And the trigger element includes the first trigger, the second trigger ..., N-1 triggers, first to N-1 triggers
First input end be connected respectively to first to N-1 data delay devices output end, first to N-1 triggers second input
End is connected to the output end of clock delay device, and first to N-1 triggers output end provides the first trigger signal, second touched respectively
Signalling ... N-1 trigger signals.
Preferably, when the clock signal includes the first clock signal of phase, second clock signal ... n-th at equal intervals
Clock signal, wherein n are the integer more than 1；And the clock delay device is used for the (n-1)th clock signal delay Td, wherein Td
Represented for the second default delay period.
The disclosure by relation between of clock in the samples edges and input data according to one of clock signal come
Input data is postponed, realizes the adaptive adjustment to data delay, the sampling degree of accuracy is improved, has saved cost.
Brief description of the drawings
In order to illustrate more clearly of the technical scheme of the embodiment of the present disclosure, simple be situated between will be made to the accompanying drawing of embodiment below
Continue, it should be apparent that, the accompanying drawing in description below only relates to some embodiments of the present disclosure, rather than the limitation to the disclosure.
Fig. 1 shows the schematic block diagram of the clock data recovery device according to the embodiment of the present disclosure.
Fig. 2 shows the block diagram of the delay adjusting apparatus according to the embodiment of the present disclosure.
Fig. 3 shows the block diagram of the data delay module according to the embodiment of the present disclosure.
Fig. 4 A show the block diagram of the selection control module according to the embodiment of the disclosure one.
Fig. 4 B show the block diagram of the selection control module according to another embodiment of the disclosure
Fig. 5 A, 5B and 5C show the signal timing diagram in the delayed selection culture of input data.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present disclosure clearer, below in conjunction with the embodiment of the present disclosure
Accompanying drawing, clear, complete description is carried out to the technical scheme of the embodiment of the present disclosure.Obviously described embodiment is the disclosure
Part of the embodiment, rather than whole embodiment.Based on described embodiment of the disclosure, ordinary skill people
The every other embodiment that member is obtained on the premise of without creative work, belong to the scope of disclosure protection.
Present disclose provides a kind of clock data recovery device, passes through the samples edges according to one of clock signal and input
The relation of clock in data between postpones to input data so that the samples edges of one of described clock signal fall
Enter in the range of the clock sampling of input data.Compared with conventional method, the clock data recovery device of the embodiment of the present disclosure need not
It is manually operated that the adaptive adjustment to data delay can be achieved, the sampling degree of accuracy is improved, has saved cost.
Fig. 1 shows the schematic block diagram of the clock data recovery device according to the embodiment of the present disclosure.
As shown in figure 1, clock data recovery device includes clock generating device 1, delay adjusting apparatus 2 and sampling apparatus 3.
Clock generating device 1 is used to receive the input data data for including clock information, based on the input data data
Clock signal clk_1, clk_2 are produced ..., clk_n.
Delay adjusting apparatus 2 is used in samples edges and input data data according to one of clock signal clk_n-1
Relation of the clock between is postponed to input data data with the input data data_d after being postponed so that described
One of clock signal clk_n-1 samples edges are fallen into the range of the clock sampling of the input data data_d after delay.
Sampling apparatus 3 is based on clock signal clk_1, the clk_2 ..., clk_n is to the input data data_d after delay
Data recovery is carried out, obtains output data output.
Fig. 2 shows the block diagram of the delay adjusting apparatus 2 according to the embodiment of the present disclosure.As shown in Fig. 2 delay adjusting apparatus
2 can include data delay module 21 and selection control module 22.Data delay module 21 is used to carry out input data data
Different delays is to produce the input data after multiple delays, and after selecting the multiple delay under control of the control signal
One of input data is supplied to sampling apparatus as output data_d.Select control module 22 be used for according to the clock signal it
Relation of the clock between in input data after one clk_n-1 samples edges and the multiple delay is believed to produce control
Number.
Fig. 3 shows the block diagram of the data delay module 21 according to the embodiment of the present disclosure.As shown in figure 3, data delay mould
Block 21 can include multiple data delay devices and selector 211.Data delay device is respectively used to carry out not input data data
With delay to produce the input data after multiple delays.In the present embodiment, the number of data delay device can be 4, point
Not Wei data delay device D1, D2, D3 and D4 (hereinafter referred delayer D), wherein data delay device D1 be used for data data is prolonged
Slow delay1 obtains delayed data data_d1, and data delay device D2 is used to be postponed data data delays delay1+ Δs T
Data data_d2, data delay device D3 are used to data data delays delay1+2 Δs T obtaining delayed data data_d3, data
Delayer D4 is used to data data delays delay1+3 Δs T obtaining delayed data data_d4.Wherein delay1 represents that first is silent
Recognize time delay, Δ T represents unit delay time.Selector 211 is the multiple for being selected under control signal ctl control
One of input data data_d1, data_d2, data_d3 and data_d4 after delay are supplied to sampling as output data_d
Device 3.In the present embodiment, initial default path is most short delay delay1 path, and this is true under different simulated conditions
Fixed minimum value.But embodiment of the disclosure not limited to this, other paths can be selected as needed as initial path.
Fig. 4 A and 4B respectively illustrates the block diagram of the selection control module 22 according to disclosure difference embodiment.
As shown in Figure 4 A, selection control module 22 can include clock delay device 221, trigger element 222 and logic judgment
Unit 223.
Clock delay device 221 is used for clock signal clk_1, clk_2 ..., in clk_n with input data data clock
Postponed along adjacent clock signal clk_n-1, with the clock signal clk_n-1_d after being postponed.In the present embodiment,
Clock signal clk_n-1 can be postponed default time Td by clock delay device 221.Td's is added to ensure enough letters
Number settling time (setup time) or retention time (hold time), so that clock signal clk_n-1 can be obtained
One ideal sampling location.Td size can carry out compromise selection according to different application conditions, and it can be warp
Value is tested, can also be by being obtained by emulation, calculating or other modes.
Trigger element 222 be used for respectively according to the samples edges of the clock signal clk_n-1_d after the delay with it is described
The relation of the clock of input data after multiple delays between provides multiple trigger signal a1, a2 and a3.In the present embodiment
In, as shown in Figure 4 A, in the case where data delay module 21 is using structure shown in Fig. 3, trigger element 222 can include unit
Delayer T1 and T2 and trigger dff1, dff2 and dff3.Unit delay device T1 is used for the data delay Δ T of input, single
Position delayer T1 is used for the Δ T of data delay 2 of input.Trigger dff1 first input end and the second input receive respectively
The delayed data data_d1 and clock signal clk_n-1_d after delay, to provide trigger signal a1 in output end；Delayed data
Data_d1 is supplied to trigger dff2 first input end after unit delay device T1 delays Δ T, and the of trigger dff2
Two inputs receive the clock signal clk_n-1_d after delay, to provide trigger signal a2 in output end；Delayed data data_
D1 passes through unit delay device T2 and postpones the first input end that 2 Δ T are supplied to trigger dff3 afterwards, and the second of trigger dff3 is defeated
Enter end and receive the clock signal clk_n-1_d after delay, to provide trigger signal a3 in output end.But those skilled in the art
It should be clear that embodiment of the disclosure not limited to this, trigger element 222 can obtain the defeated of different delays using various other modes
Enter data.Such as in Fig. 4 B embodiment, it may not be necessary to unit delay device T1 and T2, but by the data delay in Fig. 3
Device D1, D2 and D3 output end are directly connected to trigger dff1, dff2 and dff3 first input end.
Logic judgment unit 223 is used to according to multiple trigger signal a1, a2 and a3 produce control signal ctl, so as to from
Desired one of selection provides as output data_d among delayed data data_d1, data_d2, data_d3 and data_d4
To sampling apparatus 3.
The selection of delayed data is described in detail below with reference to Fig. 5 A, 5B and 5C.
As shown in Figure 5A, clock signal clk_n-1 samples edges lag behind the clock in delayed data signal data_d1
Rising edge, delayed data signal data_d1 samplings are possible to mistake can be caused to sample using the clock signal.Such case
Under, the clock signal clk_n-1_d for delaying Td adopts delayed data signal data_d1 high level, trigger dff1 outputs
High level, and now trigger dff2 and dff3 output is low level, i.e. (a1, a2, a3) is 100, and triggering adjustment is patrolled
Volume so that using delay input data data_d1 delay △ T (that is, the second road delayed data data_d2 in Fig. 3) as true
Data-signal data_real export.As can be seen from Figure 5A, clock signal clk_n-1 is to real data-signal data_
Real sampled point falls in place so that when there is True Data signal data_real satisfactory signal to establish
Between and the retention time, so that it is guaranteed that sampling accuracy.
Similarly, in case of fig. 5b, clock signal clk_n-1 samples edges lag behind delayed data signal
Rising edge clock in data_d2, the clock signal clk_n-1_d for delaying Td adopt delayed data signal data_d2 height
Level.Now dff1 and dff2 the output high level of trigger, and trigger dff3 output low levels, i.e. (a1, a2, a3) is
110, generation control signal makes selector 211 to postpone 2 △ T of input data data_d1 delays (that is, the 3rd tunnel delays in Fig. 3
Data data_d3) it is used as real data-signal data_real to export.In the case of figure 5 c, clock signal clk_n-1
Samples edges lag behind rising edge clock in delayed data signal data_d3, trigger dff1, dff2 and dff3 are exported
High level, i.e. (a1, a2, a3) is 111, and generation control signal will postpone input data data_d1 and be delayed 3 △ T (that is, in Fig. 3
The 4th road delayed data data_d4) exported as real data-signal data_real.In addition, trigger dff1,
Dff2 and dff3 export it is low level in the case of, i.e. (a1, a2, a3) be 000 in the case of, it is believed that default delay
Delay1 is suitable, and generation control signal is using the first via delayed data data_d1 in Fig. 3 as real data-signal
Data_real is exported.Certainly, the mode of above logic judgment is only example, and those skilled in the art can be as needed
Select any other logic judgement mode.
Control signal can use various forms, such as four logical signal b<3:0>Form.Such as it can set as follows
Control signal：During (a1, a2, a3)=000, b<3:0>=0001；During (a1, a2, a3)=100, b<3:0>=0010；(a1,
A2, a3)=110 when, b<3:0>=0100；During (a1, a2, a3)=111, b<3:0>=1000.
Although figure 3 above, Fig. 4 A and Fig. 4 B the tunnels of embodiment Zhong Yi tetra- delay (four data delayer D1, D2, D3 and
D4, three triggers dff1, dff2 and dff3) exemplified by be described, but the it will be apparent to one skilled in the art that disclosure
Embodiment not limited to this, those skilled in the art can select any number of delay line as needed and adaptively change
Trigger logic.
In accordance with an embodiment of the present disclosure, the clock edge in the samples edges and input data according to one of clock signal is passed through
Between context input data is postponed, can be forward according to sampling clock or adaptively data be prolonged rearward
Shi Jinhang increases and decreases accordingly, ensures to complete correctly to sample when data arrive with this, data are with adopting under the conditions of eliminating different PVT
The delay of sample clock mismatches, and improves the sampling degree of accuracy, has saved cost.Moreover, the data delay line of embodiment of the disclosure
Road and decision logic can be selected arbitrarily as needed, possess higher flexibility when in use.
Preferred embodiment of the present disclosure is the foregoing is only, is not limited to the disclosure, for those skilled in the art
For, the disclosure can have various changes and change.All any modifications made within the spirit and principle of the disclosure, it is equal
Replace, improve etc., it should be included within the protection domain of the disclosure.
Claims (7)
- A kind of 1. clock data recovery device, it is characterised in that including：Clock generating device, for receiving the input data for including clock information, clock signal is produced based on the input data；Delay adjusting apparatus, it is connected with clock generating device and sampling apparatus, for the samples edges according to one of clock signal Input data is postponed with relation of the clock in input data between so that the sampling of one of described clock signal Edge is fallen into the range of the clock sampling of input data；AndSampling apparatus, it is connected with clock generating device and delay adjusting apparatus, after according to the clock signal to delay Input data carries out data recovery, obtains output data.
- 2. clock data recovery device according to claim 1, it is characterised in that the delay adjusting apparatus includes：Data delay module, is connected with sampling apparatus, after carrying out different delays to input data to produce multiple delays Input data, and select one of input data after the multiple delay to be supplied to sampling cartridge under control of the control signal Put；AndControl module is selected, is connected with clock generating device and data Postponement module, for according to one of the clock signal The relation of clock in input data after samples edges and the multiple delay between produces control signal.
- 3. clock data recovery device according to claim 2, it is characterised in that the data delay module includes：Multiple data delay devices, it is respectively used to carry out different delays to input data to produce the input number after multiple delays According to；AndSelector, it is connected with selection control module, sampling apparatus and the multiple data delay device, for the control in control signal One of input data after the multiple delay of the lower selection of system is supplied to sampling apparatus.
- 4. clock data recovery device according to claim 3, it is characterised in that the selection control module includes：Clock delay device, is connected with clock generating device, in clock signal with the clock of input data along it is adjacent when Clock signal is postponed, with the clock signal after being postponed；Trigger element, it is connected with the clock delay device, for respectively according to the samples edges of the clock signal after the delay Multiple trigger signals are provided the relation of the clock of the input data after the multiple delay between；AndLogic judgment unit, it is connected with the multiple trigger element, for producing control letter according to the multiple trigger signal Number.
- 5. clock data recovery device according to claim 4, it is characterised in thatThe multiple data delay device includes the first data delay device, the second data delay device ..., Nth data delayer, difference For input data to be postponed into delay1, delay1+ Δs T, delay1+2 Δ T, delay1+3 Δ T ..., delay1+ (N-1) Δ T, wherein N are the integer more than 1, and delay1 represented for the first default delay period, and Δ T represents unit delay time；AndThe trigger element includes：N-2 unit delay device, it is respectively used to the input data for delaying delay1 postponing Δ T, 2 Δ T ..., (N-2) Δ again T；First trigger, the second trigger ..., N-1 triggers, wherein the first input end of the first trigger is connected to first The output end of data delay device, second to N-1 triggers first input end are connected respectively to the defeated of N-2 unit delay device Go out end, first to N-1 triggers the second output end is all connected to the output end of clock delay device, and first to N-1 touches Hair device output end provide respectively the first trigger signal, the second trigger signal ... N-1 trigger signals.
- 6. clock data recovery device according to claim 4, it is characterised in thatThe multiple data delay device includes the first data delay device, the second data delay device ..., Nth data delayer, difference For input data to be postponed into delay1, delay1+ Δs T, delay1+2 Δ T, delay1+3 Δ T ..., delay1+ (N-1) Δ T, wherein N are the integer more than 1, and delay1 represented for the first default delay period, and Δ T represents unit delay time；AndThe trigger element includes the first trigger, the second trigger ..., N-1 triggers, and the of first to N-1 triggers One input be connected respectively to first to N-1 data delay devices output end, first to N-1 triggers the second input connects The output end of clock delay device is connected to, first to N-1 triggers output end provides the first trigger signal, the second triggering letter respectively Number ... N-1 trigger signals.
- 7. clock data recovery device according to claim 4, it is characterised in thatThe clock signal includes the first clock signal of phase, the clock signal of second clock signal ... n-th at equal intervals, wherein N is the integer more than 1；AndThe clock delay device is used to the (n-1)th clock signal delay Td, wherein Td representing for the second default delay period.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720937563.2U CN206993091U (en) | 2017-07-28 | 2017-07-28 | A kind of clock data recovery device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720937563.2U CN206993091U (en) | 2017-07-28 | 2017-07-28 | A kind of clock data recovery device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112148654A (en) * | 2019-06-27 | 2020-12-29 | 凌阳科技股份有限公司 | Method and circuit for adjusting clock edge of clock signal |
| CN113054995A (en) * | 2021-03-29 | 2021-06-29 | 南方电网数字电网研究院有限公司 | Clock data recovery method and device |
| CN113066413A (en) * | 2021-04-20 | 2021-07-02 | 合肥京东方显示技术有限公司 | Clock data recovery device and method |
-
2017
- 2017-07-28 CN CN201720937563.2U patent/CN206993091U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112148654A (en) * | 2019-06-27 | 2020-12-29 | 凌阳科技股份有限公司 | Method and circuit for adjusting clock edge of clock signal |
| CN113054995A (en) * | 2021-03-29 | 2021-06-29 | 南方电网数字电网研究院有限公司 | Clock data recovery method and device |
| CN113066413A (en) * | 2021-04-20 | 2021-07-02 | 合肥京东方显示技术有限公司 | Clock data recovery device and method |
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