CN213458042U - Analog processing circuit for metastable state in pre-simulation - Google Patents
Analog processing circuit for metastable state in pre-simulation Download PDFInfo
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- CN213458042U CN213458042U CN202023008118.9U CN202023008118U CN213458042U CN 213458042 U CN213458042 U CN 213458042U CN 202023008118 U CN202023008118 U CN 202023008118U CN 213458042 U CN213458042 U CN 213458042U
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Abstract
The utility model discloses a to metastable state analog processing circuit in preceding emulation, including clock A, first register R1, second register R2 and clock B, first register R1 is provided with first register signal input part, first register signal output part and first register clock end, and this preceding analog processing circuit still includes third register R3 and selector. The utility model discloses to the analogue processing circuit of metastability carry out analogue processing to the metastability in the emulation in the front for the chip circuit who designs out can tolerate the metastability.
Description
Technical Field
The utility model belongs to the chip design field, concretely relates to analog processing circuit to metastable state in preceding emulation.
Background
A CDC (clock domain crossing problem) signal refers to a signal passing from one clock domain to another asynchronous clock domain, the two clocks are either different in frequency or in phase, and when the effective edge of the transmit clock is too close to the effective edge of the receive clock, the transmit data changes within the setup/hold time of the receive clock edge, Metastability occurs, and the output of the sampling register will go into an unstable state. The metastable state not only can cause logic misjudgment, but also can cause the metastable state of the next stage (namely cause the propagation of the metastable state) by outputting the intermediate voltage value between 0 and 1, and the propagation of the metastable state enlarges the fault plane and is difficult to process.
The front simulation analog processing circuit is shown in figure 1 and comprises a clock A, a first register R1, a second register R2 and a clock B, wherein the first register R1 is provided with a first register signal input end, a first register signal output end and a first register clock end, the second register R2 is provided with a second register signal input end, a second register signal output end and a second register clock end, the clock B is provided with a clock B time control output end and a clock B signal input end, the clock A is provided with a clock A signal output end, the clock A signal output end is connected with the first register signal input end, the first register signal output end is connected with the second register signal input end, the clock B time control output end is respectively connected with the first register clock end and the second register clock end, the second register signal output end is connected with the clock B signal input end, the signal s from the clock a signal output terminal is input through the first register signal input terminal, the signal q1 from the first register signal output terminal is input through the second register signal input terminal, the clock B time control output terminal inputs the time control signals to the first register R1 and the second register R2 through the first register clock terminal and the second register clock terminal, respectively, and the signal q2 output from the second register signal output terminal is input from the clock B signal input terminal.
The pre-simulation (RTL simulation) of fig. 1 is a behavior simulation (functional simulation) that cannot detect the occurrence of the metastable state, and the designer does not know whether the asynchronous signal advances by one beat or lags by one beat when the asynchronous circuit design is implemented, so that there may be a potential risk of alignment between the control logic and the data logic.
SUMMERY OF THE UTILITY MODEL
In order to solve the above-mentioned defect, on the one hand, the utility model provides an in preceding emulation to the analog processing circuit of metastable state, this circuit carries out analog processing to the metastable state in the emulation in the front for the chip circuit that designs can tolerate the signal that the metastable state caused problem of clapping in advance or lags behind.
A metastable state analog processing circuit in pre-simulation comprises a clock A, a first register R1, a second register R2 and a clock B, wherein the first register R1 is provided with a first register signal input end, a first register signal output end and a first register clock end, the second register R2 is provided with a second register signal input end, a second register signal output end and a second register clock end, the clock B is provided with a clock B time control output end and a clock B signal input end, the clock A is provided with a clock A signal output end, the clock A signal output end is connected with the first register signal input end, the first register signal output end is connected with the second register signal input end, the clock B time control output end is respectively connected with the first register clock end and the second register clock end, the pre-simulation analog processing circuit further comprises a third register R3 and a selector, the third register R3 is provided with a third register signal input end, a third register signal output end and a third register clock end, the selector is provided with a selection end, a selector output end and a random value, the selection end is connected with the random value, the selection end comprises a first selection end, a second selection end and a third selection end, the first register signal output end is further connected with the first selection end, the clock B time control output end is further connected with the third register clock end, the second register signal output end is respectively connected with the third register signal input end and the second selection end, the third register signal output end is connected with the third selection end, and the selector output end is connected with the clock B signal input end.
Optionally, the selector is a MUX selector.
On the other hand, the utility model also provides a preceding emulation method of chip circuit tolerable metastable state.
A chip circuit can tolerate a pre-simulation method of a metastable state, and the method adopts the pre-simulation analog processing circuit.
The utility model discloses inventive principle and beneficial effect:
the utility model discloses the inventor discovers through long-term research, during the emulation of chip RTL, the metastable state can't be found to the EDA instrument, because data path/clock path (data channel/clock channel) do not accomplish the physics wire winding yet during RTL simulation, is not to have time delay information, and the EDA instrument can not carry out setup/hold inspection, and the EDA instrument can simulate according to following rule during preceding emulation:
1. the asynchronous signal changes before the rising edge of the clock, and the output changes just after the clock edge.
2. The asynchronous signal changes after the rising edge of the clock, then the output does not change.
The actual situation of the chip is as follows:
although the asynchronous cdc _ s signal varies before the rx _ clk rising edge, if the setup time is not met, the actual output of the chip hardware may be two cases:
the first case is that the pre-simulation is consistent with the chip real estate, as in fig. 2.
The second case is that the pre-simulation is one beat ahead of the chip reality, as in fig. 3.
Although the asynchronous cdc _ s signal changes after the rising edge of rx _ clk, if the hold time is not met, the actual output of the chip hardware may be two cases:
the first case is that the pre-simulation coincides with the actual output condition of the chip, as shown in fig. 4.
The second case is that the pre-simulation actually outputs one beat later than the chip, as in fig. 5.
The four types are different between the representation of the CDC signal in the pre-simulation and the representation in the real chip, and there may be a situation that the signals of the pre-simulation and the real chip are advanced by one beat or delayed by one beat, so that the pre-simulation function may be correct but the real chip function may be wrong.
The invention randomly selects whether to delay or advance one beat, so that the simulation processing circuit can simulate the condition that CDC signals are randomly delayed or advanced one beat in the process of pre-simulation, and the designed chip circuit can tolerate the influence caused by the metastable state recovery.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
FIG. 1 is a schematic diagram of a pre-simulation processing circuit of the background art of the present invention;
FIG. 2 is a schematic view of the principle a of the present invention;
FIG. 3 is a schematic view of the principle b of the present invention;
FIG. 4 is a schematic view of the principle c of the present invention;
FIG. 5 is a schematic view of the principle d of the present invention;
FIG. 6 is a schematic diagram of a pre-simulation processing circuit of the present invention;
in fig. 1-6, rx _ clk is the asynchronous receiving clock, cdc _ s is the asynchronous signal, q (sim) is the flip-flop emulation output, and q (hw) is the chip flip-flop actual output.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The technical solution of the present invention will be described in detail with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Referring to fig. 6, fig. 6 is a schematic diagram of a pre-simulation processing circuit according to the present invention.
A pre-simulation analog processing circuit comprises a clock A, a first register R1, a second register R2, a third register R3, a selector and a clock B, wherein the first register R1 is provided with a first register signal input end, a first register signal output end and a first register clock end, the second register R2 is provided with a second register signal input end, a second register signal output end and a second register clock end, the third register R3 is provided with a third register signal input end, a third register signal output end and a third register clock end, the selector is provided with a selection end, a selector output end and a random value, the selection end is connected with the random value and comprises a first selection end, a second selection end and a third selection end, the clock B is provided with a clock B time control output end and a clock B signal input end, the clock A is provided with a clock A signal output end, the clock A signal output end is connected with the first register signal input end, the first register signal output end is connected with the second register signal input end, the first register signal output end is further connected with the first selection end, the clock B time control output end is respectively connected with the first register clock end, the second register clock end and the third register clock end, the second register signal output end is respectively connected with the third register signal input end and the second selection end, the third register signal output end is connected with the third selection end, and the selector output end is connected with the clock B signal input end.
Delaying one beat: at this time, the third selection terminal is selected, the signal s from the clock a enters from the third register signal input terminal through the first register R1 and the second register R2, the signal q3 is output from the third register signal output terminal, and the signal q3 is output through the selector output terminal and input through the clock B signal input terminal.
One beat in advance: at this time, the first selection terminal is selected, the signal s from the clock a enters through the first register signal input terminal, the signal q1 is output from the first register output terminal, and the signal q1 is output through the selector output terminal and input through the clock B signal input terminal.
And (3) standard output: at this time, the second selection terminal is selected, the signal s from the clock a enters from the second register signal input terminal after passing through the first register R1, the signal q2 is output from the second register signal output terminal, and the signal q2 is output from the selector output terminal and input through the clock B signal input terminal.
Therefore, according to the random signal of the selector, the asynchronous processing signal can be randomly selected to be output with one beat delay or one beat advance, the influence of simulating the CDC signal on the chip function in the preceding simulation stage is realized, and the condition that the preceding simulation function is correct but the actual chip function is wrong is avoided.
By adding the third register R3 and the selector in the prior pre-simulation analog processing circuit, the situation that the CDC signal is randomly delayed by one beat can be simulated during pre-simulation, so that the designed chip circuit can tolerate the metastable state.
Optionally, the selector is a MUX selector.
Based on foretell preceding analog simulation processing circuit, the utility model discloses still provide a chip circuit can tolerate preceding simulation method of metastable state, this method adopts foretell preceding analog simulation processing circuit.
In the description of the present invention, it is to be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, a fixed connection, an indirect connection via an intermediary, a connection between two elements, or an interaction between two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention. In the description of the present invention, "a plurality" means two or more unless specifically stated otherwise.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present application and in the drawings described above, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.
Claims (2)
1. A metastable state analog processing circuit in pre-simulation comprises a clock A, a first register R1, a second register R2 and a clock B, wherein the first register R1 is provided with a first register signal input end, a first register signal output end and a first register clock end, the second register R2 is provided with a second register signal input end, a second register signal output end and a second register clock end, the clock B is provided with a clock B time control output end and a clock B signal input end, the clock A is provided with a clock A signal output end, the clock A signal output end is connected with the first register signal input end, the first register signal output end is connected with the second register signal input end, the clock B time control output end is respectively connected with the first register clock end and the second register clock end, and is characterized by further comprising a third register R3 and a selector, the third register R3 is provided with a third register signal input end, a third register signal output end and a third register clock end, the selector is provided with a selection end, a selector output end and a random value, the selection end is connected with the random value, the selection end comprises a first selection end, a second selection end and a third selection end, the first register signal output end is further connected with the first selection end, the clock B time control output end is further connected with the third register clock end, the second register signal output end is respectively connected with the third register signal input end and the second selection end, the third register signal output end is connected with the third selection end, and the selector output end is connected with the clock B signal input end.
2. The circuitry for analog processing of meta-stability in pre-simulation as claimed in claim 1, wherein said selector is a MUX selector.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202023008118.9U CN213458042U (en) | 2020-12-15 | 2020-12-15 | Analog processing circuit for metastable state in pre-simulation |
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| CN202023008118.9U CN213458042U (en) | 2020-12-15 | 2020-12-15 | Analog processing circuit for metastable state in pre-simulation |
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