CN104113304A - Two-phase mutually non-overlap clock circuit and method thereof - Google Patents
Two-phase mutually non-overlap clock circuit and method thereof Download PDFInfo
- Publication number
- CN104113304A CN104113304A CN201410291168.2A CN201410291168A CN104113304A CN 104113304 A CN104113304 A CN 104113304A CN 201410291168 A CN201410291168 A CN 201410291168A CN 104113304 A CN104113304 A CN 104113304A
- Authority
- CN
- China
- Prior art keywords
- output
- input
- gate
- delay unit
- door
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Disclosed in the invention is a two-phase mutually non-overlap clock circuit comprising an input buffer unit, a first NOT gate, a first time delay unit, a second time delay unit, a first AND gate, a second AND gate, a first output buffer unit, and a second output buffer unit. The input terminal of the first NOT gate is connected with the output terminal of the input buffer unit; the input terminal of the first time delay unit is connected with the output terminal of the first NOT gate; the input terminal of the second time delay unit is connected with the output terminal of the first time delay unit; the input terminal of the first AND gate is respectively connected with the output terminal of the input buffer unit and the output terminal of the first time delay unit; the input terminal of the second AND gate is respectively connected with the output terminal of the first NOT gate and the output terminal of the second time delay unit; the input terminal of the first output buffer unit is connected with the output terminal of the first AND gate; and the input terminal of the second output buffer unit is connected with the output terminal of the second AND gate. According to the invention, the clock time delay is determined precisely by the way of capacitor introduction into the circuit; the precision and the stability are high; the non-overlap degree of the generated two-phase mutually non-overlap clock signal is good; and the integrating degree of the simulation result and the chip is high.
Description
Technical field
The present invention relates to circuit design technique field, be specifically related to two not overlapping clock circuit and methods thereof mutually.
Background technology
Of the prior art two not overlapping clock circuits are mutually mainly to have utilized the principle of inverter device time delay to produce two not overlapping clock signals mutually.But under the CMOS of standard technique, such device time delay is generally all accurate not, may there is very large deviation in the simulation result of its device time delay and measured value, this may cause the not overlapping clock of different chip chambers inconsistent, even may cause mutually not overlapping clock that circuit produces to have to a certain degree overlapping, thereby affect the actual performance of switched-capacitor circuit.
The mutual not overlapping clock of shown in Fig. 1 the two Jing Cao in 1999 Nian You Universities of California is published in " A Clock Generator and Output Buffer for 12bit; 75MS/s, 3.3V CMOS ADC with SFDR 85dB " literary composition.
With reference to Fig. 1, set forth the existing two mutual not operation principles of overlapping clock circuit.By input buffer 1 ', received the clock signal of input, for input clock signal buffering being inputed to this two not overlapping clock circuit mutually, and by logic "and" operation (first with door 5 '), produce a non-intersect clock in road with output signal after the time delay of two not gate devices; The first not gate 2 ', for clock is anti-phase, its output clock produces the non-intersect clock in another road by the output signal with after two not gate devices (the second not gate 3 ', the 3rd not gate 4 ') time delay by logic "and" operation (second with door 6 '); The first output buffer cell 7 ', its effect is the signal Buffer output producing with door 5 ' first, forms two CLK1 of overlapping clock not mutually; The second output buffer cell 8 ', its effect is the signal Buffer output producing with door 6 ' second, forms two CLK2 of overlapping clock not mutually.
As shown in Figure 2, can there is to a certain degree overlapping in of the prior art two clock signals that mutually not overlapping clock circuits produce.
Summary of the invention
The object of the present invention is to provide a kind of two not overlapping clock circuit and methods thereof mutually, by introduce the mode of delay capacitor in circuit, determine accurately clock delay, precision is high, stability good, the not overlapping degree of the two mutual overlapping clock signals that produce is not good, and the measured value compatible degree of simulation result and chip is high.
In order to achieve the above object, the present invention is achieved through the following technical solutions: a kind of two not overlapping clock circuits mutually, be characterized in, and comprise:
Accept the input buffer cell of input clock signal;
The first not gate, its input is connected with the output of described input buffer cell, for clock signal is anti-phase;
The first delay unit, its input is connected with the output of described the first not gate, postpones for generation of regular time;
The second delay unit, its input is connected with the output of described the first delay unit, postpones for generation of regular time;
First with door, its input is connected with the output of described input buffer cell and the output of described the first delay unit respectively, for carrying out logic and operation;
Second with door, its input is connected with the output of described the first not gate and the output of described the second delay unit respectively, for carrying out logic and operation;
The first output buffer cell, its input is connected with the output of door with described first, for the mutual not wherein phase of overlapping clock of Buffer output two;
The second output buffer cell, its input is connected with the output of door with described second, for mutual not another phase of overlapping clock of Buffer output two.
The first described delay unit comprises the second not gate and the first delay capacitor;
The input of the second described not gate is connected with the output of the first not gate;
The output of the second described not gate is connected with input and first delay capacitor of door with first respectively.
The second described delay unit comprises the 3rd not gate and the second delay capacitor;
The input of the 3rd described not gate is connected with the output of the second not gate;
The output of the 3rd described not gate is connected with input and first delay capacitor of door with second respectively.
A kind of two not overlapping clock circuit generation methods mutually, are characterized in, comprise following steps:
Input buffer cell receive clock signal, export to the first not gate input and first and door input;
After first non-goalkeeper's clock signal is anti-phase, export to the first delay unit input and second and door input;
The first delay unit by clock signal be fixed export to after time delay first with the input of door and the input of the second delay unit;
The second delay unit by clock signal be fixed export to after time delay second with the input of door;
First carries out exporting to after logic and operation the input of the first output buffer cell with the clock signal of goalkeeper's input buffer cell output, the clock signal of the first delay unit output;
Second carries out exporting to after logic and operation the input of the second output buffer cell with the clock signal of goalkeeper's the first not gate output, the clock signal of the second delay unit output;
A wherein phase in the first output buffer unit buffers output two mutual not overlapping clocks;
Another phase in the second output buffer unit buffers output two mutual not overlapping clocks.
The present invention two mutually not overlapping clock circuit and method thereof compared with prior art has the following advantages: by introduce the mode of delay capacitor in circuit, determine accurately clock delay, precision is high, stability good; This circuit can only change the not overlapping time by adjusting the capacitance of delay capacitor very easily, and the not overlapping degree of two mutual overlapping clock signals of generation is not good, and the measured value compatible degree of simulation result and chip is high.
Accompanying drawing explanation
Fig. 1 is the two mutual not block diagrams of overlapping clock circuit in prior art.
Fig. 2 is the not overlapping clock signal schematic diagram mutually that in prior art, two mutually not overlapping clock circuits generate.
Fig. 3 is the mutual not block diagram of overlapping clock circuit of the present invention a kind of two.
Fig. 4 is embodiment design sketch.
Embodiment
Below in conjunction with accompanying drawing, by describing a preferably specific embodiment in detail, the present invention is further elaborated.
As shown in Figure 3, a kind of two not overlapping clock circuits mutually, comprise: the input buffer cell 1 of accepting input clock signal; The first not gate 2, its input is connected with the output of described input buffer cell 1, for clock signal is anti-phase; The first delay unit 3, its input is connected with the output of described the first not gate 2, postpones for generation of regular time; The second delay unit 4, its input is connected with the output of described the first delay unit 3, postpones for generation of regular time; First with door 5, its input is connected with the output of described input buffer cell 1 and the output of described the first delay unit 3 respectively, for carrying out logic and operation; Second with door 6, its input is connected with the output of described the first not gate 2 and the output of described the second delay unit 4 respectively, for carrying out logic and operation; The first output buffer cell 7, its input is connected with the output of door 5 with described first, for the mutual not wherein phase of overlapping clock of Buffer output two; The second output buffer cell 8, its input is connected with the output of door 6 with described second, for mutual not another phase of overlapping clock of Buffer output two.
The first delay unit 3 comprises the second not gate 31 and the first delay capacitor 32; The input of the second described not gate 31 is connected with the output of the first not gate 2; The output of the second described not gate 31 is connected with input and first delay capacitor 32 of door 5 with first respectively.The second not gate 31, anti-phase for input signal is carried out, and at the limited inversion signal of its output node output driving current; The first delay capacitor 32, produces time delay interval and the linear signal of delay capacitor for output node at the second not gate 31.
The second delay unit 4 comprises the 3rd not gate 41 and the second delay capacitor 42; The input of the 3rd described not gate 41 is connected with the output of the second not gate 31; The output of the 3rd described not gate 41 is connected with input and first delay capacitor 32 of door 6 with second respectively.The 3rd not gate 41, anti-phase for input signal is carried out, and at the limited inversion signal of its output node output driving current; The second delay capacitor 42, produces time delay interval and the linear signal of delay capacitor for output node at the 3rd not gate 41.Fig. 4 has shown the effect that the present invention can reach.
A kind of two not overlapping clock circuit generation methods mutually, comprise following steps:
Input buffer cell 1 receive clock signal, exports the input and first and door 5 input of the first not gate 2 to;
After the first not gate 2 is anti-phase by clock signal, export the input and second and door 6 input of the first delay unit 3 to;
The first delay unit 3 by clock signal be fixed export to after time delay first with the input of door 5 and the input of the second delay unit 4;
The second delay unit 4 by clock signal be fixed export to after time delay second with the input of door 6;
First carries out the clock signals of clock signals for input buffer cell 1 output, the first delay unit 3 outputs to export to after logic and operation the input of the first output buffer cell 7 with door 5;
Second carries out the clock signals of clock signals for the first not gate 2 output, the second delay unit 4 outputs to export to after logic and operation the input of the second output buffer cell 8 with door 6;
A wherein phase in the mutual not overlapping clock of the first output buffer cell 7 Buffer output two;
Another phase in the mutual not overlapping clock of the second output buffer cell 8 Buffer output two.
Although content of the present invention has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.Those skilled in the art, read after foregoing, for multiple modification of the present invention with to substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (4)
1. two not overlapping clock circuits mutually, is characterized in that, comprise:
Accept the input buffer cell (1) of input clock signal;
The first not gate (2), its input is connected with the output of described input buffer cell (1), for clock signal is anti-phase;
The first delay unit (3), its input is connected with the output of described the first not gate (2), postpones for generation of regular time;
The second delay unit (4), its input is connected with the output of described the first delay unit (3), postpones for generation of regular time;
First with door (5), its input is connected with the output of described input buffer cell (1) and the output of described the first delay unit (3) respectively, for carrying out logic and operation;
Second with door (6), its input is connected with the output of described the first not gate (2) and the output of described the second delay unit (4) respectively, for carrying out logic and operation;
The first output buffer cell (7), its input is connected with the output of door (5) with described first, for the mutual not wherein phase of overlapping clock of Buffer output two;
The second output buffer cell (8), its input is connected with the output of door (6) with described second, for mutual not another phase of overlapping clock of Buffer output two.
2. as claimed in claim 1 two not overlapping clock circuits mutually, is characterized in that, described the first delay unit (3) comprises the second not gate (31) and the first delay capacitor (32);
The input of described the second not gate (31) is connected with the output of the first not gate (2);
The output of described the second not gate (31) is connected with input and first delay capacitor (32) of door (5) with first respectively.
3. as claimed in claim 1 two not overlapping clock circuits mutually, is characterized in that, described the second delay unit (4) comprises the 3rd not gate (41) and the second delay capacitor (42);
The input of the 3rd described not gate (41) is connected with the output of the second not gate (31);
The output of the 3rd described not gate (41) is connected with input and first delay capacitor (32) of door (6) with second respectively.
4. not overlapping clock circuit generation method mutually, is characterized in that, comprises following steps:
Input buffer cell (1) receive clock signal, export to the first not gate (2) input and first and door (5) input;
After the first not gate (2) is anti-phase by clock signal, export to the first delay unit (3) input and second and door (6) input;
The first delay unit (3) by clock signal be fixed export to after time delay first with the door input of (5) and the input of the second delay unit (4);
The second delay unit (4) by clock signal be fixed export to after time delay second with the input of door (6);
First carries out the clock signal of the clock signal of input buffer cell (1) output, the first delay unit (3) output to export to after logic and operation the input of the first output buffer cell (7) with door (5);
Second carries out the clock signal of the clock signal of the first not gate (2) output, the second delay unit (4) output to export to after logic and operation the input of the second output buffer cell (8) with door (6);
A wherein phase in the first output buffer cell (7) Buffer output two mutual not overlapping clocks;
Another phase in the second output buffer cell (8) Buffer output two mutual not overlapping clocks.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410291168.2A CN104113304B (en) | 2014-06-26 | 2014-06-26 | Two-phase mutually non-overlap clock circuit and method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410291168.2A CN104113304B (en) | 2014-06-26 | 2014-06-26 | Two-phase mutually non-overlap clock circuit and method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104113304A true CN104113304A (en) | 2014-10-22 |
| CN104113304B CN104113304B (en) | 2017-01-11 |
Family
ID=51709959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410291168.2A Active CN104113304B (en) | 2014-06-26 | 2014-06-26 | Two-phase mutually non-overlap clock circuit and method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104113304B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106130540A (en) * | 2016-07-05 | 2016-11-16 | 中国科学院上海微系统与信息技术研究所 | Broad-adjustable disjoint signals circuit and system |
| CN108566180A (en) * | 2018-05-04 | 2018-09-21 | 中国科学技术大学 | A kind of single delay chain circuit generating two-way delay |
| CN109804426A (en) * | 2017-08-16 | 2019-05-24 | 深圳市汇顶科技股份有限公司 | Image sensing circuit and picture depth sensor-based system |
| CN110768674A (en) * | 2019-10-29 | 2020-02-07 | 湖南国科微电子股份有限公司 | Analog-to-digital conversion device, analog-to-digital conversion equipment and analog-to-digital conversion method |
| WO2021258801A1 (en) * | 2020-06-22 | 2021-12-30 | 深圳比特微电子科技有限公司 | Clock circuit system, computing chip, hash board, and data processing device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5867453A (en) * | 1998-02-06 | 1999-02-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-setup non-overlap clock generator |
| CN102522994A (en) * | 2011-12-07 | 2012-06-27 | 清华大学 | Clock generation circuit used in analog-to-digital converter (ADC) with high speed and high precision |
| CN103166605A (en) * | 2013-01-25 | 2013-06-19 | 湘潭芯力特电子科技有限公司 | Multiphase non-overlapping clock circuit |
-
2014
- 2014-06-26 CN CN201410291168.2A patent/CN104113304B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5867453A (en) * | 1998-02-06 | 1999-02-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-setup non-overlap clock generator |
| CN102522994A (en) * | 2011-12-07 | 2012-06-27 | 清华大学 | Clock generation circuit used in analog-to-digital converter (ADC) with high speed and high precision |
| CN103166605A (en) * | 2013-01-25 | 2013-06-19 | 湘潭芯力特电子科技有限公司 | Multiphase non-overlapping clock circuit |
Non-Patent Citations (1)
| Title |
|---|
| 张勇: "《基于流水型ADC的真随机数发生器的设计与实现》", 《中国优秀硕士学位论文全文数据库（电子期刊）》 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106130540A (en) * | 2016-07-05 | 2016-11-16 | 中国科学院上海微系统与信息技术研究所 | Broad-adjustable disjoint signals circuit and system |
| CN109804426A (en) * | 2017-08-16 | 2019-05-24 | 深圳市汇顶科技股份有限公司 | Image sensing circuit and picture depth sensor-based system |
| CN109804426B (en) * | 2017-08-16 | 2021-04-27 | 深圳市汇顶科技股份有限公司 | Image sensing circuit and image depth sensing system |
| US11089245B2 (en) | 2017-08-16 | 2021-08-10 | Shenzhen GOODIX Technology Co., Ltd. | Image sensor circuit and image depth sensor system |
| CN108566180A (en) * | 2018-05-04 | 2018-09-21 | 中国科学技术大学 | A kind of single delay chain circuit generating two-way delay |
| CN110768674A (en) * | 2019-10-29 | 2020-02-07 | 湖南国科微电子股份有限公司 | Analog-to-digital conversion device, analog-to-digital conversion equipment and analog-to-digital conversion method |
| WO2021258801A1 (en) * | 2020-06-22 | 2021-12-30 | 深圳比特微电子科技有限公司 | Clock circuit system, computing chip, hash board, and data processing device |
| TWI784457B (en) * | 2020-06-22 | 2022-11-21 | 大陸商深圳比特微電子科技有限公司 | Clock circuitry, computing chips, hashboards and data processing equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104113304B (en) | 2017-01-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104113304A (en) | Two-phase mutually non-overlap clock circuit and method thereof | |
| US8760325B2 (en) | Scheme for balancing skew between lanes of high-speed serial digital interface | |
| CN105811923B (en) | A kind of clock duty cycle adjustment circuit | |
| Patel et al. | VHDL implementation of UART with status register | |
| CN102804157B (en) | The calibration of the write timing in storage arrangement | |
| CN103731136B (en) | Sequential equivalent sampling circuit and method based on delay signals | |
| CN106886636A (en) | A kind of accurate Forecasting Methodology of the worst power supply noise of high-speed circuit system | |
| CN105445645A (en) | Digital monitoring circuit used for monitoring integrated circuit NBTI aging effect | |
| US9256246B1 (en) | Clock skew compensation with adaptive body biasing in three-dimensional (3D) integrated circuits (ICs) (3DICs) | |
| CN109284084A (en) | A kind of real random number generator of no capacitance coupling effect | |
| CN103354448B (en) | Based on the high resolution time interval generation system of FPGA | |
| US10169527B2 (en) | Accurate statistical timing for boundary gates of hierarchical timing models | |
| CN104579295A (en) | Clock dynamic switching circuit and method | |
| CN102435818A (en) | Test method of high-precision dynamic comparator and test circuit thereof | |
| CN107943205B (en) | Circuit and method for calculating clock period by using delay chain in DDR (double data rate) comprehensive physical layer | |
| CN204065907U (en) | A kind of MCU chip frequency-dividing clock means for correcting | |
| CN106209090A (en) | A kind of combining unit pulse per second (PPS) synchronism output system and method based on FPGA | |
| CN104123966A (en) | Automatic periodic read operation based read speed measuring circuit | |
| CN105607689A (en) | High-speed multiphase clock synchronization method | |
| CN103425043A (en) | High-precision time-to-digital converter based on USB | |
| Szplet et al. | A flash time-to-digital converter with two independent time coding lines | |
| JP2022529634A (en) | Switch leak compensation circuit | |
| WO2014038173A1 (en) | Ad converter and receiving apparatus | |
| CN204480671U (en) | A kind of antimierophonic delay counter | |
| CN203632631U (en) | Non-overlapping clock generating clock |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |