CN204065907U - A kind of MCU chip frequency-dividing clock means for correcting - Google Patents
A kind of MCU chip frequency-dividing clock means for correcting Download PDFInfo
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- CN204065907U CN204065907U CN201420403988.1U CN201420403988U CN204065907U CN 204065907 U CN204065907 U CN 204065907U CN 201420403988 U CN201420403988 U CN 201420403988U CN 204065907 U CN204065907 U CN 204065907U
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Abstract
The utility model discloses a kind of MCU chip frequency-dividing clock means for correcting, its this device includes clock module, clock division circuits, correcting register, correction interface, storer and means for correcting, wherein, clock module, clock division circuits, correcting register, correction interface, storer are arranged at chip internal, and means for correcting is arranged at chip exterior; When clock correction, by the means for correcting of outside, corrected value is write correcting register by correction interface, clock module adjusts clock according to corrected value, through clock division circuits, clock is exported, external calibration device exports according to clock, adjustment corrected value until the corrected value that finds clock jitter minimum, and calculates the deviate between actual frequency, by corrected value and clock jitter write chip internal storer.
Description
Technical field
The utility model relates to a kind of clock correction method, particularly relates to a kind of clock correction apparatus and method of MCU chip.
Background technology
Now in the chips, particularly the design of MCU is central all can use clock correction function usually, but be subject to restriction and the technology constraint of cost, current internal clocking only can reach the precision of 0.5% ~ 2% after correcting, such clock accuracy level is for needing asynchronous communication or requiring that higher system is then often inadequate for clock accuracy, need could be solved by the more accurate external crystal-controlled oscillation of precision, and use external crystal-controlled oscillation can increase hardware cost, and external crystal-controlled oscillation needs to increase new IO, particularly increasing new IO for the system that design size is less can cause whole hardware area to become large, scheme is caused to realize.
Patented claim 2004100864081 provides a kind of monitoring clock correction method and device, this monitoring clock correction method and device, a signal source of clock is provided by outside, and after the arbitrary input end input of monitoring chip, a signal enabling Corrective control unit is exported by the buffer of monitoring chip inside, also start two counting units simultaneously, first counting unit adds up external reference clock number, second counting unit adds up the clock number of monitoring chip internal clocking generation component, first counting unit add up external reference clock count to reach some and stop counting time, second counting unit also stops the accumulative clock number produced by monitoring chip inner clock generators at one time, and produce the microprocessing unit of a look-at-me notice monitoring chip inside, relatively the first counting unit the external reference clock number that add up and the second counting unit the clock number of monitoring chip internal oscillator generation that adds up, can correct monitoring chip internal oscillator.
But when system needs a high-precision clock, simultaneously because the reason such as hardware cost and product size, when can not increase external crystal-controlled oscillation, a high-precision internal clocking oscillator just becomes the good method addressed this problem.But high-precision clock to be provided at chip internal, need the clock correction circuit that inner increase is a lot, such as want the precision reaching 0.5%, correction resistance or corrective capacity is at least needed to have 8 grades of selections at present, namely resistance (electric capacity) value scope 2^7 ~ 2^0 is corrected, when needs improve precision further, need correction gear to bring up to 10 grades even more than, correct the scope at least 2^9 ~ 2^0 of resistance like this.And in scope wide like this, accomplish that the coupling of device is more difficult, need to increase more additional corrections circuit to improve the matching of device.
Summary of the invention
For solving the problem, the purpose of this utility model is to provide a kind of MCU chip frequency-dividing clock means for correcting, and this device utilizes means for correcting to correct frequency-dividing clock, greatly can improve clock accuracy on the basis of the precision of existing clock oscillator.
Another object of the present utility model is to provide a kind of MCU chip frequency-dividing clock means for correcting, and this device saves external crystal-controlled oscillation, saves exterior I O, is simple and easy to implement, and does not need to increase extra circuit and realizes.
For achieving the above object, the technical solution of the utility model is as follows.
A kind of MCU chip frequency-dividing clock means for correcting, it is characterized in that described device includes at clock module (inner crystal oscillator), clock division circuits, correcting register, correction interface, storer and means for correcting, wherein, clock module, clock division circuits, correcting register, correction interface, storer are arranged at chip internal, and means for correcting is arranged at chip exterior; Clock module is for generation of internal clocking, and clock division circuits is for generation of frequency-dividing clock, and correcting register is used for configurable clock generator corrected value, and clock module (inner crystal oscillator) connects clock division circuits, carries out communication with means for correcting; Correcting register connects correction interface, and correction interface carries out communication with means for correcting and storer respectively; Correction interface is used for communicating with external calibration device, is write by corrected value in correcting register, by last corrected value and deviation write storer; Meanwhile, corrected value is fed back to clock module by correcting register, and outside means for correcting is used for the accuracy computation of clock sampling and clock.
Described storer is nonvolatile memory.
Described means for correcting, realizes at test phase test machine, then realizes with cd-rom recorder in the burning stage.
In actual applications, most communications applications or clock timing frequency lower, the traffic rate of such as uart is generally 9.6KHz or 4.8KHz, and clock-timed frequency is lower, is generally counting 1 second or 1 minute.The clock frequency of major clock is higher, generally reaches 10MHz ~ 20MHz.Ratio between the two reaches more than 1000:1, ratio between major clock crystal oscillator and communication clock is just become through being carried out communication clock deviation after offset correction or timer clock deviation by means for correcting, therefore after the MCU chip frequency-dividing clock means for correcting that the utility model realizes, practical communication clock jitter can reach less than 0.1%, the clock jitter of clock timer can reach 1*10^ (-7) below, substantially increases the clock accuracy of practical application.
Accompanying drawing explanation
Fig. 1 is the hardware structure diagram that the utility model is implemented.
Fig. 2 is the clock correction process flow diagram that the utility model is implemented.
Fig. 3 is the process flow diagram of the clock correction that the utility model is applied.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the utility model, and be not used in restriction the utility model.
Shown in Fig. 1, be the circuit diagram of the MCU chip frequency-dividing clock means for correcting that the utility model realizes, shown in figure, generally have inner crystal oscillator at chip internal, clock division circuits, correcting register, correction interface and storer, have means for correcting in the outside of chip.
Wherein, clock module, clock division circuits, correcting register, correction interface, storer are arranged at chip internal, and means for correcting is arranged at chip exterior; Clock module is for generation of internal clocking, and clock division circuits is for generation of frequency-dividing clock, and correcting register is used for configurable clock generator corrected value, and clock module (inner crystal oscillator) connects clock division circuits, carries out communication with means for correcting; Correcting register connects correction interface, and correction interface carries out communication with means for correcting and storer respectively; Correction interface is used for communicating with external calibration device, is write by corrected value in correcting register, by last corrected value and deviation write storer; Meanwhile, corrected value is fed back to clock module by correcting register, and outside means for correcting is used for the accuracy computation of clock sampling and clock.
Because trimming process generally completes at chip testing phase or in the burning chip stage, described means for correcting, realizes at test phase test machine, then realizes with cd-rom recorder in the burning stage.
Shown in Fig. 2, bearing calibration is: when clock correction, by the means for correcting of outside, corrected value is write correcting register by correction interface, clock module adjusts clock according to corrected value, exported by clock through clock division circuits, external calibration device exports according to clock, and adjustment corrected value is until the corrected value that finds clock jitter minimum, and the deviate calculated between actual frequency, by corrected value and clock jitter write chip internal storer.
The corresponding clock jitter of each described corrected value, by comparing the clock jitter corresponding to each corrected value, can obtain minimum clock jitter value.
In actual applications, consider the deviation of technique, the deviation that the clock that inner crystal oscillator produces is not having timing to have 20%, generally first can carry out clock correction to clock crystal oscillator, as shown in Figure 2.The clock that clock obtains a low speed by frequency division exports, the outside clock crystal oscillator of a high speed that adopts is sampled to this clock, (inner crystal oscillator is referred to here when clock is fast, fast for design load, inner crystal oscillator is fast, clock exports also can be thereupon fast) time, (this clock correction value is generally the number of bit more than to amendment clock correction value, concrete bit wide confirms when designing, if such as our corrected value is 8 bits, so clock correction value can from 0x00 until 0xFF, each corrected value can a corresponding different internal clock frequencies, minimum value can be found) by calculating, clock is exported slack-off, when clock is partially slow, amendment clock correction value, clock is exported accelerate.
The corrected value such as given tacit consent to is 0x80, corrected value increases, and clock frequency slows down, corrected value reduces, and clock frequency speeds, find that clock frequency is partially slow when adopting acquiescence corrected value to measure (measurement is compared by actual clock frequency f real=M*fout and fdesign), amendment corrected value is 0x7F, retest clock frequency, if still partially slow, again reduce (generally to have a default step-length, reduce according to the step-length preset, default step-length can be adopted to estimate, obtain best corrected value fast) clock correction value, till the corrected value finding clock jitter minimum.
Shown in Fig. 3, in the calculating of the enterprising stepping row clock deviation in basis corrected, delta=freal/fdesign-1, for the number N choosing calibration cycle during the precision needed according to the actual requirements and surely, and corrected value (corrected value that minimum deflection is corresponding) and deviate are write preservation in the flash (can be the nonvolatile memories such as OTP or EEPROM) of chip herein.When carrying out clock division and arranging, deviate is read from flash, calculate actual frequency division value.
Suppose that the frequency of our current major clock is 20MHz (fdesign), asynchronous communication speed is 4.8KHz, and chip deviate is the correction that-1.002% such clock that we can select chip to export a 4.8KHz (theoretic divide ratio M is 4166) carries out clock.Adopt the clock (ftest) of 50MHz to sample during chip testing, the cycle of sampling is 20 times (N).Because the clock of sampling and the clock that is sampled exist certain phase deviation, therefore there will be the sampling error of one-period, because sampling error=fdiv/ (N*ftest) is far smaller than the clock division precision after correction, therefore can ignore.Sampling error is 4.8*10^3/ (20*50*10^6)=4.8*10^ (-6).Because the precision after error amount is far smaller than correction can be ignored.The divide ratio that clock exports is 20*10^6* (1-1.002%)/4.8*10^3=4125, and the deviation that last clock exports is 20*10^6* (1-1.002%)/4125/4.8*10^3-1=-2.02^10 (-5).Can find out that the precision of communication frequency precision comparison clock correction is now greatly improved.
If there is multiple application needing high precision clock timing in actual chips, can consider that carrying out independent clock jitter for each frequency-dividing clock calculates, then, in the middle of the flash deviation of each frequency-dividing clock being write chip, when clock division value is set, corresponding deviate is selected to carry out calculating.
The utility model, by correction, can increase substantially clock accuracy effectively, and saves external crystal-controlled oscillation, saves exterior I O, is simple and easy to implement, and does not need to increase extra circuit and realizes, with low cost.
In a word; the foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model, all do within spirit of the present utility model and principle any amendment, equivalent to replace and improvement etc., all should be included within protection domain of the present utility model.
Claims (3)
1. a MCU chip frequency-dividing clock means for correcting, it is characterized in that described device includes clock module, clock division circuits, correcting register, correction interface, storer and means for correcting, wherein, clock module, clock division circuits, correcting register, correction interface, storer are arranged at chip internal, and means for correcting is arranged at chip exterior; Clock module is for generation of internal clocking, and clock division circuits is for generation of frequency-dividing clock, and correcting register is used for configurable clock generator corrected value, and clock module connects clock division circuits, carries out communication with means for correcting; Correcting register connects correction interface, and correction interface carries out communication with means for correcting and storer respectively; Correction interface is used for communicating with external calibration device, is write by corrected value in correcting register, by last corrected value and deviation write storer; Meanwhile, corrected value is fed back to clock module by correcting register, and outside means for correcting is used for the accuracy computation of clock sampling and clock.
2. MCU chip frequency-dividing clock means for correcting as claimed in claim 1, it is characterized in that described storer, is nonvolatile memory.
3. MCU chip frequency-dividing clock means for correcting as claimed in claim 1, it is characterized in that described means for correcting, is test machine or cd-rom recorder.
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| CN201420403988.1U CN204065907U (en) | 2014-07-21 | 2014-07-21 | A kind of MCU chip frequency-dividing clock means for correcting |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104122936A (en) * | 2014-07-21 | 2014-10-29 | 深圳市芯海科技有限公司 | MCU chip frequency division clock correcting device and method |
| CN106598137A (en) * | 2016-11-02 | 2017-04-26 | 深圳驰芯微电子有限公司 | Chip |
| CN112419628A (en) * | 2020-11-20 | 2021-02-26 | 深圳市捷诚技术服务有限公司 | RTC (real time clock) calibration method and device, computer readable medium and POS (point of sale) machine |
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2014
- 2014-07-21 CN CN201420403988.1U patent/CN204065907U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104122936A (en) * | 2014-07-21 | 2014-10-29 | 深圳市芯海科技有限公司 | MCU chip frequency division clock correcting device and method |
| CN104122936B (en) * | 2014-07-21 | 2017-06-13 | 深圳市芯海科技有限公司 | A kind of MCU chip frequency-dividing clock means for correcting and method |
| CN106598137A (en) * | 2016-11-02 | 2017-04-26 | 深圳驰芯微电子有限公司 | Chip |
| CN112419628A (en) * | 2020-11-20 | 2021-02-26 | 深圳市捷诚技术服务有限公司 | RTC (real time clock) calibration method and device, computer readable medium and POS (point of sale) machine |
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Address after: 518000, A building, block 9, garden city digital garden, 1079 Nanhai Road, Guangdong, Shenzhen, Nanshan District Patentee after: Chipsea Technology (Shenzhen) Co., Ltd. Address before: 518067 Nanshan District, Shenzhen, Nanhai Avenue, garden city, No. 1079, building A, block, floor 9 Patentee before: Xinhai Science and Technology Co., Ltd., Shenzhen City |