CN106598137A - Chip and method for manufacturing the same - Google Patents
Chip and method for manufacturing the same Download PDFInfo
- Publication number
- CN106598137A CN106598137A CN201610952467.5A CN201610952467A CN106598137A CN 106598137 A CN106598137 A CN 106598137A CN 201610952467 A CN201610952467 A CN 201610952467A CN 106598137 A CN106598137 A CN 106598137A
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- Prior art keywords
- module
- chip
- internal clocking
- sleep
- clock
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- 238000000034 method Methods 0.000 title abstract description 3
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000004891 communication Methods 0.000 claims abstract description 35
- 238000001514 detection method Methods 0.000 claims 1
- 238000013461 design Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000000686 essence Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
- Mobile Radio Communication Systems (AREA)
- Transceivers (AREA)
Abstract
The invention provides a chip, comprising: the internal clock module is used for generating the internal clock signal of the chip; the sleep and wake-up module is connected with the internal clock module and is used for controlling the internal clock module to enter a sleep mode or wake up the internal clock module; and the dynamic clock adjusting module is connected to the internal clock module and used for adjusting the clock frequency of the chip. The chip is designed to add the functions of deep sleep and quick awakening without reducing the encryption property, the intervention of host software is completely not needed, the complexity of master control hardware and software is not increased, all the functions are automatically completed, the working frequency is relatively low in ordinary communication, the power consumption can be saved, and the clock can be automatically adjusted to high frequency in the operation encryption process to ensure that the operation is completed within the specified time.
Description
Technical field
The present invention relates to chip design art field, more particularly to chip.
Background technology
Encryption chip is applied in many electronic systems, for protecting the design of software/hardware, protects safety of data etc.
Deng, but current encryption chip, such as ATMEL, Maxim etc., AES is all mainly biased toward, ignore power problemses.Due to adding
Close chip power-consumption is typically little, is in the past not need especially low power consumption.But modern new electronic system is mainly portable type
Equipment, such as mobile phone, flat board and handheld game machine, these battery apparatus are to take notice of very much power problemses.So, at present can only be
When discord encryption chip communicates, its dump, this method can increase hardware cost and increase the difficulty of software design.
Therefore, for drawbacks described above, a kind of chip of necessary design, to solve drawbacks described above.
The content of the invention
It is an object of the invention to overcome the defect of prior art, there is provided one kind can chip, its can not reduce encryption
Property and do not increase under conditions of any complexity of master control hardware and software, reduce the power consumption of chip itself.
What the present invention was realized in：A kind of chip, including：Internal clocking module, for chip internal clock letter
Number generation；Sleep and wake module, are connected to the internal clocking module, enter to fall asleep for controlling the internal clocking module
Sleep mode wakes up the internal clocking module；Dynamic clock adjusting module, is connected to the internal clocking module, for adjusting
The whole chip clock frequency.
Further, also including communication interface modules, for producing the signal that signal of communication and demodulation are received.
Further, also including enciphering algorithm module, for being encrypted to algorithm and protecting.
Further, also including communication speed matching module, for detecting communication speed, and according to the communication speed come
Adjust the internal clocking module.
Further, the sleep and wake module can preset time point.
Further, the enciphering algorithm module is using 160 canonical algorithms or 192 Bits Expanding algorithms.
The present invention provides a kind of chip, including internal clocking module, for the generation of the chip internal clock signal；Sleep
Sleep and wake module, be connected to the internal clocking module, for controlling the internal clocking module into sleep pattern or
Wake up the internal clocking module；Dynamic clock adjusting module, is connected to the internal clocking module, for adjusting the chip
Clock frequency.This design of chip, under conditions of encryption is not reduced completely, adds the work(of deep sleep and fast wake-up
Can, completely without the intervention of host software, any complexity of master control hardware and software will not be increased, all are automatically performed,
Meanwhile, dynamic clock adjusting module is employed, in common communications, operating frequency compares relatively low, can so save power consumption,
When computing is encrypted, clock can be automatically adjusted on high frequency, it is ensured that completed within the time of regulation.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, without having to pay creative labor, may be used also
To obtain other accompanying drawings according to these accompanying drawings.
Fig. 1 is the schematic diagram of chip provided in an embodiment of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than the embodiment of whole.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
As Fig. 1, the embodiment of the present invention provide a kind of chip, the chip includes internal clocking module 1, in the chip
The generation of portion's clock signal；Sleep and wake module 2, are connected to the internal clocking module 1, for controlling the internal clocking
Module 1 enters sleep pattern or wakes up the internal clocking module；Dynamic clock adjusting module 3, when being connected to described internal
Clock module 1, for adjusting the chip clock frequency.The dynamic clock adjusting module 3, in common communications, operating frequency
Compare relatively low, can so save power consumption, when computing is encrypted, clock can be automatically adjusted on high frequency, it is ensured that in regulation
Complete in time.The dynamic clock adjusting module 3 is minimum to accomplish power to adjust clock frequency according to the needs of computing,
Further, as shown in figure 1, in specific embodiment structure of the present invention, also including communication interface modules 4, being used for
Signal of communication and the signal that receives of demodulation are produced, response is produced according to communication protocol, shaken hands and the communication operation such as data exchange.Also
Including enciphering algorithm module 5, for being encrypted to algorithm and protecting.Enciphering algorithm module of the present invention 5 is using 160 marks
Quasi- algorithm or 192 Bits Expanding algorithms, can as needed select 160 canonical algorithms or 192 Bits Expanding algorithms.Difference exists
In chip power-consumption is easier to be cracked than relatively low but extensive because of using during 160 canonical algorithms of selection, and selects 192
Bits Expanding algorithm, chip power-consumption will relatively select chip power-consumption during 160 canonical algorithms high, but security performance is high.It is big absolutely
Enciphering algorithm module 5 described in most time is all processing communication work, and communication speed is very slow, at this time clock can be reduced, only
Have when the computing of the enciphering algorithm module 5 is encrypted, just need at full speed, and only give the full-speed clock of the enciphering algorithm module 5.
Further, as shown in figure 1, in specific embodiment structure of the present invention, also including communication speed matching module 6,
For detecting communication speed, and according to the communication speed adjusting the internal clocking module so that internal clocking just may be used
To meet communication needs, so ensure that chip runs under low-limit frequency, realizes lowest power consumption.
Further, as shown in figure 1, in specific embodiment structure of the present invention, the sleep and wake module 2 can be advance
Setting time point.The sleep and wake module 2 can ceaselessly detect the communication interface modules 4 if it exceeds described set in advance
Fixed time point, internal clocking can stop completely, low in energy consumption to several uW into deep sleep.The enciphering algorithm module 5 is in
Under this kind of state.When the communication interface modules 4 has any signal, the sleep and wake module 2 wake up at once clock, due to
It is just to start, the clock frequency of the internal clocking module 1 is not very stable, the now communication speed matching module 6 meeting
The clock of matching communication, it is ensured that accuracy.The principle of matching be waken up due to the internal clocking module after, communication now
Speed with sleep before communication speed be as because internal clocking start after frequency drift scope be also to be known a priori by,
After startup, several points in frequency range are all sampled, best point is locked as early as possible according to communication feature, and during this
Do not stop to adjust, till frequency stable.
The chip employs dynamic clock adjusting module 3, is connected to the internal clocking module 1, described for adjusting
Chip clock frequency.Additionally use communication speed matching module 6, for detecting communication speed, and according to the communication speed come
Adjust the internal clocking module so that internal clocking can just meet communication needs, so ensure chip in low-limit frequency
Lower operation, realizes lowest power consumption.This design of chip, under conditions of encryption is not reduced completely, add deep sleep and
The function of fast wake-up, completely without the intervention of host software, will not increase any complexity of master control hardware and software, and one
Cut and be automatically performed, in common communications, operating frequency compares relatively low, can so save power consumption, when computing is encrypted, clock
Can be automatically adjusted on high frequency, it is ensured that complete within the time of regulation.
Presently preferred embodiments of the present invention is the foregoing is only, not to limit the present invention, all essences in the present invention
Within god and principle, any modification, equivalent substitution and improvements made etc. should be included within the scope of the present invention.
Claims (6)
1. a kind of chip, it is characterised in that include：
Internal clocking module, for the generation of the chip internal clock signal；
Sleep and wake module, are connected to the internal clocking module, and for controlling the internal clocking module sleep mould is entered
Formula wakes up the internal clocking module；
Dynamic clock adjusting module, is connected to the internal clocking module, for adjusting the chip clock frequency.
2. chip as claimed in claim 1, it is characterised in that also including communication interface modules, for produce signal of communication and
The signal that demodulation is received.
3. chip as claimed in claim 1, it is characterised in that also including enciphering algorithm module, for being encrypted to algorithm
And protection.
4. chip as claimed in claim 1, it is characterised in that also including communication speed matching module, for detection communication speed
Degree, and according to the communication speed adjusting the internal clocking module.
5. chip as claimed in claim 1, it is characterised in that the sleep and wake module can preset time point.
6. chip as claimed in claim 3, it is characterised in that the enciphering algorithm module using 160 canonical algorithms or
192 Bits Expanding algorithms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610952467.5A CN106598137A (en) | 2016-11-02 | 2016-11-02 | Chip and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610952467.5A CN106598137A (en) | 2016-11-02 | 2016-11-02 | Chip and method for manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106598137A true CN106598137A (en) | 2017-04-26 |
Family
ID=58589599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610952467.5A Pending CN106598137A (en) | 2016-11-02 | 2016-11-02 | Chip and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106598137A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110908310A (en) * | 2019-12-03 | 2020-03-24 | 深圳开立生物医疗科技股份有限公司 | Clock configuration method and system of controller and ultrasonic equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102445953A (en) * | 2010-09-30 | 2012-05-09 | 重庆重邮信科通信技术有限公司 | Method for adjusting clock source of embedded equipment |
| CN204065907U (en) * | 2014-07-21 | 2014-12-31 | 深圳市芯海科技有限公司 | A kind of MCU chip frequency-dividing clock means for correcting |
| CN105183131A (en) * | 2015-08-18 | 2015-12-23 | 江苏钜芯集成电路技术有限公司 | Low power BT40 chip |
-
2016
- 2016-11-02 CN CN201610952467.5A patent/CN106598137A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102445953A (en) * | 2010-09-30 | 2012-05-09 | 重庆重邮信科通信技术有限公司 | Method for adjusting clock source of embedded equipment |
| CN204065907U (en) * | 2014-07-21 | 2014-12-31 | 深圳市芯海科技有限公司 | A kind of MCU chip frequency-dividing clock means for correcting |
| CN105183131A (en) * | 2015-08-18 | 2015-12-23 | 江苏钜芯集成电路技术有限公司 | Low power BT40 chip |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110908310A (en) * | 2019-12-03 | 2020-03-24 | 深圳开立生物医疗科技股份有限公司 | Clock configuration method and system of controller and ultrasonic equipment |
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| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
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| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20170426 |