CN111966205B - Power saving method and device for server CPLD supporting PFR - Google Patents
Power saving method and device for server CPLD supporting PFR Download PDFInfo
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Abstract
The invention provides a power saving method and a device for a server CPLD (complex programmable logic device) supporting PFR (pulse frequency response), wherein the method comprises the following steps: s1, a clock phase-locked loop module generates clocks with different frequency grades according to a clock source; s2, distributing a clock with a corresponding frequency grade for the functional module of the CPLD by the clock management module according to the system on-off state; the functional modules of the CPLD comprise a power-on module, a power-off module, a monitoring module and an authentication module; and S3, adopting the distributed clocks with corresponding frequency grades by each functional module of the CPLD, and completing authentication before system power-on, power-off and monitoring each working process according to the system power-on and power-off state in a matching manner. The invention determines and selects the clock with the frequency grade required by each module of the CPLD according to the clocks with different frequency grades and the system state, thereby achieving the effect of saving electricity and improving the defects of single clock work and high electricity consumption of the traditional server CPLD.
Description
Technical Field
The invention belongs to the technical field of power consumption control of CPLDs, and particularly relates to a power saving method and device of a server CPLD supporting PFR.
Background
PFR is short for Platform Firmware development, platform Firmware flexibility.
CPLD is a Complex Programmable logic device for short of Complex Programmable logic device.
The general calculation formula of the dynamic power consumption can be referred to as follows: p = V 2 * F C. The value of P represents the consumed power, V represents the voltage, F represents the frequency, and C represents the load capacitance; faster F means greater power consumption. The general servers are mostly operated continuously all the year round, and are a very considerable number in energy consumption.
The modules of the CPLD of the general server use the same clock source to drive the internal logic gate. Since the clock source provided to each module is fixed, the IC consumption will be in a fixed range of values in terms of energy consumption. The higher the frequency, the higher the power consumed.
Therefore, it is very necessary to provide a power saving method and apparatus for a server CPLD supporting PFR to overcome the above-mentioned drawbacks in the prior art.
Disclosure of Invention
Aiming at the defect that each module of the CPLD in the prior art uses the same clock source to push internal logic, the invention provides a power-saving method and a power-saving device of a server CPLD supporting PFR, so as to solve the technical problem.
In a first aspect, the present invention provides a power saving method for a server CPLD supporting PFR, including the following steps:
s1, a clock phase-locked loop module generates clocks with different frequency grades according to a clock source;
s2, the clock management module distributes clocks with corresponding frequency grades to the functional modules of the CPLD according to the on-off state of the system; the functional modules of the CPLD comprise a power-on module, a power-off module, a monitoring module and an authentication module;
and S3, adopting the distributed clocks with corresponding frequency grades by each functional module of the CPLD, and completing authentication before system power-on, power-off and monitoring each working process according to the system power-on and power-off state in a matching manner.
Further, the step S1 specifically includes the following steps:
s11, a clock phase-locked loop module takes a clock source as input;
s12, a clock phase-locked loop module generates a first frequency clock, a second frequency clock and a third frequency clock; the frequency of the second frequency clock is greater than that of the third frequency clock and less than that of the first frequency clock;
and S13, the clock phase-locked loop module outputs the first frequency clock, the second frequency clock and the third frequency clock and provides the output to the clock management module.
Further, the step S2 specifically includes the following steps:
s21, a clock management module acquires a system on-off state;
when the system is not started, step S22 is entered;
when the system state is started, step S23 is entered;
s22, the clock management module distributes a first frequency clock for the authentication module, distributes a second frequency clock for the power-on module, distributes a third frequency clock for the power-off module, and the step S3 is carried out;
and S23, the clock management module distributes a second frequency clock to the lower power module, distributes a third frequency clock to the authentication module and distributes a third frequency clock to the power-on module. Before starting up, the authentication is carried out, and at the moment, the authentication module distributes a high-frequency clock, so that the authentication time can be shortened.
Further, the monitoring module comprises an I2C slave engine module, an LED control module, a power supply and a CPU thermal control module;
step S21 is preceded by the steps of:
and S21', the clock management module distributes a second frequency clock to the I2C slave engine module, distributes a third frequency clock to the LED control module and distributes a third frequency clock to the power supply and CPU thermal control module.
Further, the authentication module comprises an SPI control module and a digital signature authentication module.
Further, the step S3 specifically includes the following steps:
s31, the I2C slave engine module of the CPLD adopts a second frequency clock, the LED control module adopts a third frequency clock, and the power supply and CPU thermal control module adopt the third frequency clock to carry out system monitoring;
s32, when the system is not started up in the on-off state, reading data in the FLASH by an SPI control module of the CPLD by adopting a first frequency clock;
s33, the digital signature authentication module of the CPLD adopts a first frequency clock to carry out firmware validity authentication according to the FLASH data read by the SPI control module;
if the firmware authentication is passed, the process proceeds to step S34;
when the firmware authentication is not passed, the computer is not started and is finished;
s34, a power-on module of the CPLD adopts a second frequency clock to start and power on;
and S35, the power-on module, the SPI control module and the digital signature authentication module of the CPLD adopt a third frequency clock to enter dormancy waiting, and the power-off module of the CPLD adopts a second frequency clock to carry out power-off waiting.
In a second aspect, the present invention provides a power saving device for a server CPLD supporting PFR, including:
the clock phase-locked loop module generates clocks with different frequency grades according to a clock source;
the clock management module distributes a clock with a corresponding frequency grade to the CPLD functional module according to the system on-off state;
the CPLD comprises a CPLD functional module, a clock using module, a power-on module, a power-off module, a monitoring module and an authentication module; the authentication module comprises an SPI control module and a digital signature authentication module; the monitoring module comprises an I2C slave engine module, an LED control module, a power supply and a CPU thermal control module; the CPLD functional module adopts the distributed clocks with corresponding frequency grades, and completes the authentication before the system is powered on, the power off and the monitoring of each working process according to the on-off state of the system.
Further, the clock phase-locked loop module includes:
the input clock unit is used for setting the clock phase-locked loop module to take the clock source as input;
the multi-frequency clock generating unit is used for setting the clock phase-locked loop module to generate a first frequency clock, a second frequency clock and a third frequency clock; the frequency of the second frequency clock is greater than that of the third frequency clock and less than that of the first frequency clock;
the multi-frequency clock providing unit is used for outputting the first frequency clock, the second frequency clock and the third frequency clock and providing the output to the clock management module.
Further, the clock management module includes:
the monitoring clock unit is used for distributing a second frequency clock for the I2C slave engine module, distributing a third frequency clock for the LED control module and distributing a third frequency clock for the power supply and CPU thermal control module;
the system comprises a startup and shutdown state acquisition unit, a power-on and shutdown state acquisition unit and a power-off and shutdown state acquisition unit, wherein the startup and shutdown state acquisition unit is used for acquiring a system startup and shutdown state;
the authentication and starting clock unit is used for distributing a first frequency clock to the authentication module, distributing a second frequency clock to the power-on module and distributing a third frequency clock to the power-off module when the system is not started;
and the shutdown clock unit is used for distributing a second frequency clock for the power-down module, a third frequency clock for the authentication module and a third frequency clock for the power-up module when the system is in a started state.
Further, the clock using module of the CPLD functional module includes:
the monitoring clock using unit is used for setting an I2C slave engine module of the CPLD to adopt a second frequency clock, the LED control module adopts a third frequency clock, and the CPU thermal control module adopts the third frequency clock to carry out system monitoring;
the SPI control module clock using unit is used for reading data in the FLASH by adopting a first frequency clock when the system power-on and power-off state is obtained to be the non-power-on state;
the digital signature authentication module clock using unit is used for carrying out firmware validity authentication by adopting a first frequency clock according to the FLASH data read by the SPI control module;
the power-on module clock using unit is used for starting and powering on the CPLD by adopting a second frequency clock when the firmware authentication passes;
and the power-off clock preparation unit is used for setting the power-on module, the SPI control module and the digital signature authentication module of the CPLD to enter dormancy waiting by adopting a third frequency clock, and setting the power-off module of the CPLD to perform power-off waiting by adopting a second frequency clock.
The beneficial effect of the invention is that,
according to the power saving method and device for the server CPLD supporting the PFR, provided by the invention, the clocks with different frequency grades are determined and selected according to the system state, the clock with the frequency grade required by each module of the CPLD is determined, the power saving effect is achieved, and the defects that the traditional server CPLD works by adopting a single clock and has high power consumption are overcome.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Therefore, compared with the prior art, the invention has prominent substantive features and remarkable progress, and the beneficial effects of the implementation are also obvious.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a first schematic flow chart of the method of the present invention;
FIG. 2 is a second schematic flow chart of the method of the present invention;
FIG. 3 is a schematic diagram of the system of the present invention;
fig. 4 is a schematic diagram of the operating frequencies of the modules of the CPLD according to the embodiment of the present invention;
FIG. 5 is a comparison diagram of power consumption before and after the CPLD adopts the present invention in the embodiment;
in the figure, 1-a multi-frequency clock generation unit; 1.1-input clock unit; 1.2-a multi-frequency clock generation unit; 1.3-a multi-frequency clock providing unit; 2-a clock management module; 2.1-monitoring the clock unit; 2.2-a power on/off state acquisition unit; 2.3-authentication and start-up clock unit; 2.4-a shutdown clock unit; a clock using module of the 3-CPLD functional module; 3.1-monitoring the clock using unit; 3.2-SPI control module clock using unit; 3.3-digital signature authentication module clock using unit; 3.4-power up module clock using unit; 3.5-Power-Down clock preparation Unit.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1:
as shown in fig. 1, the present invention provides a power saving method for a server CPLD supporting PFR, including the following steps:
s1, a clock phase-locked loop module generates clocks with different frequency grades according to a clock source;
s2, distributing a clock with a corresponding frequency grade for the functional module of the CPLD by the clock management module according to the system on-off state; the functional modules of the CPLD comprise a power-on module, a power-off module, a monitoring module and an authentication module;
and S3, adopting the distributed clocks with corresponding frequency grades by each functional module of the CPLD, and completing authentication before system power-on, power-off and monitoring each working process according to the system power-on and power-off state in a matching manner.
Example 2:
as shown in fig. 2, the present invention provides a power saving method for a server CPLD supporting PFR, including the following steps:
s1, a clock phase-locked loop module generates clocks with different frequency grades according to a clock source; the method comprises the following specific steps:
s11, a clock phase-locked loop module takes a clock source as input;
s12, a clock phase-locked loop module generates a first frequency clock, a second frequency clock and a third frequency clock; the frequency of the second frequency clock is greater than that of the third frequency clock and less than that of the first frequency clock;
s13, the clock phase-locked loop module outputs the first frequency clock, the second frequency clock and the third frequency clock and provides the first frequency clock, the second frequency clock and the third frequency clock to the clock management module;
s2, the clock management module distributes clocks with corresponding frequency grades to the functional modules of the CPLD according to the on-off state of the system; the functional modules of the CPLD comprise a power-on module, a power-off module, a monitoring module and an authentication module; the monitoring module comprises an I2C slave engine module, an LED control module, a power supply and a CPU heat control module; the method comprises the following specific steps:
s21', the clock management module distributes a second frequency clock to the I2C slave engine module, distributes a third frequency clock to the LED control module and distributes a third frequency clock to the power supply and CPU thermal control module;
s21, a clock management module acquires a system on-off state;
when the system is not started, step S22 is entered;
when the system state is started, step S23 is entered;
s22, the clock management module distributes a first frequency clock for the authentication module, distributes a second frequency clock for the power-on module, distributes a third frequency clock for the power-off module, and the step S3 is carried out;
s23, the clock management module distributes a second frequency clock for the lower power module, distributes a third frequency clock for the authentication module and distributes a third frequency clock for the power-on module;
s3, adopting distributed clocks with corresponding frequency grades by each functional module of the CPLD, and completing authentication before system power-on, power-off and monitoring each working process according to the system power-on and power-off state; the method comprises the following specific steps:
s31, the I2C slave engine module of the CPLD adopts a second frequency clock, the LED control module adopts a third frequency clock, and the power supply and CPU thermal control module adopt the third frequency clock for system monitoring;
s32, when the system is not started up in the on-off state, reading data in the FLASH by an SPI control module of the CPLD by adopting a first frequency clock;
s33, the digital signature authentication module of the CPLD adopts a first frequency clock to authenticate the validity of the firmware according to the FLASH data read by the SPI control module;
if the firmware authentication is passed, the process proceeds to step S34;
when the firmware authentication is not passed, the computer is not started and is finished;
s34, a power-on module of the CPLD adopts a second frequency clock to start and power on;
and S35, the power-on module, the SPI control module and the digital signature authentication module of the CPLD adopt a third frequency clock to enter dormancy waiting, and the power-off module of the CPLD adopts a second frequency clock to carry out power-off waiting.
In some embodiments, the digital signature authentication module performs digital signature authentication by using an ECDSA256 module and an SHA256 module, the ECDSA256 module uses a digital signature algorithm, and the SHA256 module uses a secure hash algorithm;
after the first frequency clock is 50MHz, the second frequency clock is 2MHz, and the third frequency clock is 100KHz, and the clocks distributed to the functional modules of the CPLD are distributed with the clocks of the corresponding frequency classes in step S2, the clocks distributed to the modules are as shown in fig. 4;
by comparing and measuring the power consumption of the CPLD, before and after the functional modules of the CPLD of the present invention are allocated with clocks of different frequencies, the overall power consumption of the CPLD is not greatly different from that of the CPLD shown in fig. 5 on the premise that the functional modules of the CPLD are the same, but after the system is turned on, the power consumption of the CPLD of the present invention is reduced from 397.03mW to 1.15mW, thereby achieving a significant power consumption reduction and achieving a power saving effect.
Example 3:
as shown in fig. 3, the present invention provides a power saving device for a server CPLD supporting PFR, including:
the clock phase-locked loop module 1 generates clocks with different frequency grades according to a clock source; the clock phase-locked loop module 1 includes:
the input clock unit 1.1 is used for setting a clock phase-locked loop module to take a clock source as input;
the multi-frequency clock generating unit 1.2 is used for setting a clock phase-locked loop module to generate a first frequency clock, a second frequency clock and a third frequency clock; the frequency of the second frequency clock is greater than that of the third frequency clock and less than that of the first frequency clock;
a multi-frequency clock providing unit 1.3, configured to output the first frequency clock, the second frequency clock, and the third frequency clock, and provide the output to the clock management module;
the clock management module 2 is used for distributing clocks with corresponding frequency grades to the CPLD functional module according to the system on-off state; the clock management module 2 includes:
the monitoring clock unit 2.1 is used for distributing a second frequency clock for the I2C slave engine module, distributing a third frequency clock for the LED control module and distributing a third frequency clock for the power supply and CPU thermal control module;
the on-off state obtaining unit 2.2 is used for obtaining the on-off state of the system;
the authentication and startup clock unit 2.3 is used for distributing a first frequency clock to the authentication module, distributing a second frequency clock to the power-on module and distributing a third frequency clock to the power-off module when the system is not started;
the shutdown clock unit 2.4 is used for distributing a second frequency clock to the power-down module, distributing a third frequency clock to the authentication module and distributing a third frequency clock to the power-on module when the system is in a started state;
the CPLD functional module clock using module 3 comprises a power-on module, a power-off module, a monitoring module and an authentication module; the authentication module comprises an SPI control module and a digital signature authentication module; the monitoring module comprises an I2C slave engine module, an LED control module, a power supply and a CPU thermal control module; the CPLD functional module adopts the distributed clocks with corresponding frequency grades, and completes the authentication before the system is powered on, the power off and the monitoring of each working process according to the system on-off state; the clock using module 3 of the CPLD functional module includes:
a monitoring clock using unit 3.1, which is used for setting an I2C slave engine module of the CPLD to adopt a second frequency clock, an LED control module adopts a third frequency clock, and a power supply and CPU thermal control module adopt a third frequency clock for system monitoring;
the SPI control module clock using unit 3.2 is used for reading data in the FLASH by adopting a first frequency clock when the system power-on and power-off state is obtained to be the non-power-on state;
the digital signature authentication module clock using unit 3.3 is used for performing firmware validity authentication by adopting a first frequency clock according to the data in the FLASH read by the SPI control module;
the power-on module clock using unit 3.4 is used for starting and powering on the CPLD by adopting a second frequency clock when the firmware authentication passes;
and the power-off clock preparation unit 3.5 is used for setting the power-on module, the SPI control module and the digital signature authentication module of the CPLD to enter dormancy waiting by adopting a third frequency clock, and setting the power-off module of the CPLD to carry out power-off waiting by adopting a second frequency clock.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (2)
1. A power saving method for a server CPLD supporting PFR is characterized by comprising the following steps:
s1, a clock phase-locked loop module generates clocks with different frequency grades according to a clock source; the step S1 comprises the following specific steps:
s11, a clock phase-locked loop module takes a clock source as input;
s12, a clock phase-locked loop module generates a first frequency clock, a second frequency clock and a third frequency clock; the frequency of the second frequency clock is greater than that of the third frequency clock and less than that of the first frequency clock;
s13, the clock phase-locked loop module outputs the first frequency clock, the second frequency clock and the third frequency clock and provides the first frequency clock, the second frequency clock and the third frequency clock to the clock management module;
s2, distributing a clock with a corresponding frequency grade for the functional module of the CPLD by the clock management module according to the system on-off state; the functional modules of the CPLD comprise a power-on module, a power-off module, a monitoring module and an authentication module; the monitoring module comprises an I2C slave engine module, an LED control module, a power supply and a CPU heat control module; the authentication module comprises an SPI control module and a digital signature authentication module; the step S2 comprises the following specific steps:
s21', the clock management module distributes a second frequency clock to the I2C slave engine module, distributes a third frequency clock to the LED control module and distributes a third frequency clock to the power supply and CPU thermal control module;
s21, a clock management module acquires a system on-off state;
when the system is not started, step S22 is entered;
when the system state is started, step S23 is entered;
s22, the clock management module distributes a first frequency clock for the authentication module, distributes a second frequency clock for the power-on module, distributes a third frequency clock for the power-off module and enters the step S3;
s23, the clock management module distributes a second frequency clock for the lower power module, distributes a third frequency clock for the authentication module and distributes a third frequency clock for the power-on module;
s3, adopting distributed clocks with corresponding frequency grades by each functional module of the CPLD, and completing authentication before system power-on, power-off and monitoring each working process according to the system power-on and power-off state; the step S3 comprises the following steps:
s31, the I2C slave engine module of the CPLD adopts a second frequency clock, the LED control module adopts a third frequency clock, and the power supply and CPU thermal control module adopt the third frequency clock for system monitoring;
s32, when the system is not started up in the on-off state, reading data in the FLASH by an SPI control module of the CPLD by adopting a first frequency clock;
s33, the digital signature authentication module of the CPLD adopts a first frequency clock to authenticate the validity of the firmware according to the FLASH data read by the SPI control module;
if the firmware authentication is passed, the process proceeds to step S34;
when the firmware authentication is not passed, the terminal is not started and the process is finished;
s34, a power-on module of the CPLD adopts a second frequency clock to start and power on;
and S35, the power-on module, the SPI control module and the digital signature authentication module of the CPLD adopt a third frequency clock to enter dormancy waiting, and the power-off module of the CPLD adopts a second frequency clock to carry out power-off waiting.
2. A power saving device for a server CPLD supporting PFR, comprising:
the clock phase-locked loop module (1) generates clocks with different frequency grades according to a clock source; the clock phase-locked loop module (1) comprises:
the input clock unit (1.1) is used for setting a clock phase-locked loop module to take a clock source as input;
the multi-frequency clock generating unit (1.2) is used for setting a clock phase-locked loop module to generate a first frequency clock, a second frequency clock and a third frequency clock; the frequency of the second frequency clock is greater than that of the third frequency clock and less than that of the first frequency clock;
the multi-frequency clock providing unit (1.3) is used for outputting the first frequency clock, the second frequency clock and the third frequency clock and providing the output to the clock management module;
the clock management module (2) distributes a clock with a corresponding frequency grade to the CPLD functional module according to the system on-off state; the clock management module (2) comprises:
the monitoring clock unit (2.1) is used for distributing a second frequency clock for the I2C slave engine module, distributing a third frequency clock for the LED control module and distributing a third frequency clock for the power supply and CPU thermal control module;
the on-off state acquisition unit (2.2) is used for acquiring the on-off state of the system;
the authentication and startup clock unit (2.3) is used for distributing a first frequency clock for the authentication module, a second frequency clock for the power-on module and a third frequency clock for the power-off module when the system is not started;
the shutdown clock unit (2.4) is used for distributing a second frequency clock for the power-down module, a third frequency clock for the authentication module and a third frequency clock for the power-on module when the system is in a started state;
the CPLD comprises a CPLD functional module clock using module (3), wherein the CPLD functional module comprises a power-on module, a power-off module, a monitoring module and an authentication module; the authentication module comprises an SPI control module and a digital signature authentication module; the monitoring module comprises an I2C slave engine module, an LED control module, a power supply and a CPU thermal control module; the CPLD functional module adopts the distributed clocks with corresponding frequency grades, and completes the authentication before the system is powered on, the power off and the monitoring of each working process according to the on-off state of the system; the CPLD functional module clock using module (3) comprises:
the monitoring clock using unit (3.1) is used for setting an I2C slave engine module of the CPLD to adopt a second frequency clock, the LED control module adopts a third frequency clock, and the power supply and CPU thermal control module adopt the third frequency clock to carry out system monitoring;
the SPI control module clock using unit (3.2) is used for reading the data in the FLASH by adopting a first frequency clock when the system power-on and power-off state is obtained to be the non-power-on state;
the digital signature authentication module clock using unit (3.3) is used for carrying out firmware validity authentication by adopting a first frequency clock according to the data in the FLASH read by the SPI control module;
the power-on module clock using unit (3.4) is used for starting and powering on the CPLD by adopting a second frequency clock when the firmware authentication is passed;
and the power-off clock preparation unit (3.5) is used for setting a power-on module, an SPI control module and a digital signature authentication module of the CPLD to enter dormancy waiting by adopting a third frequency clock, and setting a power-off module of the CPLD to carry out power-off waiting by adopting a second frequency clock.
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| CN113204804B (en) * | 2021-04-25 | 2022-03-22 | 山东英信计算机技术有限公司 | Security module, server mainboard and server |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101246388A (en) * | 2007-02-14 | 2008-08-20 | 盛群半导体股份有限公司 | Microcontroller and its power-saving method |
| CN101782791A (en) * | 2010-01-29 | 2010-07-21 | 杭州电子科技大学 | Clock/reset and configuration controller hardcore in communication processor chip |
| CN110399034A (en) * | 2019-07-04 | 2019-11-01 | 福州瑞芯微电子股份有限公司 | A kind of power consumption optimization method and terminal of SoC system |
-
2020
- 2020-09-08 CN CN202010937152.XA patent/CN111966205B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101246388A (en) * | 2007-02-14 | 2008-08-20 | 盛群半导体股份有限公司 | Microcontroller and its power-saving method |
| CN101782791A (en) * | 2010-01-29 | 2010-07-21 | 杭州电子科技大学 | Clock/reset and configuration controller hardcore in communication processor chip |
| CN110399034A (en) * | 2019-07-04 | 2019-11-01 | 福州瑞芯微电子股份有限公司 | A kind of power consumption optimization method and terminal of SoC system |
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