CN104113304B - Two-phase mutually non-overlap clock circuit and method thereof - Google Patents
Two-phase mutually non-overlap clock circuit and method thereof Download PDFInfo
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- CN104113304B CN104113304B CN201410291168.2A CN201410291168A CN104113304B CN 104113304 B CN104113304 B CN 104113304B CN 201410291168 A CN201410291168 A CN 201410291168A CN 104113304 B CN104113304 B CN 104113304B
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Abstract
Disclosed in the invention is a two-phase mutually non-overlap clock circuit comprising an input buffer unit, a first NOT gate, a first time delay unit, a second time delay unit, a first AND gate, a second AND gate, a first output buffer unit, and a second output buffer unit. The input terminal of the first NOT gate is connected with the output terminal of the input buffer unit; the input terminal of the first time delay unit is connected with the output terminal of the first NOT gate; the input terminal of the second time delay unit is connected with the output terminal of the first time delay unit; the input terminal of the first AND gate is respectively connected with the output terminal of the input buffer unit and the output terminal of the first time delay unit; the input terminal of the second AND gate is respectively connected with the output terminal of the first NOT gate and the output terminal of the second time delay unit; the input terminal of the first output buffer unit is connected with the output terminal of the first AND gate; and the input terminal of the second output buffer unit is connected with the output terminal of the second AND gate. According to the invention, the clock time delay is determined precisely by the way of capacitor introduction into the circuit; the precision and the stability are high; the non-overlap degree of the generated two-phase mutually non-overlap clock signal is good; and the integrating degree of the simulation result and the chip is high.
Description
Technical field
The present invention relates to technical field of circuit design, be specifically related to biphase non-overlapping clock circuit and method thereof.
Background technology
Biphase non-overlapping clock circuit of the prior art, the principle mainly by inverter device time delay produces biphase non-overlapping clock signal.But under the CMOS technology of standard, such device time delay is the most accurate, the simulation result of its device time delay and measured value there may be the biggest deviation, this would potentially result in different chip chamber not overlap clock inconsistent, the non-overlapping clock possibly even causing circuit to produce exists a certain degree of overlapping, thus affects the actual performance of switched-capacitor circuit.
Biphase non-overlapping clock shown in Fig. 1 was published at " A Clock by the Jing Cao of University of California in 1999
Generator and Output Buffer for 12bit, 75MS/s, 3.3V CMOS ADC with SFDR 85dB " in a literary composition.
With reference to Fig. 1, illustrate the operation principle of existing biphase non-overlapping clock circuit.The clock signal of input is received by input buffer 1 ', for inputting input clock signal buffering to this biphase non-overlapping clock circuit, and produce a non-intersect clock in road with the output signal after two not gate device time delays by logic "and" operation (first and door 5 ')；First not gate 2 ', for by clock inversion, its output clock will produce the non-intersect clock in another road with the output signal after two not gate devices (the second not gate 3 ', the 3rd not gate 4 ') time delay by logic "and" operation (second and door 6 ')；First output buffer cell 7 ', its effect is by the first signal damping output produced with door 5 ', forms the CLK1 of biphase non-overlapping clock；Second output buffer cell 8 ', its effect is by the second signal damping output produced with door 6 ', forms the CLK2 of biphase non-overlapping clock.
As in figure 2 it is shown, the clock signal that biphase non-overlapping clock circuit of the prior art produces can exist a certain degree of overlapping.
Summary of the invention
It is an object of the invention to provide a kind of biphase non-overlapping clock circuit and method thereof, clock delay is determined accurately by the way of introducing delay capacitor in circuit, precision is high, degree of stability is good, the not overlapping degree of the biphase non-overlapping clock signal produced is good, and simulation result is high with the measured value compatible degree of chip.
In order to achieve the above object, the present invention is achieved through the following technical solutions: a kind of biphase non-overlapping clock circuit, is characterized in, comprises:
Accept the input buffer cell of input clock signal；
First not gate, its input is connected with the outfan of described input buffer cell, for clock signal is anti-phase；
First delay unit, its input is connected with the outfan of described first not gate, is used for producing regular time delay；
Second delay unit, its input is connected with the outfan of described first delay unit, is used for producing regular time delay；
First and door, its input outfan with the outfan of described input buffer cell and described first delay unit respectively is connected, and is used for carrying out logic and operation；
Second and door, its input outfan with the outfan of described first not gate and described second delay unit respectively is connected, and is used for carrying out logic and operation；
First output buffer cell, its input is connected with the outfan of door with described first, the wherein phase in the biphase non-overlapping clock of Buffer output；
Second output buffer cell, its input is connected with the outfan of door with described second, another phase in the biphase non-overlapping clock of Buffer output.
The first described delay unit comprises the second not gate and the first delay capacitor；
The input of the second described not gate and the outfan of the first not gate connect；
The outfan of the second described not gate is connected with input and first delay capacitor of door with first respectively.
The second described delay unit comprises the 3rd not gate and the second delay capacitor；
The input of the 3rd described not gate and the outfan of the second not gate connect；
The outfan of the 3rd described not gate is connected with input and first delay capacitor of door with second respectively.
A kind of biphase non-overlapping clock circuit generates method, is characterized in, comprises the steps of
Input buffer cell receives clock signal, the input of output to the first not gate and first and the input of door；
After first non-goalkeeper's clock signal is anti-phase output to the input of the first delay unit and second with the input of door；
First delay unit export after clock signal is fixed time delay to first with the input of door and the input of the second delay unit；
Second delay unit exports the input to second Yu door after clock signal is fixed time delay；
First clock signal exported with goalkeeper's input buffer cell, the clock signal of the first delay unit output export the input to the first output buffer cell after carrying out logic and operation；
Second clock signal exported with goalkeeper's the first not gate, the clock signal of the second delay unit output export the input to the second output buffer cell after carrying out logic and operation；
First output buffer unit buffers exports the wherein phase in biphase non-overlapping clock；
Second output buffer unit buffers exports another phase in biphase non-overlapping clock.
The biphase non-overlapping clock circuit of the present invention and method thereof compared with prior art have the advantage that by the way of introducing delay capacitor in circuit and determine clock delay accurately, and precision is high, degree of stability is good；This circuit can be the most only by adjusting the time that the capacitance of delay capacitor cannot not change overlappingly, and the not overlapping degree of the biphase non-overlapping clock signal of generation is good, and simulation result is high with the measured value compatible degree of chip.
Accompanying drawing explanation
Fig. 1 is the block diagram of biphase non-overlapping clock circuit in prior art.
Fig. 2 is the non-overlapping clock signal schematic diagram that in prior art, biphase non-overlapping clock circuit generates.
Fig. 3 is the block diagram of a kind of biphase non-overlapping clock circuit of the present invention.
Fig. 4 is embodiment design sketch.
Detailed description of the invention
Below in conjunction with accompanying drawing, by describing a preferably specific embodiment in detail, the present invention is further elaborated.
As it is shown on figure 3, a kind of biphase non-overlapping clock circuit, comprise: accept the input buffer cell 1 of input clock signal；First not gate 2, its input is connected with the outfan of described input buffer cell 1, for clock signal is anti-phase；First delay unit 3, its input is connected with the outfan of described first not gate 2, is used for producing regular time delay；Second delay unit 4, its input is connected with the outfan of described first delay unit 3, is used for producing regular time delay；First with door 5, its input outfan with the outfan of described input buffer cell 1 and described first delay unit 3 respectively is connected, and is used for carrying out logic and operation；Second with door 6, its input outfan with the outfan of described first not gate 2 and described second delay unit 4 respectively is connected, and is used for carrying out logic and operation；First output buffer cell 7, its input is connected with the outfan of described first with door 5, the wherein phase in the biphase non-overlapping clock of Buffer output；Second output buffer cell 8, its input is connected with the outfan of described second with door 6, another phase in the biphase non-overlapping clock of Buffer output.
First delay unit 3 comprises the second not gate 31 and the first delay capacitor 32；The input of the second described not gate 31 and the outfan of the first not gate 2 connect；The outfan of the second described not gate 31 is connected with input and first delay capacitor 32 of door 5 with first respectively.Second not gate 31, for carrying out anti-phase to input signal, and at the limited inversion signal of its output node output driving current；First delay capacitor 32, produces, for the output node at the second not gate 31, the signal that time delay interval is linear with delay capacitor.
Second delay unit 4 comprises the 3rd not gate 41 and the second delay capacitor 42；The input of the 3rd described not gate 41 and the outfan of the second not gate 31 connect；The outfan of the 3rd described not gate 41 is connected with input and first delay capacitor 32 of door 6 with second respectively.3rd not gate 41, for carrying out anti-phase to input signal, and at the limited inversion signal of its output node output driving current；Second delay capacitor 42, produces, for the output node at the 3rd not gate 41, the signal that time delay interval is linear with delay capacitor.Fig. 4 illustrates the present invention and be can achieve the effect that.
A kind of biphase non-overlapping clock circuit generates method, comprises the steps of
Input buffer cell 1 receives clock signal, the input of output to the first not gate 2 and first and the input of door 5；
First not gate 2 by the input of output after anti-phase for clock signal to the first delay unit 3 and second with the input of door 6；
First delay unit 3 export after clock signal is fixed time delay to first with the input of door 5 and the input of the second delay unit 4；
Second delay unit 4 exports the input to second Yu door 6 after clock signal is fixed time delay；
The clock signal that first clock signal exported by input buffer cell 1 with door 5, the first delay unit 3 export exports the input to the first output buffer cell 7 after carrying out logic and operation；
The clock signal that second clock signal exported by first not gate 2 with door 6, the second delay unit 4 export exports the input to the second output buffer cell 8 after carrying out logic and operation；
A wherein phase in the first output biphase non-overlapping clock of buffer cell 7 Buffer output；
Another phase in the second output biphase non-overlapping clock of buffer cell 8 Buffer output.
Although present disclosure has been made to be discussed in detail by above preferred embodiment, but it should be appreciated that the description above is not considered as limitation of the present invention.After those skilled in the art have read foregoing, multiple amendment and replacement for the present invention all will be apparent from.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (3)
1. a biphase non-overlapping clock circuit, it is characterised in that comprise:
Accept the input buffer cell (1) of input clock signal；
First not gate (2), its input is connected with the outfan of described input buffer cell (1), for clock signal is anti-phase；
First delay unit (3), described the first delay unit (3) comprises the second not gate (31) and the first delay capacitor (32), the input of described the second not gate (31) and the outfan of the first not gate (2) connect, the outfan of described the second not gate (31) and the first delay capacitor (32) connect, and described the first delay unit (3) is used for producing regular time delay；
Second delay unit (4), its input is connected with the outfan of described first delay unit (3), is used for producing regular time delay；
First with door (5), its input outfan with the outfan of described input buffer cell (1) and described second not gate (31) respectively is connected, and is used for carrying out logic and operation；
Second with door (6), its input is connected with the outfan of described first not gate (2) and the outfan of described second delay unit (4) respectively, is used for carrying out logic and operation；
First output buffer cell (7), its input is connected with the outfan of described first with door (5), the wherein phase in the biphase non-overlapping clock of Buffer output；
Second output buffer cell (8), its input is connected with the outfan of described second with door (6), another phase in the biphase non-overlapping clock of Buffer output.
Biphase non-overlapping clock circuit the most as claimed in claim 1, it is characterised in that described the second delay unit (4) comprises the 3rd not gate (41) and the second delay capacitor (42)；
The input of the 3rd described not gate (41) and the outfan of the second not gate (31) connect；
The outfan of the 3rd described not gate (41) is connected with input and first delay capacitor (32) of door (6) with second respectively.
3. a biphase non-overlapping clock circuit generates method, it is characterised in that comprise the steps of
Input buffer cell (1) receives clock signal, the input of output to the first not gate (2) and first and the input of door (5)；
First not gate (2) by the input of output after anti-phase for clock signal to the first delay unit (3) and second with the input of door (6)；
First delay unit (3) export after clock signal is fixed time delay to first with the input of door (5) and the input of the second delay unit (4)；
Second delay unit (4) exports the input to second Yu door (6) after clock signal is fixed time delay；
The clock signal that first clock signal exported by input buffer cell (1) with door (5), the first delay unit (3) export exports the input to the first output buffer cell (7) after carrying out logic and operation；
The clock signal that second clock signal exported by first not gate (2) with door (6), the second delay unit (4) export exports the input to the second output buffer cell (8) after carrying out logic and operation；
A wherein phase in the first output biphase non-overlapping clock of buffer cell (7) Buffer output；
Another phase in the second output biphase non-overlapping clock of buffer cell (8) Buffer output.
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| CN201410291168.2A CN104113304B (en) | 2014-06-26 | 2014-06-26 | Two-phase mutually non-overlap clock circuit and method thereof |
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| CN106130540B (en) * | 2016-07-05 | 2019-04-26 | 中国科学院上海微系统与信息技术研究所 | Broad-adjustable disjoint signals circuit and system |
| CN109804426B (en) * | 2017-08-16 | 2021-04-27 | 深圳市汇顶科技股份有限公司 | Image sensing circuit and image depth sensing system |
| CN108566180A (en) * | 2018-05-04 | 2018-09-21 | 中国科学技术大学 | A kind of single delay chain circuit generating two-way delay |
| CN110768674A (en) * | 2019-10-29 | 2020-02-07 | 湖南国科微电子股份有限公司 | Analog-to-digital conversion device, analog-to-digital conversion equipment and analog-to-digital conversion method |
| CN111562808A (en) * | 2020-06-22 | 2020-08-21 | 深圳比特微电子科技有限公司 | Clock circuit system, computing chip, computing board and digital currency mining machine |
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| US5867453A (en) * | 1998-02-06 | 1999-02-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-setup non-overlap clock generator |
| CN102522994A (en) * | 2011-12-07 | 2012-06-27 | 清华大学 | Clock generation circuit used in analog-to-digital converter (ADC) with high speed and high precision |
| CN103166605A (en) * | 2013-01-25 | 2013-06-19 | 湘潭芯力特电子科技有限公司 | Multiphase non-overlapping clock circuit |
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| US5867453A (en) * | 1998-02-06 | 1999-02-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-setup non-overlap clock generator |
| CN102522994A (en) * | 2011-12-07 | 2012-06-27 | 清华大学 | Clock generation circuit used in analog-to-digital converter (ADC) with high speed and high precision |
| CN103166605A (en) * | 2013-01-25 | 2013-06-19 | 湘潭芯力特电子科技有限公司 | Multiphase non-overlapping clock circuit |
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| 《基于流水型ADC的真随机数发生器的设计与实现》;张勇;《中国优秀硕士学位论文全文数据库（电子期刊）》;20111215;图3-19 * |
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