CN104579298B - Flip-flop and semiconductor circuit - Google Patents

Flip-flop and semiconductor circuit Download PDF

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CN104579298B
CN104579298B CN201410548796.4A CN201410548796A CN104579298B CN 104579298 B CN104579298 B CN 104579298B CN 201410548796 A CN201410548796 A CN 201410548796A CN 104579298 B CN104579298 B CN 104579298B
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transistor
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CN104579298A (en
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拉赫·辛哈
金珉修
金正熙
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Samsung Electronics Co Ltd
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/3562Bistable circuits of the primary-secondary type
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037Bistable circuits
    • H03K3/0375Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037Bistable circuits
    • H03K3/0372Bistable circuits of the primary-secondary type

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Abstract

提供了一种触发器和半导体电路。示例实施例公开了一种触发器,该触发器包括:第一反相器,被构造为对第一数据进行反相;第一晶体管和第二晶体管,彼此串联连接且被构造为分别接收反相的第一数据和第一时钟;第一门,被构造为对第一数据和第一时钟执行逻辑运算;第三晶体管,被构造为接收所述逻辑运算的输出。第二晶体管和第三晶体管连接到第一节点。

Figure 201410548796

A flip-flop and semiconductor circuit are provided. Example embodiments disclose a flip-flop comprising: a first inverter configured to invert first data; a first transistor and a second transistor connected in series with each other and configured to receive the inverters, respectively. a first data and a first clock of a phase; a first gate configured to perform a logic operation on the first data and the first clock; and a third transistor configured to receive an output of the logic operation. The second transistor and the third transistor are connected to the first node.

Figure 201410548796

Description

触发器和半导体电路flip-flops and semiconductor circuits

本申请基于和请求2013年10月16日提交到韩国知识产权局的第10-2013-0123398号韩国专利申请的优先权,所述申请的公开内容通过引用整体包含于此。This application is based on and claims priority to Korean Patent Application No. 10-2013-0123398 filed with the Korean Intellectual Property Office on October 16, 2013, the disclosure of which is incorporated herein by reference in its entirety.

技术领域technical field

本发明构思涉及一种半导体电路和半导体系统。The inventive concept relates to a semiconductor circuit and a semiconductor system.

背景技术Background technique

作为半导体装置之一,触发器进行操作以响应于时钟信号而存储输入数据,并顺序地传送存储的数据。多个触犯器可被用于传送数据。As one of the semiconductor devices, flip-flops operate to store input data in response to a clock signal, and sequentially transfer the stored data. Multiple triggers can be used to transmit data.

另一方面,随着高速电子产品的趋势,提供给触发器的时钟信号的速度已逐渐增加。为了在这种环境下可靠地操作多个触发器,不管高速时钟信号如何,都不需要在触发器的操作期间发生定时失效。On the other hand, with the trend of high-speed electronics, the speed of clock signals supplied to flip-flops has gradually increased. In order to operate multiple flip-flops reliably in this environment, timing failures need not occur during the operation of the flip-flops regardless of the high-speed clock signal.

发明内容SUMMARY OF THE INVENTION

本发明构思提供一种以小的尺寸对称地形成采样窗口并因此提高产品可靠性的半导体电路。The inventive concept provides a semiconductor circuit that symmetrically forms sampling windows in a small size and thus improves product reliability.

此外,本发明构思提供一种以小的尺寸对称地形成采样窗口并因此提高产品可靠性的半导体系统。In addition, the inventive concept provides a semiconductor system that symmetrically forms sampling windows in a small size and thus improves product reliability.

在下面的描述中部分地阐明本发明构思的其它优点、对像和特征,并且通过下面的检索本发明构思的其它优点、对像和特征对于本领域普通技术人员变得清楚或者从本发明构思的实践中学习到本发明构思的其它优点、对像和特征。Other advantages, objects and features of the inventive concept are set forth in part in the following description and will become apparent to those of ordinary skill in the art or from the inventive concept by the following search. Other advantages, objects and features of the inventive concept are learned from the practice of the present invention.

在本发明构思的一个示例实施例中,提供了一种触发器,该触发器包括:第一反相器,被构造为对第一数据进行反相;第一晶体管和第二晶体管,彼此串联连接且被构造为分别接收反相的第一数据和第一时钟;第三晶体管;第一门,被构造为对第一数据和第一时钟执行逻辑运算;第三晶体管,被构造为接收所述逻辑运算的输出,其中,第二晶体管和第三晶体管连接到第一节点。In an example embodiment of the inventive concept, there is provided a flip-flop including: a first inverter configured to invert first data; a first transistor and a second transistor connected in series with each other connected and configured to receive the inverted first data and the first clock, respectively; a third transistor; a first gate configured to perform a logical operation on the first data and the first clock; and a third transistor configured to receive the output of the logic operation, wherein the second transistor and the third transistor are connected to the first node.

在本发明构思的一个示例实施例中,提供了一种半导体电路,所述半导体电路包括:主电路和从电路,被构造为分别接收第一时钟和第二时钟,第一时钟和第二时钟彼此具有不同相位,其中,主电路包括:第一晶体管、第二晶体管、第三晶体管、第一反相器和第一门,其中,第一晶体管、第二晶体管和第三晶体管串联连接在第一电压端与第二电压端之间,其中,第一反相器被构造为对输入数据进行反相并对第一晶体管进行门控制,其中,第一门被构造为对第三晶体管进行门控制,第一门被构造为对输入数据和第一时钟执行逻辑运算,其中,第二晶体管被构造为接收第一时钟。In one example embodiment of the inventive concept, a semiconductor circuit is provided, the semiconductor circuit including a master circuit and a slave circuit configured to receive first and second clocks, respectively, the first and second clocks have different phases from each other, wherein the main circuit includes: a first transistor, a second transistor, a third transistor, a first inverter and a first gate, wherein the first transistor, the second transistor and the third transistor are connected in series at the between a voltage terminal and a second voltage terminal, wherein the first inverter is configured to invert the input data and gate the first transistor, wherein the first gate is configured to gate the third transistor Controlling, the first gate is configured to perform a logical operation on the input data and the first clock, wherein the second transistor is configured to receive the first clock.

在本发明构思的一实施例中,提供了一种半导体系统,该半导体系统包括:发送器,被构造为使用参考时钟发送第一数据;接收器,被构造为接收第一数据,其中,接收器包括:时钟产生单元,被构造为使用参考时钟产生具有不同相位的第一时钟和第二时钟;主电路,被构造为接收第一数据和第一时钟并输出第二数据;从电路,被构造为接收第二数据和第二时钟并输出第三数据,其中,主电路包括在第一电压端与第一节点之间的用于将第二数据改变至第一电平的第一电路,在第一节点与第二电压端之间的用于将第二数据改变至第二电平的第二电路,并且第二电路被构造为根据第一数据和第二时钟的逻辑运算信号而操作。In one embodiment of the inventive concept, there is provided a semiconductor system including: a transmitter configured to transmit first data using a reference clock; a receiver configured to receive the first data, wherein the receiving The device includes: a clock generating unit configured to generate a first clock and a second clock having different phases using a reference clock; a master circuit configured to receive the first data and the first clock and output the second data; a slave circuit configured to be configured to receive the second data and the second clock and output the third data, wherein the main circuit includes a first circuit between the first voltage terminal and the first node for changing the second data to a first level, A second circuit for changing the second data to a second level between the first node and the second voltage terminal, and the second circuit is configured to operate according to the first data and the logic operation signal of the second clock .

在本发明构思的另一示例实施例中,提供了一种半导体电路,该半导体电路包括:时钟产生单元,被构造为使用参考时钟产生第一时钟和与第一时钟不同的第二时钟;主电路,被构造为接收第一数据和第一时钟并输出第二数据;从电路,被构造为接收第二数据和第二时钟并输出第三数据,其中,第二时钟包括第一子时钟和第二子时钟,其中,主电路包括:第一PMOS晶体管,连接到电源电压;第二PMSO晶体管,串联连接到第一PMOS晶体管并被第一时钟门控制;第一NMOS晶体管,串联连接到第二PMOS晶体管并连接到地电压端;第一反相器,被构造为通过对输入数据进行反相而对第一PMOS晶体管进行门控制;NOR门,被构造为通过执行对于第一时钟和输入数据的NOR逻辑运算而对第一NMOS晶体管进行门控制;时钟产生单元包括:延迟单元,被构造为对参考时钟的相位进行延迟以产生第一时钟;NAND门,被构造为执行对于第一时钟和参考时钟的NAND逻辑运算以产生第一子时钟,第二反相器,被构造为对第一子时钟进行反相以产生第二子时钟。In another example embodiment of the present inventive concept, there is provided a semiconductor circuit including: a clock generating unit configured to generate a first clock and a second clock different from the first clock using a reference clock; a main clock a circuit configured to receive the first data and the first clock and output the second data; the slave circuit configured to receive the second data and the second clock and output the third data, wherein the second clock includes the first sub-clock and The second sub-clock, wherein the main circuit includes: a first PMOS transistor connected to the power supply voltage; a second PMSO transistor connected in series to the first PMOS transistor and controlled by the first clock gate; a first NMOS transistor connected in series to the first clock gate Two PMOS transistors are connected to the ground voltage terminal; the first inverter is configured to gate the first PMOS transistor by inverting the input data; the NOR gate is configured to perform gate control for the first clock and the input NOR logic operation of data to gate control the first NMOS transistor; the clock generation unit includes: a delay unit, configured to delay the phase of the reference clock to generate the first clock; NAND gate, configured to execute the first clock for the first clock. and a NAND logic operation of the reference clock to generate the first sub-clock, and a second inverter configured to invert the first sub-clock to generate the second sub-clock.

至少一个示例实施例公开了一种被构造为产生第一时钟和第二时钟的时钟产生电路,一种被构造为接收第一数据、对于第一时钟和第一数据执行逻辑运算并基于逻辑运算而产生第一输出数据的主电路以及一种被构造为基于第一输出数据和第二时钟而产生第二输出数据的从电路。At least one example embodiment discloses a clock generation circuit configured to generate a first clock and a second clock, a circuit configured to receive first data, perform a logical operation on the first clock and the first data, and based on the logical operation And a master circuit that generates first output data and a slave circuit configured to generate second output data based on the first output data and a second clock.

附图说明Description of drawings

通过下面结合附图进行的详细描述,本发明构思的上述和其它目的、特点和优点将会变得更明显,在附图中:The above and other objects, features and advantages of the present inventive concept will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

图1是根据本发明构思的示例实施例的半导体电路的框图;1 is a block diagram of a semiconductor circuit according to an example embodiment of the inventive concept;

图2是根据本发明构思的示例实施例的半导体电路的电路图;FIG. 2 is a circuit diagram of a semiconductor circuit according to an example embodiment of the inventive concept;

图3是解释根据本发明构思的示例实施例的半导体电路的操作的示图;FIG. 3 is a diagram explaining an operation of a semiconductor circuit according to example embodiments of the inventive concept;

图4是根据本发明构思的另一示例实施例的半导体电路的电路图;4 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concept;

图5是示出图4的半导体电路的操作时序的示图;FIG. 5 is a diagram illustrating an operation timing of the semiconductor circuit of FIG. 4;

图6是根据本发明构思的另一示例实施例的半导体电路的电路图;FIG. 6 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concept;

图7是图6的第一时钟和第二时钟的时序图;FIG. 7 is a timing diagram of the first clock and the second clock of FIG. 6;

图8是根据本发明构思的另一示例实施例的半导体电路的电路图;FIG. 8 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concept;

图9是根据本发明构思的另一示例实施例的半导体电路的电路图;FIG. 9 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concept;

图10是根据本发明构思的另一示例实施例的半导体电路的电路图;10 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concept;

图11是根据本发明构思的另一示例实施例的半导体电路的电路图;11 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concept;

图12是根据本发明构思的另一示例实施例的半导体电路的电路图;12 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concept;

图13是包括根据本发明构思的一些示例实施例的半导体电路的半导体系统的框图;13 is a block diagram of a semiconductor system including a semiconductor circuit according to some example embodiments of the inventive concepts;

图14是示出可采用根据本发明构思的一些示例实施例的半导体电路的计算系统的构造的框图;14 is a block diagram illustrating a configuration of a computing system that may employ semiconductor circuits according to some example embodiments of the inventive concepts;

图15是示出可采用根据本发明构思的一些示例实施例的半导体电路的电子系统的构造的框图;15 is a block diagram illustrating a configuration of an electronic system that may employ semiconductor circuits according to some example embodiments of the inventive concepts;

图16是示出将图15的电子系统应用至智能手机的示例的示图。FIG. 16 is a diagram illustrating an example of applying the electronic system of FIG. 15 to a smartphone.

具体实施方式Detailed ways

现在将在下文中参照附图更充分地描述本发明构思,在附图中示出了本发明构思的示例实施例。然而,本发明构思可以以不同的形式来实施,且不应该解释为局限于在这里所阐述的示例实施例。相反,提供这些示例实施例使得本公开将是彻底和完全的,并将本发明构思的范围充分地传达给本领域技术人员。贯穿说明书,相同附图标号指示相同组件。在附图中,为了清晰起见,会夸大层和区域的厚度。The inventive concept will now be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the inventive concept are shown. The inventive concepts may, however, be embodied in different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. Throughout the specification, the same reference numerals refer to the same components. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

除非这里另有说明或与上下文明显矛盾,否则在描述本发明构思的上下文(尤其,在权利要求的上下文)中使用的单数形式或相似指代将被解释为覆盖单数和复数二者。除非另有注释,否则术语“包括”、“具有”、“包含”和“含有”将被解释为开放式术语(即,表示“包含,但不限于”)。Unless otherwise indicated herein or clearly contradicted by context, the use of the singular or similar references in the context of describing the inventive concept (especially, in the context of the claims) is to be construed to cover both the singular and the plural. The terms "including," "having," "including," and "containing" are to be construed as open-ended terms (ie, meaning "including, but not limited to,") unless otherwise noted.

除非另有定义,否则这里使用的所有技术术语和科学术语具有与本发明构思所属领域的普通技术人员所通常理解的含义相同的含义。注意的是,除非另有限定,否则在这里使用的任何和所有示例或提供的术语仅意图更好地示出本发明构思,且不限制本发明构思的范围。此外,除非另有定义,否则在通用词典中定义的所有术语不应被过度解释。Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It is noted that any and all examples or terminology used herein are merely intended to better illustrate the inventive concept, and do not limit the scope of the inventive concept, unless otherwise defined. Also, unless otherwise defined, all terms defined in the general dictionary should not be overly construed.

将参照示出本发明构思的示例实施例的立体图、剖视图和/或平面图来描述本发明构思。因此,示例性示图的轮廓可根据制造技术和/或容量而被修改。也就是说,本发明构思的示例实施例不意图限制本发明构思的范围,而是覆盖因制造技术的改变而可引起的所有改变和修改。因此,以示意图的形式示出附图中示出的区域,并且区域的形状通过说明的方式,而不是限制的方式而被简化示出。The inventive concept will be described with reference to perspective, cross-sectional, and/or plan views illustrating example embodiments of the inventive concept. Accordingly, the outlines of the exemplary diagrams may be modified according to manufacturing technology and/or capacity. That is, the exemplary embodiments of the inventive concept are not intended to limit the scope of the inventive concept, but to cover all changes and modifications that may be caused by changes in manufacturing techniques. Accordingly, the regions illustrated in the figures are shown in schematic form, and their shapes are simplified by way of illustration, and not limitation.

以下,将参照图1和图2来描述根据本发明构思的示例实施例的半导体电路1。Hereinafter, a semiconductor circuit 1 according to an example embodiment of the inventive concept will be described with reference to FIGS. 1 and 2 .

图1是根据本发明构思的示例实施例的半导体电路1的框图,图2是根据本发明构思的示例实施例的半导体电路1的电路图。FIG. 1 is a block diagram of a semiconductor circuit 1 according to an example embodiment of the present inventive concept, and FIG. 2 is a circuit diagram of a semiconductor circuit 1 according to an example embodiment of the present inventive concept.

参照图1,半导体电路1包括主级(master stage)100、从级(slave stage)200和时钟产生单元300。1 , a semiconductor circuit 1 includes a master stage 100 , a slave stage 200 and a clock generation unit 300 .

例如,半导体电路1可接收输入数据并执行对接收到的数据的采样。但是,本发明构思不限于此。在下面中,示例性示出半导体装置1是主从触发器。但是,本发明构思不限于此,本发明构思的技术构思可不受限制地修改且应用于其它半导体装置。For example, the semiconductor circuit 1 may receive input data and perform sampling of the received data. However, the inventive concept is not limited thereto. In the following, the semiconductor device 1 is exemplarily shown as a master-slave flip-flop. However, the inventive concept is not limited thereto, and the technical idea of the inventive concept can be modified without limitation and applied to other semiconductor devices.

主级100接收第一数据ID和第一时钟CK1。主级100可基于第一时钟CK1接收第一数据ID,并输出第二数据OD1。可从时钟产生单元300提供第一时钟CK1。The main stage 100 receives the first data ID and the first clock CK1. The main stage 100 may receive the first data ID based on the first clock CK1 and output the second data OD1. The first clock CK1 may be provided from the clock generating unit 300 .

从级200接收第二时钟CK2和第二数据OD1。从级200可基于第二时钟CK2接收第二数据OD1,并输出第三数据OD2。在该示例实施例中,第二时钟CK2也可从时钟产生单元300提供。这里,第一数据ID可以是输入至半导体电路1的输入数据,第二数据OD1可以是从主级100输出的第一输出数据,第三数据OD2可以是从从级200输出的第二输出数据。The slave stage 200 receives the second clock CK2 and the second data OD1. The slave stage 200 may receive the second data OD1 based on the second clock CK2 and output the third data OD2. In this example embodiment, the second clock CK2 may also be supplied from the clock generating unit 300 . Here, the first data ID may be input data input to the semiconductor circuit 1 , the second data OD1 may be the first output data output from the master stage 100 , and the third data OD2 may be the second output data output from the slave stage 200 .

另一方面,提供给从级200的第二时钟CK2可包括第一子时钟CK2-1和第二子时钟CK2-2。主级100可使用第一时钟CK1和逻辑运算信号MCK1,其中,所述逻辑运算信号MCK1通过执行对于第一时钟CK1和第一数据ID的逻辑运算而获得,这将在后面描述。以下,将描述将第二时钟CK2划分为多个子时钟并将划分的子时钟应用至从级200的构造,但是本发明构思不限于此。On the other hand, the second clock CK2 provided to the slave stage 200 may include a first sub-clock CK2-1 and a second sub-clock CK2-2. The main stage 100 may use a first clock CK1 and a logic operation signal MCK1 obtained by performing a logic operation on the first clock CK1 and the first data ID, which will be described later. Hereinafter, a configuration of dividing the second clock CK2 into a plurality of sub-clocks and applying the divided sub-clocks to the slave stage 200 will be described, but the inventive concept is not limited thereto.

参照图2,主级100可包括例如第一电路101、第二电路103、第一反相器IN11、第一门G11、第二反相器IN12和第一保持器(keeper)41。2 , the main stage 100 may include, for example, a first circuit 101 , a second circuit 103 , a first inverter IN11 , a first gate G11 , a second inverter IN12 and a first keeper 41 .

第一电路101和第二电路103围绕第一节点N1而串联连接。第一电路101连接至第一电压端,第二电路103连接至第二电压端。例如,第一电压可以是电源电压,第二电压可以是地电压,但不限于此。The first circuit 101 and the second circuit 103 are connected in series around the first node N1. The first circuit 101 is connected to the first voltage terminal, and the second circuit 103 is connected to the second voltage terminal. For example, the first voltage may be a power supply voltage, and the second voltage may be a ground voltage, but not limited thereto.

第一电路101可通过串联连接第一晶体管MP11和第二晶体管MP12而形成。第二电路103可包括第三晶体管MN11。例如,第一晶体管MP11可以是PMOS晶体管,第二晶体管MP12可以是PMOS晶体管,且第三晶体管MN11可以是NMOS晶体管。第一电路101可接收第一数据ID和第一时钟CK1,并且可通过接收到的数据改变第二数据OD1。第二电路103可通过第一门G11接收逻辑地运算的信号以进行运算,并改变第二数据OD1。详细地讲,第一电路101可将第二数据OD1改变至第一电平,并且第二电路103可将第二数据OD1改变至第二电平。例如,第一电平可以是逻辑低电平,而第二电平可以是逻辑高电平。将在后面描述其详细内容。The first circuit 101 may be formed by connecting the first transistor MP11 and the second transistor MP12 in series. The second circuit 103 may include a third transistor MN11. For example, the first transistor MP11 may be a PMOS transistor, the second transistor MP12 may be a PMOS transistor, and the third transistor MN11 may be an NMOS transistor. The first circuit 101 may receive the first data ID and the first clock CK1, and may change the second data OD1 by the received data. The second circuit 103 may receive the logically operated signal through the first gate G11 to perform an operation, and change the second data OD1. In detail, the first circuit 101 may change the second data OD1 to a first level, and the second circuit 103 may change the second data OD1 to a second level. For example, the first level may be a logic low level and the second level may be a logic high level. The details thereof will be described later.

第一反相器IN11对第一数据ID进行反相,并产生反相的数据IDB。第一数据ID可以是例如主级100接收的输入数据。第一反相器IN11可连接到第一晶体管MP11,并且第一数据ID的反相的数据IDB可被提供给第一晶体管MP11。反相的数据IDB可对第一晶体管MP11进行门控。The first inverter IN11 inverts the first data ID and generates inverted data IDB. The first data ID may be, for example, input data received by the main stage 100 . The first inverter IN11 may be connected to the first transistor MP11, and the inverted data IDB of the first data ID may be supplied to the first transistor MP11. The inverted data IDB may gate the first transistor MP11.

第二晶体管MP12可接收第一时钟CK1并且可被第一时钟CK1门控制。The second transistor MP12 may receive the first clock CK1 and may be gate-controlled by the first clock CK1.

第一门G11接收第一数据ID和第一时钟CK1。第一门G11通过执行接收到的第一数据ID和第一时钟CK1的第一逻辑运算而产生逻辑运算信号MCK1,并将产生的逻辑运算信号MCK1提供给第三晶体管MN11。第一门G11可以是例如或非(NOR)门。因此,第一逻辑运算可以是NOR逻辑运算。逻辑运算信号MCK1可对第三晶体管MN11进行门控制。The first gate G11 receives the first data ID and the first clock CK1. The first gate G11 generates a logic operation signal MCK1 by performing a first logic operation of the received first data ID and the first clock CK1, and supplies the generated logic operation signal MCK1 to the third transistor MN11. The first gate G11 may be, for example, a NOR gate. Therefore, the first logic operation may be a NOR logic operation. The logic operation signal MCK1 may gate control the third transistor MN11.

第二反相器IN12可连接在第一节点N1和第二节点N2之间。第二反相器IN12可对第一节点N1的信号进行反相并将反相的信号输出至第二节点N2,输出信号可以是第二数据OD1。The second inverter IN12 may be connected between the first node N1 and the second node N2. The second inverter IN12 may invert the signal of the first node N1 and output the inverted signal to the second node N2, and the output signal may be the second data OD1.

第一保持器41可连接在第一节点N1和第二节点N2之间。第一保持器41可并联连接到第二反相器IN12。第一保持器41可使用第一时钟CK1和逻辑运算信号MCK1进行操作。第一保持器41可对第二数据OD1进行锁存。因此,第二数据OD1可被保持恒定,而不受外部干扰。The first holder 41 may be connected between the first node N1 and the second node N2. The first holder 41 may be connected in parallel to the second inverter IN12. The first holder 41 may operate using the first clock CK1 and the logic operation signal MCK1. The first holder 41 may latch the second data OD1. Therefore, the second data OD1 can be kept constant without external disturbance.

从级200可包括第四晶体管MN21、第五晶体管MP21、第二保持器42和第三反相器IN21。The slave stage 200 may include a fourth transistor MN21, a fifth transistor MP21, a second holder 42 and a third inverter IN21.

第四晶体管MN21和第五晶体管MP21可并联连接在第二节点N2和第三接点N3之间。例如,第四晶体管MN21可以是NMOS晶体管,而第五晶体管MP21可以是PMOS晶体管。第四晶体管MN21可被第二子时钟CK2-2门控制,而第五晶体管MP21可被第一子时钟CK2-1门控制。第四晶体管MN21和第五晶体管MP21可确定是否将第二数据OD1传送至第三接点N3。The fourth transistor MN21 and the fifth transistor MP21 may be connected in parallel between the second node N2 and the third node N3. For example, the fourth transistor MN21 may be an NMOS transistor, and the fifth transistor MP21 may be a PMOS transistor. The fourth transistor MN21 may be gate-controlled by the second sub-clock CK2-2, and the fifth transistor MP21 may be gate-controlled by the first sub-clock CK2-1. The fourth transistor MN21 and the fifth transistor MP21 may determine whether to transfer the second data OD1 to the third node N3.

第三反相器IN21连接至第三节点N3,并对传送至第三节点N3的信号进行反相。由第三反相器IN21反相的反相后的信号可以是第三数据OD2。The third inverter IN21 is connected to the third node N3, and inverts the signal transmitted to the third node N3. The inverted signal inverted by the third inverter IN21 may be the third data OD2.

第二保持器42可连接到第三接点N3。第二保持器42可包括第四反相器IN22和第五反相器IN23。第四反相器IN22和第五反相器IN23可串联连接,并且第四反相器IN22可接收第一子时钟CK2-1和第二子时钟CK2-2以进行操作。第二保持器42可对提供给第三接点N3的信号进行锁存。The second holder 42 may be connected to the third contact N3. The second holder 42 may include a fourth inverter IN22 and a fifth inverter IN23. The fourth inverter IN22 and the fifth inverter IN23 may be connected in series, and the fourth inverter IN22 may receive the first sub-clock CK2-1 and the second sub-clock CK2-2 to operate. The second holder 42 may latch the signal supplied to the third contact N3.

参照图1,时钟产生单元300可接收参考时钟CK,并从参考时钟CK产生第一时钟CK1和第二时钟CK2。第二时钟CK2可包括第一子时钟CK2-1和第二子时钟CK2-2。Referring to FIG. 1 , the clock generating unit 300 may receive the reference clock CK, and generate the first clock CK1 and the second clock CK2 from the reference clock CK. The second clock CK2 may include a first sub-clock CK2-1 and a second sub-clock CK2-2.

在该示例实施例中,第一时钟CK1和第二时钟CK2可彼此不同。换言之,第一时钟CK1的相位与第二时钟CK2的相位不同。详细地讲,第一时钟CK1和第二时钟CK2可被产生,使得第一时钟CK1和第二时钟CK2的沿中的至少一个沿成为非重叠沿。更为详细地讲,第一时钟CK1和第二时钟CK2可被产生,使得第一时钟CK1的第一沿与第二时钟CK2的第一沿不重叠,并且第一时钟CK1的至少一部分第二沿与第二时钟CK2的第二沿重叠。例如,第一沿可以是上升沿RE,而第二沿可以是下降沿FE,但是不限于此。第一沿可以是下降沿,而第二沿可以是上升沿。In this example embodiment, the first clock CK1 and the second clock CK2 may be different from each other. In other words, the phase of the first clock CK1 is different from the phase of the second clock CK2. In detail, the first clock CK1 and the second clock CK2 may be generated such that at least one of the edges of the first clock CK1 and the second clock CK2 becomes a non-overlapping edge. In more detail, the first clock CK1 and the second clock CK2 may be generated such that the first edge of the first clock CK1 does not overlap with the first edge of the second clock CK2, and at least a portion of the first clock CK1 is second. The edge overlaps with the second edge of the second clock CK2. For example, the first edge may be the rising edge RE, and the second edge may be the falling edge FE, but is not limited thereto. The first edge may be a falling edge and the second edge may be a rising edge.

参照图2,时钟产生单元300可包括第六反相器IN31和第七反相器IN32。Referring to FIG. 2 , the clock generating unit 300 may include a sixth inverter IN31 and a seventh inverter IN32.

在图2的半导体电路1中,第一时钟CK1可以与参考时钟CK相同。因此,时钟产生单元300可将参考时钟按原样提供给主级100。In the semiconductor circuit 1 of FIG. 2 , the first clock CK1 may be the same as the reference clock CK. Therefore, the clock generation unit 300 may provide the reference clock to the main stage 100 as it is.

第一子时钟CK2-1可通过由第六反相器IN31对参考时钟CK反相来产生。此外,第二子时钟CK2-2可通过由第七反相器IN32对第一子时钟CK2-1反相来产生。The first sub-clock CK2-1 may be generated by inverting the reference clock CK by the sixth inverter IN31. Also, the second sub-clock CK2-2 may be generated by inverting the first sub-clock CK2-1 by the seventh inverter IN32.

将参照图3和表1来描述根据本发明构思的示例实施例的半导体电路1的操作。The operation of the semiconductor circuit 1 according to example embodiments of the inventive concepts will be described with reference to FIG. 3 and Table 1 .

图3和表1是解释半导体电路1的操作的示图和表。图3是示出半导体电路1的操作时序的示图,表1是示出第一门G11根据其输入的输出的表。FIG. 3 and Table 1 are diagrams and tables for explaining the operation of the semiconductor circuit 1 . FIG. 3 is a diagram showing the operation timing of the semiconductor circuit 1 , and Table 1 is a table showing the output of the first gate G11 according to its input.

表1Table 1

Figure GDA0002049914890000071
Figure GDA0002049914890000071

在详细解释描述半导体电路1的操作之前,将描述可表示触发器电路的操作特性的一些术语。Before explaining the operation of the semiconductor circuit 1 in detail, some terms that can represent the operation characteristics of the flip-flop circuit will be described.

首先,采样窗口Tsw表示为了使触发器电路读取输入信号的数据值而需要保持输入信号的时间。采样窗口可如下面的等式1表示。First, the sampling window Tsw represents the time required to hold the input signal in order for the flip-flop circuit to read the data value of the input signal. The sampling window can be expressed as Equation 1 below.

[等式1][Equation 1]

采样窗口(Tsw)=数据建立时间(Tsetup)+数据保持时间(Thold)Sampling window (Tsw) = data setup time (Tsetup) + data hold time (Thold)

这里,数据建立时间Tsetup表示为了使触发器电路从输入信号精确地读取数据值而预先提供的时间。即,数据建立时间Tsetup是表示为了使触发器电路可从输入信号精确地读取数据值,而在时钟信号被施加之前触发器电路准备读取操作而需要的时间的指标。Here, the data setup time Tsetup represents a time provided in advance in order for the flip-flop circuit to accurately read the data value from the input signal. That is, the data setup time Tsetup is an index indicating the time required for the flip-flop circuit to prepare for a read operation before the clock signal is applied so that the flip-flop circuit can accurately read the data value from the input signal.

在本发明构思中,数据建立时间Tsetup表示为了在第二数据OD1通过第一数据ID改变时精确地读取第一数据ID的值而应预先提供的时间。数据建立时间Tsetup可包括数据建立上升时间Tsr和数据建立下降时间Tsf。数据建立上升时间Tsr表示为了精确地读取第一数据ID的上升沿RE(即,为了精确地读取逻辑高电平)而应提供的时间,而数据建立下降时间Tsf表示为了读取第一数据ID的下降沿FE(即,为了精确地读取逻辑低电平)而应提供的时间。In the inventive concept, the data setup time Tsetup represents a time that should be provided in advance in order to accurately read the value of the first data ID when the second data OD1 is changed by the first data ID. The data setup time Tsetup may include a data setup rise time Tsr and a data setup fall time Tsf. The data setup rise time Tsr represents the time that should be provided in order to accurately read the rising edge RE of the first data ID (ie, in order to accurately read the logic high level), and the data setup fall time Tsf represents the time required to read the first data ID. The time that the falling edge FE of the data ID (ie, to accurately read the logic low level) should be provided.

参照图3,可以看出,当第一数据ID在数据建立上升时间Tsr改变至逻辑高电平或在数据建立下降时间Tsf改变至逻辑低电平时,第二数据OD1改变。3 , it can be seen that when the first data ID changes to a logic high level at the data setup rise time Tsr or to a logic low level at the data setup fall time Tsf, the second data OD1 changes.

例如,对于数据建立上升时间Tsr,当第一时钟CK1被施加时第一数据ID的逻辑高电平应被读取。当第一时钟CK1具有恒定值C或更大值时,第一数据ID的上升沿RE也应具有足够读取逻辑高电平的恒定值D。因此,在图3中,可将C与D之间的时间考虑为数据建立上升时间Tsr。由于可从数据建立上升时间Tsr类推出数据建立下降时间Tsf,因此将省略对其的描述。For example, for the data setup rise time Tsr, the logic high level of the first data ID should be read when the first clock CK1 is applied. When the first clock CK1 has a constant value C or greater, the rising edge RE of the first data ID should also have a constant value D sufficient to read a logic high level. Therefore, in FIG. 3, the time between C and D can be considered as the data setup rise time Tsr. Since the data settling fall time Tsf can be derived from the data settling rise time Tsr class, the description thereof will be omitted.

另一方面,数据保持时间Thold表示为了使触发器电路从输入信号精确地读取数据值而应保持输入信号的时间。即,数据保持时间Thold是表示为了使触发器电路可从输入信号精确地读取数据值,而在时钟信号被施加之后应保持输入信号的时间的指标。On the other hand, the data hold time Thold represents the time for which the input signal should be held in order for the flip-flop circuit to accurately read the data value from the input signal. That is, the data hold time Thold is an index indicating the time for which the input signal should be held after the clock signal is applied so that the flip-flop circuit can accurately read the data value from the input signal.

在本发明构思中,数据保持时间Thold表示为了精确地读取第一数据ID的值以使第二数据OD1保持恒定而应保持第一数据ID的时间。数据保持时间Thold可包括数据保持上升时间Thr和数据保持下降时间Thf。数据保持上升时间Thr表示为了刚好在第一数据ID的上升沿RE被产生之前精确地读取逻辑低电平而应保持第一数据ID的时间,而数据保持下降时间Thf表示为了刚好在第一数据ID的下降沿FE被产生之前精确地读取逻辑高电平而应保持第一数据ID的时间。In the inventive concept, the data holding time Thold represents the time during which the first data ID should be held in order to accurately read the value of the first data ID to keep the second data OD1 constant. The data hold time Thold may include a data hold rise time Thr and a data hold fall time Thf. The data hold rise time Thr represents the time during which the first data ID should be held in order to accurately read the logic low level just before the rising edge RE of the first data ID is generated, and the data hold fall time Thf represents the time for which the first data ID should be held just before the first data ID's rising edge RE is generated. The time that the first data ID should be held by reading the logic high level exactly before the falling edge FE of the data ID is generated.

参照图3,可以看出,即使示出了数据保持上升时间Thr和数据保持下降时间Thf的第一数据ID被改变至第一逻辑高电平或逻辑低电平,第二数据OD1仍保持恒定。Referring to FIG. 3, it can be seen that even if the first data ID showing the data holding rising time Thr and the data holding falling time Thf is changed to the first logic high level or the logic low level, the second data OD1 remains constant .

例如,对于数据保持下降时间Thf,当第一时钟CK1被施加时第一数据ID的逻辑高电平应被读取。当第一时钟CK1具有恒定值A或更大值时,第一数据ID的下降沿FE应保持足够读取逻辑高电平的恒定值B或更大值。因此,在图3中,将A与B之间的时间考虑为数据保持下降时间Thf。由于可从数据保持下降时间Thf类推出数据保持上升时间Thr,因此将省略对其的描述。在根据本发明构思的示例实施例的半导体电路1中,可从数据建立上升时间Tsr和数据保持下降时间Thf之和获得高采样窗口Tsw_high,可从数据建立下降时间Tsf和数据保持上升时间Thr之和获得低采样窗口Tsw_low。换言之,高采样窗口Tsw_high表示将第一数据ID的电平读取为逻辑高电平而提供的时间与第一数据ID的电平应被保持为逻辑高电平的时间之和。For example, for the data hold fall time Thf, the logic high level of the first data ID should be read when the first clock CK1 is applied. When the first clock CK1 has a constant value A or more, the falling edge FE of the first data ID should maintain a constant value B or more sufficient to read a logic high level. Therefore, in FIG. 3, the time between A and B is considered as the data hold fall time Thf. Since the data hold rise time Thr can be derived from the data hold fall time Thf class, the description thereof will be omitted. In the semiconductor circuit 1 according to example embodiments of the inventive concept, the high sampling window Tsw_high may be obtained from the sum of the data setup rise time Tsr and the data hold fall time Thf, and the high sampling window Tsw_high may be obtained from the sum of the data setup fall time Tsf and the data hold rise time Thr and get the low sampling window Tsw_low. In other words, the high sampling window Tsw_high represents the sum of the time provided for reading the level of the first data ID as a logic high level and the time during which the level of the first data ID should be kept at a logic high level.

另一方面,低采样窗口Tsw_low表示将第一数据ID的电平读取为逻辑低电平而应提供的时间与第一数据ID的电平应被保持为逻辑低电平的时间之和。On the other hand, the low sampling window Tsw_low represents the sum of the time that should be provided to read the level of the first data ID as a logic low level and the time that the level of the first data ID should be kept at the logic low level.

在通常的触发器电路中,随着采样窗口的大小变得越小,触发器电路可以以更高速度操作。In a general flip-flop circuit, as the size of the sampling window becomes smaller, the flip-flop circuit can operate at a higher speed.

参照图3和表1,如果第一数据ID施加至主级100,则第一数据ID通过主级100直接输出为第二数据OD1(操作(1))。详细地讲,由于当第一数据ID的电平是逻辑低电平时第一时钟CK1的电平变为高电平,第一晶体管MP11和第二晶体管MP12均被导通。但是,第三晶体管MN11保持在截止状态。因此,第一节点N1保持在高电平,结果,第二数据OD1被保持在第一电平(逻辑低电平)(操作(2))。3 and Table 1, if the first data ID is applied to the main stage 100, the first data ID is directly output as the second data OD1 through the main stage 100 (operation (1)). In detail, since the level of the first clock CK1 becomes a high level when the level of the first data ID is a logic low level, both the first transistor MP11 and the second transistor MP12 are turned on. However, the third transistor MN11 remains in an off state. Therefore, the first node N1 is maintained at the high level, and as a result, the second data OD1 is maintained at the first level (logic low level) (operation (2)).

由于第一时钟CK1的电平是逻辑高电平,因此第一子时钟CK2-1的电平变为逻辑低电平,第二子时钟CK2-2的电平变为逻辑高电平。由于第一子时钟CK2-1由第六反相器IN31产生,因此第一子时钟CK2-1的相位相比于第一时钟CK1的相位延迟一定时间。由于第二子时钟CK2-2由第七反相器IN32产生,所以第二子时钟CK2-2的相位相比于第一子时钟CK2-1的相位延迟一定时间。由于可从上述的时钟产生单元300的构造推导出参考时钟CK与第一子时钟CK2-1和第二子时钟CK2-2之间的上述关系,因此将省略其详细描述。Since the level of the first clock CK1 is a logic high level, the level of the first sub clock CK2-1 becomes a logic low level, and the level of the second sub clock CK2-2 becomes a logic high level. Since the first sub-clock CK2-1 is generated by the sixth inverter IN31, the phase of the first sub-clock CK2-1 is delayed by a certain time compared to the phase of the first clock CK1. Since the second sub-clock CK2-2 is generated by the seventh inverter IN32, the phase of the second sub-clock CK2-2 is delayed by a certain time compared to the phase of the first sub-clock CK2-1. Since the above-described relationship between the reference clock CK and the first and second sub-clocks CK2-1 and CK2-2 can be derived from the above-described configuration of the clock generating unit 300, a detailed description thereof will be omitted.

另一方面,如果如上所述,第一子时钟CK2-1是逻辑高电平并且第二子时钟CK2-2是逻辑低电平,则第四晶体管MN21和第五晶体管MP21截止,并且从级200处于禁用状态。因此,第一数据ID无法被锁存至从级200。On the other hand, if the first sub clock CK2-1 is a logic high level and the second sub clock CK2-2 is a logic low level as described above, the fourth transistor MN21 and the fifth transistor MP21 are turned off, and the slave stage 200 is disabled. Therefore, the first data ID cannot be latched to the slave stage 200 .

然后,如果形成第一时钟CK1的上升沿RE,则第二晶体管MP12截止。但是,由第一门G11产生的逻辑运算信号MCK1的电平保持为逻辑低电平。因此,第三晶体管MN11仍处于截止状态,第一节点N1保持在逻辑高电平。Then, if the rising edge RE of the first clock CK1 is formed, the second transistor MP12 is turned off. However, the level of the logic operation signal MCK1 generated by the first gate G11 remains at a logic low level. Therefore, the third transistor MN11 is still in an off state, and the first node N1 is kept at a logic high level.

由于形成了第一时钟CK1的上升沿RE,因此第一子时钟CK2-1和第二子时钟CK2-2分别具有下降沿FE和上升沿RE。因此,从级200被启用。因此,第二数据OD1被提供给从级200,第三反相器IN21对第二数据OD1进行反相以输出第三数据。第三数据OD2可处于逻辑高电平。Since the rising edge RE of the first clock CK1 is formed, the first sub-clock CK2-1 and the second sub-clock CK2-2 have a falling edge FE and a rising edge RE, respectively. Therefore, the slave stage 200 is enabled. Therefore, the second data OD1 is supplied to the slave stage 200, and the third inverter IN21 inverts the second data OD1 to output the third data. The third data OD2 may be at a logic high level.

然后,如果形成第一数据ID的下降沿FE,则形成反相的数据IDB的上升沿(操作(3)),其中,通过第一反相器IN11对第一数据ID进行时间延迟而产生所述反相的数据IDB。反相的数据IDB保持在逻辑高电平以截止第一晶体管MP11。但是,由于逻辑运算信号MCK1仍处于逻辑低电平,因此第三晶体管MN11处于截止状态,因此第二数据OD1保持在逻辑低电平。Then, if the falling edge FE of the first data ID is formed, the rising edge of the inverted data IDB is formed (operation (3)), wherein the first data ID is time-delayed by the first inverter IN11 to generate the Describe the inverted data IDB. The inverted data IDB remains at a logic high level to turn off the first transistor MP11. However, since the logic operation signal MCK1 is still at a logic low level, the third transistor MN11 is in an off state, and thus the second data OD1 remains at a logic low level.

另一方面,由于第一时钟CK1的上升沿RE和第一数据ID的下降沿FE部分地相互重叠,因此在逻辑运算信号MCK1中可发生局部改变M1。但是,这种局部改变不会对第三晶体管MN11施加影响。此外,局部改变M1可不发生。On the other hand, since the rising edge RE of the first clock CK1 and the falling edge FE of the first data ID partially overlap each other, a local change M1 may occur in the logic operation signal MCK1. However, such a local change does not exert an influence on the third transistor MN11. Furthermore, local changes M1 may not occur.

然后,如果形成第一时钟CK1的下降沿FE,则可形成逻辑运算信号MCK1的上升沿RE(操作(4))。通过逻辑运算信号MCK1,第三晶体管MN11导通,并且第一节点N1改变至逻辑低电平(操作(5))。因此,通过第二反相器IN12对第二数据OD1延迟一定时间,并将第二数据OD1改变至逻辑高电平(操作(6))。结果,第一数据ID可被输出为在第一时钟CK1的下降沿FE的第一数据ID。Then, if the falling edge FE of the first clock CK1 is formed, the rising edge RE of the logic operation signal MCK1 may be formed (operation (4)). By the logic operation signal MCK1, the third transistor MN11 is turned on, and the first node N1 is changed to a logic low level (operation (5)). Therefore, the second data OD1 is delayed for a certain time by the second inverter IN12, and is changed to a logic high level (operation (6)). As a result, the first data ID may be output as the first data ID at the falling edge FE of the first clock CK1.

如果形成第一时钟CK1的下降沿FE,则从级200被禁用,并且无法对第二数据OD1进行锁存。因此,第三数据OD2被保持在逻辑高电平。If the falling edge FE of the first clock CK1 is formed, the slave stage 200 is disabled and the second data OD1 cannot be latched. Therefore, the third data OD2 is maintained at a logic high level.

另一方面,参照表1,可以看出,逻辑运算信号MCK1仅在第一时钟CK1和第一数据ID均处于逻辑低电平时处于逻辑高电平。On the other hand, referring to Table 1, it can be seen that the logic operation signal MCK1 is at a logic high level only when the first clock CK1 and the first data ID are both at a logic low level.

再次参照图3,如果在第一数据ID保持在逻辑低电平状态的情况下形成第一时钟CK1的上升沿RE,则第一晶体管MP11、第二晶体管MP12和第三晶体管MN11全部截止,且主级100被禁用。因此,第二数据OD1保持在逻辑高电平。此外,如果形成第一时钟CK1的上升沿RE,则从级200被启用。从级200接收逻辑高电平的第二数据OD1,并形成第三数据OD2的下降沿。结果,在第一时钟CK1的上升沿RE,从级200读取第一数据ID并将输出读取的第一数据ID作为第三数据OD2(操作(7))。Referring again to FIG. 3 , if the rising edge RE of the first clock CK1 is formed with the first data ID kept in the logic low state, the first transistor MP11 , the second transistor MP12 and the third transistor MN11 are all turned off, and Main stage 100 is disabled. Therefore, the second data OD1 remains at a logic high level. Furthermore, if the rising edge RE of the first clock CK1 is formed, the slave stage 200 is enabled. The second data OD1 of a logic high level is received from the stage 200 and forms a falling edge of the third data OD2. As a result, at the rising edge RE of the first clock CK1, the first data ID is read from the stage 200 and the read first data ID is output as the third data OD2 (operation (7)).

然后,如果形成第一数据ID的上升沿RE,则第一晶体管MP11导通,但是第二晶体管MP12和第三晶体管MN11仍处于截止状态。因此,主级100处于禁用状态,而第二数据OD1保持恒定(操作(8))。由于第一时钟CK1处于逻辑高电平,因此从级200被启用,并且第三反相器IN21对第二数据OD1进行反相并输出反相的第二数据作为第三数据OD2。Then, if the rising edge RE of the first data ID is formed, the first transistor MP11 is turned on, but the second transistor MP12 and the third transistor MN11 are still in the off state. Therefore, the main stage 100 is in a disabled state, and the second data OD1 is kept constant (operation (8)). Since the first clock CK1 is at a logic high level, the slave stage 200 is enabled, and the third inverter IN21 inverts the second data OD1 and outputs the inverted second data as the third data OD2.

然后,如果第一时钟CK1处于逻辑低电平,并且第一数据ID处于逻辑低电平,则第一晶体管MP11截止。此时,由于逻辑运算信号MCK1处于逻辑高电平,因此第三晶体管MN11导通,而第一节点N1处于逻辑低电平。因此,第二数据OD1处于逻辑高电平。但是,由于第一时钟CK1处于逻辑低电平,因此从级200被禁用,并因此从级200无法对第二数据OD1进行锁存。Then, if the first clock CK1 is at a logic low level and the first data ID is at a logic low level, the first transistor MP11 is turned off. At this time, since the logic operation signal MCK1 is at a logic high level, the third transistor MN11 is turned on, and the first node N1 is at a logic low level. Therefore, the second data OD1 is at a logic high level. However, since the first clock CK1 is at a logic low level, the slave stage 200 is disabled, and thus the slave stage 200 cannot latch the second data OD1.

如果形成了第一数据ID的上升沿RE,则第一晶体管MP11和第二晶体管MP12导通,并形成第一节点N1的上升沿(操作(9))。此时,形成逻辑运算信号MCK1的下降沿FE,并且第三晶体管MN11截止(操作(10))。如果形成第一节点N1的上升沿RE,则第二反相器IN12对第二数据OD1延迟一定时间,且形成第二数据OD1的下降沿FE。此时,第一时钟CK1处于逻辑低电平,而从级200处于禁用状态。If the rising edge RE of the first data ID is formed, the first transistor MP11 and the second transistor MP12 are turned on, and the rising edge of the first node N1 is formed (operation (9)). At this time, the falling edge FE of the logic operation signal MCK1 is formed, and the third transistor MN11 is turned off (operation (10)). If the rising edge RE of the first node N1 is formed, the second inverter IN12 delays the second data OD1 for a certain time, and forms the falling edge FE of the second data OD1. At this time, the first clock CK1 is at a logic low level, and the slave stage 200 is in a disabled state.

如果形成第一时钟CK1的上升沿RE,则第二晶体管MP12和第三晶体管MN11截止,而主级100被禁用。因此,第二数据OD1保持在逻辑低电平(操作(11))。在第一时钟CK1的上升沿RE,从级200被启用,且接收第二数据OD1并对第二数据OD1进行反相以输出反相的第二数据OD1作为第三数据OD2。由于可通过对于上述内容的推导充分地预料到半导体电路1的后续操作,因此将省略其描述。If the rising edge RE of the first clock CK1 is formed, the second transistor MP12 and the third transistor MN11 are turned off, and the main stage 100 is disabled. Therefore, the second data OD1 is maintained at a logic low level (operation (11)). At the rising edge RE of the first clock CK1, the slave stage 200 is enabled, and receives the second data OD1 and inverts the second data OD1 to output the inverted second data OD1 as the third data OD2. Since the subsequent operations of the semiconductor circuit 1 can be sufficiently anticipated by derivation from the above, the description thereof will be omitted.

根据如上描述的该实施例的半导体电路1的操作被概括为如下。The operation of the semiconductor circuit 1 according to this embodiment as described above is summarized as follows.

首先,在形成第一时钟CK1的上升沿RE之后,形成第一子时钟CK2-1的下降沿。因此,主级100基于图3的时间点T1被禁用,而从级200基于图3的时间点T2被启用。First, after the rising edge RE of the first clock CK1 is formed, the falling edge of the first sub clock CK2-1 is formed. Therefore, the master stage 100 is disabled based on the time point T1 of FIG. 3 , and the slave stage 200 is enabled based on the time point T2 of FIG. 3 .

即,由于第一子时钟CK2-1的下降沿FE不能被形成为与第一时钟CK1的上升沿RE重叠,因此主级100和从级200的启用/禁用操作被顺序执行。That is, since the falling edge FE of the first sub clock CK2-1 cannot be formed to overlap with the rising edge RE of the first clock CK1, the enable/disable operations of the master stage 100 and the slave stage 200 are sequentially performed.

如果主级100和从级200的启用/禁用操作没有被顺序执行,则第一数据ID不会被输出为第三数据OD2以匹配时钟信号,而是已经存储在主级100或从级200中的数据被输出为第三数据OD2,而不管第一数据ID如何。这种故障导致半导体电路1(例如,触发器)的采样窗口增加,并因此所述装置的操作可靠性劣化。If the enable/disable operations of the master stage 100 and the slave stage 200 are not sequentially performed, the first data ID is not output as the third data OD2 to match the clock signal, but has been stored in the master stage 100 or the slave stage 200 The data of are output as third data OD2 regardless of the first data ID. Such failure causes the sampling window of the semiconductor circuit 1 (eg, flip-flop) to increase, and thus the operational reliability of the device deteriorates.

但是,在半导体电路1中,通过上述构造来预先截断任何可能的故障,从而可提高半导体电路1的操作可靠性。However, in the semiconductor circuit 1, any possible failure is blocked in advance by the above-described configuration, so that the operational reliability of the semiconductor circuit 1 can be improved.

此外,主级100的时序歪斜(timing skew)对采样窗口的大小和对称性有很大影响。但是,根据半导体电路1的电路构造,可减小主级100的时序歪斜,从而可以以小的尺寸来对称地形成采样窗口。In addition, the timing skew of the main stage 100 has a great influence on the size and symmetry of the sampling window. However, according to the circuit configuration of the semiconductor circuit 1, the timing skew of the main stage 100 can be reduced, so that the sampling window can be symmetrically formed in a small size.

在如上构造的半导体电路1中,低采样窗口Tsw_low和高采样窗口Tsw_high已被分别测量为大约2至5ps和大约3至7ps。因此,可以确认,在低采样窗口Tsw_low与高采样窗口Tsw_high之间几乎不存在时间差,从而对称地形成采样窗口Tsw。由于采样窗口Tsw被对称地形成,因此可提高半导体电路1的可靠性。In the semiconductor circuit 1 constructed as above, the low sampling window Tsw_low and the high sampling window Tsw_high have been measured to be about 2 to 5 ps and about 3 to 7 ps, respectively. Therefore, it can be confirmed that there is almost no time difference between the low sampling window Tsw_low and the high sampling window Tsw_high, so that the sampling window Tsw is formed symmetrically. Since the sampling windows Tsw are formed symmetrically, the reliability of the semiconductor circuit 1 can be improved.

另一方面,主级100和从级200可具有不同阈值电压Vt。例如,主级100的阈值电压可低于从级200的阈值电压。如果主级100的阈值电压被构造为低于从级200的阈值电压,则可以以小的尺寸来形成采样窗口Tsw。下面的表2表示在阈值电压彼此不同的情况下的功率损耗与采样窗口Tsw的比率。On the other hand, the master stage 100 and the slave stage 200 may have different threshold voltages Vt. For example, the threshold voltage of the master stage 100 may be lower than the threshold voltage of the slave stage 200 . If the threshold voltage of the master stage 100 is configured to be lower than the threshold voltage of the slave stage 200, the sampling window Tsw may be formed in a small size. Table 2 below shows the ratio of power consumption to sampling window Tsw in the case where the threshold voltages are different from each other.

表2Table 2

High VtHigh Vt Low VtLow Vt Low Vt–High VtLow Vt–High Vt TswTsw 11 0.760.76 0.820.82 漏功率leakage power 11 5.785.78 2.32.3

参照表2,如果假设在主级100和从级200二者具有高阈值电压的情况下半导体电路1的采样窗口Tsw为1且半导体电路1的功率损耗为1,则在主级100和从级200二者具有低阈值电压的情况下,采样窗口Tsw增加至0.76倍,而功率损耗增加至5.789倍。由于随着阈值电压降低,电路可以以高速操作,因此采样窗口可减小。但是,由于漏电流增加至上述程度,因此功率损耗增加至5.78倍。Referring to Table 2, if it is assumed that the sampling window Tsw of the semiconductor circuit 1 is 1 and the power loss of the semiconductor circuit 1 is 1 in the case where both the master stage 100 and the slave stage 200 have high threshold voltages, then in the master stage 100 and the slave stage 200 with low threshold voltages, the sampling window Tsw is increased by a factor of 0.76, and the power loss is increased by a factor of 5.789. Since the circuit can operate at high speed as the threshold voltage decreases, the sampling window can be reduced. However, since the leakage current increases to the above-mentioned level, the power loss increases by a factor of 5.78.

通过使主级100和从级200的阈值电压彼此不同,可解决上述问题。例如,主级100的阈值电压可被构造为低于从级200的阈值电压。在这种情况下,与半导体电路1具有高阈值电压的情况相比,采样窗口增加至0.82倍,而功率损耗增加至2.3倍The above problem can be solved by making the threshold voltages of the master stage 100 and the slave stage 200 different from each other. For example, the threshold voltage of the master stage 100 may be configured to be lower than the threshold voltage of the slave stage 200 . In this case, compared to the case where the semiconductor circuit 1 has a high threshold voltage, the sampling window is increased by a factor of 0.82, and the power loss is increased by a factor of 2.3

与主机100和从级200二者具有低阈值电压的情况相比,可以确认,采样窗口以相似的方式减小且功率损耗减小为低于其一半。因此,如果主级100的阈值电压被构造为低于从级200的阈值电压,则功率损耗被最小化,且采样窗口减小。Compared to the case where both the master 100 and the slave 200 have low threshold voltages, it can be confirmed that the sampling window is reduced in a similar manner and the power consumption is reduced to less than half. Therefore, if the threshold voltage of the master stage 100 is configured to be lower than the threshold voltage of the slave stage 200, the power loss is minimized and the sampling window is reduced.

这里,主级100的阈值电压可表示在主级100中使用的有源装置的阈值电压(例如,第一晶体管MP11、第二晶体管MP12和第三晶体管MN11以及第一保持器41的阈值电压),从级200的阈值电压可表示在从级200中使用的有源装置的阈值电压(例如,第四晶体管MN21和第五晶体管MP21的阈值电压以及第二保持器42的阈值电压)。Here, the threshold voltage of the main stage 100 may represent threshold voltages of active devices used in the main stage 100 (eg, threshold voltages of the first transistor MP11 , the second transistor MP12 and the third transistor MN11 and the first keeper 41 ) , the threshold voltage of the slave stage 200 may represent the threshold voltage of the active devices used in the slave stage 200 (eg, the threshold voltages of the fourth transistor MN21 and the fifth transistor MP21 and the threshold voltage of the second keeper 42 ).

参照图4和图5,将描述根据另一实施例的半导体电路2。将省略对与上述描述重复的内容的解释,而将围绕实施例之间的不同点进行解释。4 and 5, a semiconductor circuit 2 according to another embodiment will be described. Explanation of the contents overlapping with the above description will be omitted, and explanation will be made focusing on the differences between the embodiments.

图4是半导体电路2的电路图,图5是示出图4的半导体电路2的操作时序的示图。FIG. 4 is a circuit diagram of the semiconductor circuit 2 , and FIG. 5 is a diagram illustrating an operation timing of the semiconductor circuit 2 of FIG. 4 .

参照图4,根据半导体电路2,与图2的半导体电路1不同,时钟产生单元310附加地包括第一延迟单元51。详细地讲,第一延迟单元51接收参考时钟CK并通过对参考时钟CK延迟一定时间而产生第一时钟CK1。为了对参考时钟CK进行延迟,第一延迟单元51可包括串联连接的两个反相器IN33和IN34。第一延迟单元51可通过对参考时钟CK进行两次反相来产生第一时钟CK1。与图2的时钟产生单元300相似,可使用第一时钟CK1产生第二时钟CK2。4 , according to the semiconductor circuit 2 , unlike the semiconductor circuit 1 of FIG. 2 , the clock generation unit 310 additionally includes a first delay unit 51 . In detail, the first delay unit 51 receives the reference clock CK and generates the first clock CK1 by delaying the reference clock CK by a certain time. In order to delay the reference clock CK, the first delay unit 51 may include two inverters IN33 and IN34 connected in series. The first delay unit 51 may generate the first clock CK1 by inverting the reference clock CK twice. Similar to the clock generating unit 300 of FIG. 2 , the second clock CK2 may be generated using the first clock CK1 .

由于时钟产生单元310包括第一延迟单元51,因此如在图5中所示,施加到主机100的第一时钟CK1的相位可被延迟。如果第一时钟CK1的相位被延迟,则第一数据ID和第一时钟CK1的上升沿RE和下降沿FE可被精确地区分,从而可防止半导体电路2的误差。由于第一时钟CK1的相位被延迟如第一大小W1一样大,因此构成第二时钟CK2的第一子时钟CK2-1和第二子时钟CK2-2的相位被延迟与第一大小W1一样大。Since the clock generating unit 310 includes the first delay unit 51, as shown in FIG. 5, the phase of the first clock CK1 applied to the host 100 may be delayed. If the phase of the first clock CK1 is delayed, the first data ID and the rising edge RE and the falling edge FE of the first clock CK1 can be accurately distinguished, so that errors of the semiconductor circuit 2 can be prevented. Since the phase of the first clock CK1 is delayed as much as the first size W1, the phases of the first sub-clock CK2-1 and the second sub-clock CK2-2 constituting the second clock CK2 are delayed as much as the first size W1 .

参照图6和图7,将描述根据本发明构思的另一示例实施例的半导体电路3。将省略对与上述描述重复的内容的解释,而将围绕实施例之间的不同点进行解释。6 and 7 , a semiconductor circuit 3 according to another example embodiment of the inventive concept will be described. Explanation of the contents overlapping with the above description will be omitted, and explanation will be made focusing on the differences between the embodiments.

图6是半导体电路3的电路图,图7是图6的第一时钟和第二时钟的时序图。FIG. 6 is a circuit diagram of the semiconductor circuit 3 , and FIG. 7 is a timing chart of the first clock and the second clock of FIG. 6 .

参照图6,半导体电路3在时钟产生单元320具有不同构造方面与图4的半导体电路2不同。详细地讲,按与图4的半导体电路2相似的方式,通过由第一延迟单元51对参考时钟CK的相位延迟与第一大小W1一样大,来产生第一时钟CK1。但是,在使用第一时钟CK1产生第一子时钟CK2-1的情况下,第二门G31被用于代替第六反相器IN31。第二门G31可以是例如NAND门。第二门G31通过对第一时钟CK1和参考时钟CK执行NAND逻辑运算来产生第一子时钟CK2-1。如图7中所示,与第一时钟CK1比较,第一子时钟CK2-1可缩短逻辑低电平的时间。当第一子时钟CK2-1处于逻辑低电平且第二子时钟CK2-2处于逻辑高电平时,从级200可被启用,并且,可使用第二门G31来缩短当从级200保持在启用状态下的时间。如果从级200的启用时间被缩短,则可防止主级100和从级200被同时启用或禁用。可通过第一子时钟CK2-1的反相来产生第二子时钟CK2-2。Referring to FIG. 6 , the semiconductor circuit 3 is different from the semiconductor circuit 2 of FIG. 4 in that the clock generating unit 320 has a different configuration. In detail, in a similar manner to the semiconductor circuit 2 of FIG. 4 , the first clock CK1 is generated by delaying the phase of the reference clock CK by the first delay unit 51 as large as the first magnitude W1. However, in the case where the first sub-clock CK2-1 is generated using the first clock CK1, the second gate G31 is used in place of the sixth inverter IN31. The second gate G31 may be, for example, a NAND gate. The second gate G31 generates the first sub-clock CK2-1 by performing a NAND logic operation on the first clock CK1 and the reference clock CK. As shown in FIG. 7 , the first sub clock CK2-1 may shorten the time of the logic low level compared with the first clock CK1. When the first sub-clock CK2-1 is at a logic low level and the second sub-clock CK2-2 is at a logic high level, the slave stage 200 may be enabled, and the second gate G31 may be used to shorten when the slave stage 200 is held at time in the enabled state. If the enable time of the slave stage 200 is shortened, the master stage 100 and the slave stage 200 can be prevented from being enabled or disabled at the same time. The second sub-clock CK2-2 may be generated by inversion of the first sub-clock CK2-1.

参照图8,将描述根据本发明构思的另一示例实施例的半导体电路4。将省略对与上述描述重复的内容的解释,而将围绕实施例之间的不同点进行解释。8 , a semiconductor circuit 4 according to another example embodiment of the inventive concept will be described. Explanation of the contents overlapping with the above description will be omitted, and explanation will be made focusing on the differences between the embodiments.

图8是半导体电路4的电路图。FIG. 8 is a circuit diagram of the semiconductor circuit 4 .

参照图8,图8的半导体电路4在时钟产生单元330包括第二延迟单元53的方面与图2的半导体电路1不同。第二延迟单元53可串联连接至第六反相器IN31。第二延迟单元53可通过串联连接两个反相器IN35和IN36而提供。8 , the semiconductor circuit 4 of FIG. 8 is different from the semiconductor circuit 1 of FIG. 2 in that the clock generation unit 330 includes the second delay unit 53 . The second delay unit 53 may be connected to the sixth inverter IN31 in series. The second delay unit 53 may be provided by connecting two inverters IN35 and IN36 in series.

第一时钟CK1与参考时钟CK相同。通过由第二延迟单元53对第一时钟CK1的相位延迟与第一大小W1一样大并由由第六反相器IN31对延迟的第一时钟CK进行反相,来产生第一子时钟CK2-1。The first clock CK1 is the same as the reference clock CK. The first sub clock CK2- 1.

参照图9,将描述根据本发明构思的另一示例实施例的半导体电路5。将省略对与上述描述重复的内容的解释。9 , a semiconductor circuit 5 according to another example embodiment of the inventive concept will be described. Explanation of content overlapping with the above description will be omitted.

图9是半导体电路5的电路图。FIG. 9 is a circuit diagram of the semiconductor circuit 5 .

参照图9,图9的半导体电路5在时钟产生单元340中的第二门G31可替换第六反相器IN31的方面与图8的半导体电路4不同。第二门G31可以是例如NAND门。第一时钟CK1可以与参考时钟CK相同。可通过经由第二延迟单元53对第一时钟CK1进行延迟,并对延迟的第一时钟CK1和第一时钟CK1执行NAND逻辑运算,而产生第一子时钟CK2-1。可通过对第一子时钟CK2-1的反相而产生第二子时钟CK2-2.9 , the semiconductor circuit 5 of FIG. 9 is different from the semiconductor circuit 4 of FIG. 8 in that the second gate G31 in the clock generating unit 340 can replace the sixth inverter IN31. The second gate G31 may be, for example, a NAND gate. The first clock CK1 may be the same as the reference clock CK. The first sub clock CK2-1 may be generated by delaying the first clock CK1 through the second delay unit 53 and performing a NAND logic operation on the delayed first clock CK1 and the first clock CK1. The second sub-clock CK2-2 may be generated by inverting the first sub-clock CK2-1.

参照图10,将描述根据本发明构思的另一示例实施例的半导体电路6。将省略对与上述描述重复的内容的解释。10 , a semiconductor circuit 6 according to another example embodiment of the inventive concept will be described. Explanation of content overlapping with the above description will be omitted.

图10是半导体电路6的电路图。FIG. 10 is a circuit diagram of the semiconductor circuit 6 .

参照图10,图10的半导体电路6在主级120和时钟产生电路350的方面与图2的半导体电路1不同。Referring to FIG. 10 , the semiconductor circuit 6 of FIG. 10 is different from the semiconductor circuit 1 of FIG. 2 in the main stage 120 and the clock generation circuit 350 .

详细地讲,图10的半导体单路6包括第一反相器IN11、第三门G12、第三电路105、第四电路107、第一保持器41和第二反相器IN12。第三电路105可连接至第三电压,且可包括第六晶体管MP13。第六晶体管MP13可以是例如PMOS晶体管。第六晶体管MP13可被由第三门G12产生的逻辑运算信号MCK2门控制。第三电压可以是例如电源电压。第三电路105可将第一节点N1的电平改变至逻辑高电平。即,第三电路105可将第二数据OD1的电平改变至逻辑低电平。In detail, the semiconductor single circuit 6 of FIG. 10 includes a first inverter IN11 , a third gate G12 , a third circuit 105 , a fourth circuit 107 , a first holder 41 and a second inverter IN12 . The third circuit 105 may be connected to the third voltage and may include a sixth transistor MP13. The sixth transistor MP13 may be, for example, a PMOS transistor. The sixth transistor MP13 may be gate-controlled by the logic operation signal MCK2 generated by the third gate G12. The third voltage may be, for example, the power supply voltage. The third circuit 105 may change the level of the first node N1 to a logic high level. That is, the third circuit 105 may change the level of the second data OD1 to a logic low level.

第四电路107可连接至第四电压,并且可包括第七晶体管MN12和第八晶体管MN13。第七晶体管MN12和第八晶体管MN13可串联连接,且可以是例如NMOS晶体管。例如,第四电压可以是地电压。第四电路107可将第一节点NI的电平改变至逻辑低电平。即,第四电路107可将第二数据OD1的电平改变至逻辑高电平。The fourth circuit 107 may be connected to a fourth voltage, and may include a seventh transistor MN12 and an eighth transistor MN13. The seventh transistor MN12 and the eighth transistor MN13 may be connected in series, and may be, for example, NMOS transistors. For example, the fourth voltage may be a ground voltage. The fourth circuit 107 may change the level of the first node NI to a logic low level. That is, the fourth circuit 107 may change the level of the second data OD1 to a logic high level.

第七晶体管MN12可被由第一反相器IN11反相的第一数据ID的反相数据IDB门控制。第八晶体管MN13被第一时钟CK1门控制。The seventh transistor MN12 may be gate-controlled by the inverted data IDB of the first data ID inverted by the first inverter IN11. The eighth transistor MN13 is gate-controlled by the first clock CK1.

第三门G12可执行第一数据ID和第一时钟CK1的逻辑运算,并且可将逻辑运算信号MCK2提供给第三电路105。第三门G12可以是例如NAND门,且可执行第一数据ID和第一时钟CK1的NAND逻辑运算。The third gate G12 may perform a logic operation of the first data ID and the first clock CK1 and may provide the logic operation signal MCK2 to the third circuit 105 . The third gate G12 may be, for example, a NAND gate, and may perform a NAND logic operation of the first data ID and the first clock CK1.

第三电路105和第四电路107可串联连接,并且可连接至第一节点N1。第二反相器IN12连接至第一节点N1,且对第一节点N1的信号进行反相以产生第二数据OD1。第一保持器41连接至第一节点N1,且可并联连接至第二反相器IN12。The third circuit 105 and the fourth circuit 107 may be connected in series, and may be connected to the first node N1. The second inverter IN12 is connected to the first node N1, and inverts the signal of the first node N1 to generate the second data OD1. The first holder 41 is connected to the first node N1, and may be connected in parallel to the second inverter IN12.

时钟产生单元350可包括第七反相器IN32和第八反相器IN37。第八反相器IN37通过对参考时钟CK的反相而产生第一时钟CK1。第一子时钟CK2-1可以与第一时钟CK1相同,并且第二子时钟CK2-2可通过由第七反相器IN32对第一子时钟CK2-1的反相而被产生。The clock generating unit 350 may include a seventh inverter IN32 and an eighth inverter IN37. The eighth inverter IN37 generates the first clock CK1 by inverting the reference clock CK. The first sub-clock CK2-1 may be the same as the first sub-clock CK1, and the second sub-clock CK2-2 may be generated by inverting the first sub-clock CK2-1 by the seventh inverter IN32.

图10的半导体电路6的从级200与图2的半导体电路1的从级相同。The slave stage 200 of the semiconductor circuit 6 of FIG. 10 is the same as the slave stage of the semiconductor circuit 1 of FIG. 2 .

图10的半导体电路6是通过图2的半导体电路1的反转的而形成的电路。换言之,图2的半导体电路1以与图10的半导体电路6相似方式进行操作,但是其电路构造与图10的半导体电路6的电路构造相反。详细地讲,第三门G12由NAND门而不是NOR门形成;由第三门G12门控制的第三电路105连接到电源电压且包括PMOS晶体管。第四电路107包括两个NMOS晶体管且连接到地电压。此外,提供给主级120的第一时钟CK1通过对参考时钟CK的反相而被产生。The semiconductor circuit 6 of FIG. 10 is a circuit formed by inversion of the semiconductor circuit 1 of FIG. 2 . In other words, the semiconductor circuit 1 of FIG. 2 operates in a similar manner to the semiconductor circuit 6 of FIG. 10 , but its circuit configuration is opposite to that of the semiconductor circuit 6 of FIG. 10 . In detail, the third gate G12 is formed of a NAND gate instead of a NOR gate; the third circuit 105 gate-controlled by the third gate G12 is connected to the supply voltage and includes a PMOS transistor. The fourth circuit 107 includes two NMOS transistors and is connected to ground voltage. Also, the first clock CK1 supplied to the main stage 120 is generated by inverting the reference clock CK.

由于可从上述内容推导出:图10的半导体电路6具有与图2的半导体电路1的电路构造不同的电路构造,但是图10的半导体电路6以与图2的半导体电路1相似方式进行操作,因此将省略对图10的半导体电路6的操作的解释。Since it can be deduced from the above that the semiconductor circuit 6 of FIG. 10 has a circuit configuration different from that of the semiconductor circuit 1 of FIG. 2 , but the semiconductor circuit 6 of FIG. 10 operates in a similar manner to the semiconductor circuit 1 of FIG. 2 , Therefore, the explanation of the operation of the semiconductor circuit 6 of FIG. 10 will be omitted.

参照图11,将描述根据本发明构思的另一示例实施例的半导体电路7。将省略对与上述描述重复的内容的解释11 , a semiconductor circuit 7 according to another example embodiment of the inventive concept will be described. Explanation of content overlapping with the above description will be omitted

图11是半导体电路7的电路图。FIG. 11 is a circuit diagram of the semiconductor circuit 7 .

图11的半导体电路7在时钟产生单元360方面与图10的半导体电路6不同。The semiconductor circuit 7 of FIG. 11 is different from the semiconductor circuit 6 of FIG. 10 in the clock generation unit 360 .

参照图11,时钟产生单元360包括第二延迟单元53。即,第一时钟CK1通过对参考时钟CK的反相而被产生,第一子时钟CK2-1通过由第二延迟单元53对第一时钟CK1的相位进行延迟而被产生。第二子时钟CK2-2可通过对第一子时钟CK2-1的反相而被产生。第二延迟单元53可通过两个反相器IN35和IN36的串联连接而被形成。Referring to FIG. 11 , the clock generation unit 360 includes the second delay unit 53 . That is, the first clock CK1 is generated by inverting the reference clock CK, and the first sub-clock CK2 - 1 is generated by delaying the phase of the first clock CK1 by the second delay unit 53 . The second sub-clock CK2-2 may be generated by inverting the first sub-clock CK2-1. The second delay unit 53 may be formed by a series connection of two inverters IN35 and IN36.

参照图12,将描述根据本发明构思的另一示例实施例的半导体电路8。将省略对与上述描述重复的内容的解释12 , a semiconductor circuit 8 according to another example embodiment of the inventive concept will be described. Explanation of content overlapping with the above description will be omitted

图12是半导体电路8的电路图。FIG. 12 is a circuit diagram of the semiconductor circuit 8 .

图12的半导体电路8在时钟产生单元370方面与图10的半导体电路6不同。详细地讲,参照图12,时钟产生单元360可包括第三延迟单元55。第三延迟单元55可包括第九反相器IN38和第四门G32。The semiconductor circuit 8 of FIG. 12 is different from the semiconductor circuit 6 of FIG. 10 in the clock generation unit 370 . In detail, referring to FIG. 12 , the clock generation unit 360 may include the third delay unit 55 . The third delay unit 55 may include a ninth inverter IN38 and a fourth gate G32.

第一时钟CK1通过由第八反相器IN37对参考时钟CK进行反相而被产生。此外,第一子时钟CK2-1通过经由第四门G32对参考时钟CK和对第一时钟CK1进行反相而获得的值执行逻辑运算而被产生。例如,第四门G32可以是NAND门,且可通过对参考时钟CK和对第一时钟CK1进行反相而获得的值执行逻辑运算而产生第一子时钟CK2-1。The first clock CK1 is generated by inverting the reference clock CK by the eighth inverter IN37. Also, the first sub clock CK2-1 is generated by performing a logical operation on the reference clock CK and a value obtained by inverting the first clock CK1 via the fourth gate G32. For example, the fourth gate G32 may be a NAND gate, and may generate the first sub clock CK2-1 by performing a logical operation on the reference clock CK and a value obtained by inverting the first clock CK1.

参照图13,将描述包括根据本发明构思的一些示例实施例的半导体电路的半导体系统10。13, a semiconductor system 10 including a semiconductor circuit according to some example embodiments of the inventive concepts will be described.

图13是半导体系统10的框图。FIG. 13 is a block diagram of the semiconductor system 10 .

半导体系统10可包括发送器20和接收器30。发送器20可使用参考时钟将第一数据ID发送至接收器30。接收器30可接收第一数据ID,并且可使用参考时钟CK处理或执行第一数据ID的采样。如上所述的半导体电路1至8中的一个半导体电路可被形成在接收器30的输入端处。接收器30的输入端可接收第一数据ID和参考时钟CK,并将第三数据OD2提供给接收器30。The semiconductor system 10 may include a transmitter 20 and a receiver 30 . The transmitter 20 may transmit the first data ID to the receiver 30 using the reference clock. The receiver 30 may receive the first data ID, and may process or perform sampling of the first data ID using the reference clock CK. One of the semiconductor circuits 1 to 8 as described above may be formed at the input terminal of the receiver 30 . The input terminal of the receiver 30 may receive the first data ID and the reference clock CK, and provide the third data OD2 to the receiver 30 .

这里,半导体系统10可以是例如处理器,但不限于此。半导体系统10可被应用于用来发送数据的半导体装置。Here, the semiconductor system 10 may be, for example, a processor, but is not limited thereto. The semiconductor system 10 can be applied to a semiconductor device for transmitting data.

参考图14,将描述可采用上述半导体电路1至8的计算系统。14, a computing system that can employ the above-described semiconductor circuits 1 to 8 will be described.

图14是示出计算系统501的构造的框图。FIG. 14 is a block diagram showing the configuration of the computing system 501 .

参照图14,计算系统501包括中央处理单元500、图形加速端口(AGP)装置510、主存储器600、存储器(例如,SSD或HDD)540、北桥520、南桥530、键盘控制器560和打印机控制器550。14, a computing system 501 includes a central processing unit 500, an accelerated graphics port (AGP) device 510, a main memory 600, a memory (eg, SSD or HDD) 540, a north bridge 520, a south bridge 530, a keyboard controller 560, and a printer control device 550.

图14中示出的计算系统501可以是个人计算机或笔记本计算机。但是,本发明构思不限于此,且计算系统501的示例可不受限制地被修改。The computing system 501 shown in FIG. 14 may be a personal computer or a notebook computer. However, the inventive concept is not limited thereto, and the example of the computing system 501 may be modified without limitation.

在计算系统501中,中央处理单元500、AGP装置510和主存储器600可连接到北桥520。但是,本发明构思不限于此,并且北桥520可被修改为包括在中央处理单元500中。In computing system 501 , central processing unit 500 , AGP device 510 and main memory 600 may be connected to north bridge 520 . However, the inventive concept is not limited thereto, and the north bridge 520 may be modified to be included in the central processing unit 500 .

AGP可以是使三维(3D)图形表达加速实现的总线标准,并且AGP装置510可包括再现监视器图像的视频卡。AGP may be a bus standard that enables accelerated implementation of three-dimensional (3D) graphics, and AGP device 510 may include a video card that reproduces monitor images.

中央处理单元500可执行驱动计算系统101所需的各种类型的逻辑运算,并且可执行OS和应用程序。半导体电路1至8中的至少一个可被采用为中央处理单元500的一部分。The central processing unit 500 may perform various types of logical operations required to drive the computing system 101, and may execute OS and application programs. At least one of the semiconductor circuits 1 to 8 may be employed as part of the central processing unit 500 .

主存储器600可从存储器540加载执行中央处理单元500的操作所需的数据以存储加载的数据。The main memory 600 may load data required to perform operations of the central processing unit 500 from the memory 540 to store the loaded data.

存储器540、键盘控制器560、打印机控制器550和各种类型的外围装置(未示出)可被连接到南桥530。A memory 540 , a keyboard controller 560 , a printer controller 550 and various types of peripheral devices (not shown) may be connected to the south bridge 530 .

存储器540是存储文件数据等的大容量数据存储器,且可通过例如HDD或SSD来实现。但是,本发明构思不限于这种示例。The storage 540 is a large-capacity data storage that stores file data and the like, and can be implemented by, for example, an HDD or an SSD. However, the inventive concept is not limited to such an example.

此外,计算系统501具有存储器540连接到南桥530的结构,但是本发明构思不限于此。可以以存储器540连接到北桥520或存储器540直接连接到中央处理单元500的方式来修改所述结构。Also, the computing system 501 has a structure in which the memory 540 is connected to the south bridge 530, but the inventive concept is not limited thereto. The structure can be modified in such a way that the memory 540 is connected to the north bridge 520 or the memory 540 is connected directly to the central processing unit 500 .

然后,将参照图15描述可采用半导体电路1至8的电子系统900。Then, an electronic system 900 that can employ the semiconductor circuits 1 to 8 will be described with reference to FIG. 15 .

图15是示出可采用半导体电路1至8的电子系统900的构造的框图。FIG. 15 is a block diagram showing the configuration of an electronic system 900 in which the semiconductor circuits 1 to 8 can be employed.

参照图15,电子系统900可包括存储器系统902、处理器904、RAM 906和用户接口908。Referring to FIG. 15 , electronic system 900 may include memory system 902 , processor 904 , RAM 906 and user interface 908 .

存储器系统902、处理器904、RAM 906和用户接口908可使用总线910彼此执行数据通信。Memory system 902 , processor 904 , RAM 906 and user interface 908 may use bus 910 to perform data communication with each other.

处理器904可用于执行程序并控制电子系统900,并且RAM 906可被用做处理器904的操作存储器。处理器904可包括半导体电路1至8中的至少一个作为构成元件的一部分。处理器904和RAM 906可被实现为封装为一个半导体装置或半导体封装件。The processor 904 may be used to execute programs and control the electronic system 900 , and the RAM 906 may be used as the operating memory of the processor 904 . The processor 904 may include at least one of the semiconductor circuits 1 to 8 as a part of the constituent elements. The processor 904 and RAM 906 may be implemented as packaged as one semiconductor device or semiconductor package.

用户接口908可被用于将数据输入至电子系统900或从电子系统900输出数据。User interface 908 may be used to input data to and output data from electronic system 900 .

存储器系统902可存储用于处理器904的操作的代码、由处理器904处理的数据或从外部输入的数据。存储器系统902可包括用于其操作的单独控制器,且可被构造为附加地包括纠错块。纠错块可被构造为使用纠错码(ECC)检测和纠正存储在存储器系统902中的数据的错误。The memory system 902 may store codes for operations of the processor 904, data processed by the processor 904, or data input from the outside. Memory system 902 may include a separate controller for its operation, and may be configured to additionally include an error correction block. Error correction blocks may be configured to detect and correct errors in data stored in memory system 902 using error correction codes (ECC).

存储器系统902可被集成至一个半导体装置。示例性地,存储器系统902可被集成至一个半导体装置以构成存储卡。例如,存储器系统902可被集成至一个半导体装置以构造存储卡,诸如PC卡(个人计算机存储卡国际协会(PCMCIA))、紧凑闪存(CF)卡、智能媒体卡(SM或SMC)、记忆棒、多媒体卡(MMC、RS-MMC、MMCmicro)、SD卡(SD、miniSD、microSD或SDHC)、通用闪速存储装置(UFS)等。The memory system 902 may be integrated into one semiconductor device. Illustratively, the memory system 902 may be integrated into one semiconductor device to constitute a memory card. For example, the memory system 902 may be integrated into a semiconductor device to construct a memory card, such as a PC Card (Personal Computer Memory Card International Association (PCMCIA)), Compact Flash (CF) card, Smart Media Card (SM or SMC), Memory Stick , Multimedia Card (MMC, RS-MMC, MMCmicro), SD Card (SD, miniSD, microSD or SDHC), Universal Flash Storage (UFS), etc.

图15所示出的电子系统900可被应用于各种电器的电子控制装置。图16是示出图15的电子装置应用于智能电话的示例的示图。在(图15的)电子系统900被应用于智能电话1000的情况下,半导体电路1至8中的至少一个可被采用为应用处理器(AP)的部分构成元件。The electronic system 900 shown in FIG. 15 can be applied to electronic control devices of various electric appliances. FIG. 16 is a diagram illustrating an example in which the electronic device of FIG. 15 is applied to a smartphone. In the case where the electronic system 900 (of FIG. 15 ) is applied to the smartphone 1000 , at least one of the semiconductor circuits 1 to 8 may be employed as a partial constituent element of an application processor (AP).

此外,(图15的)电子系统900可被提供为电子装置(诸如,计算机、超移动PC(UMPC)、工作站、上网本、个人数字助理(PDA)、便携式计算机、上网平板、无线电话、移动电话、智能手机、电子书、便携式多媒体播放器(PMP)、便携式游戏机、导航装置、黑盒、数码相机、3维电视接收器、数字音频记录器、数字音频播放器、数字图像记录器、数字图像播放器、数字视频记录器、数字视频播放器、可在无线环境下发送和接收信息的装置、构成家庭网络的各种电子装置之一、构成计算机网络的各种电子装置之一、构成电信网络的各种电子装置之一、RFID装置)的各种构成元件之一或构成计算系统的各种构成元件之一。Additionally, the electronic system 900 (of FIG. 15) may be provided as an electronic device such as a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a nettable, a wireless phone, a mobile phone , smartphones, e-books, portable multimedia players (PMP), portable game consoles, navigation devices, black boxes, digital cameras, 3D TV receivers, digital audio recorders, digital audio players, digital image recorders, digital Image player, digital video recorder, digital video player, device that can send and receive information in a wireless environment, one of various electronic devices that constitute a home network, one of various electronic devices that constitute a computer network, one of various electronic devices that constitute a telecommunication One of various electronic devices of a network, one of various constituent elements of an RFID device) or one of various constituent elements of a computing system.

虽然以示意性目的已经描述了本发明构思的示例实施例,但是本领域技术人员将清楚的是,在不脱离所附权利要求公开的本发明构思的范围和精神的前提下,可以进行各种修改、添加和替换。While example embodiments of the inventive concept have been described for illustrative purposes, it will be apparent to those skilled in the art that various modifications are possible without departing from the scope and spirit of the inventive concept as disclosed in the accompanying claims. Modifications, additions and substitutions.

Claims (18)

1. A flip-flop, comprising:
a first circuit connected between a first voltage terminal and a first node and configured to change a voltage of the first node to a first level of the first voltage terminal according to first data and a first clock;
a first gate configured to perform a logical operation on first data and a first clock;
a second circuit connected between the first node and a second voltage terminal and configured to change a voltage of the first node to a second level of the second voltage terminal according to an output of the logical operation,
wherein the second clock provided to the slave stage of the flip-flop comprises a first sub-clock and a second sub-clock, the second sub-clock being an inverse of the first sub-clock,
wherein the second clock is generated based on the first clock,
wherein the first circuit comprises:
a first inverter configured to invert the first data;
a first transistor and a second transistor connected in series between a first voltage terminal and a first node and configured to receive inverted first data and a first clock, respectively, wherein the second circuit includes:
and a third transistor connected between the first node and the second voltage terminal and configured to receive an output of the logical operation, wherein the first clock is generated by the reference clock, and the first sub-clock is generated by performing a NAND logical operation on the reference clock and the first clock.
2. The flip-flop of claim 1, further comprising:
a clock generation unit configured to receive a reference clock and generate a first clock and a second clock.
3. The flip-flop according to claim 2, wherein the clock generation unit is configured to generate the first sub-clock by inverting the first clock.
4. The flip-flop of claim 2, wherein the clock generation unit comprises:
a first delay unit configured to delay a phase of a first clock and generate a second clock using the delayed first clock.
5. The flip-flop of claim 4, wherein the clock generation unit is configured to generate the first sub-clock by performing a NAND logic operation on the reference clock and the delayed first clock.
6. The flip-flop of claim 4, wherein the first clock and the reference clock are the same.
7. The flip-flop according to claim 2, wherein the clock generation unit is configured to generate the first clock by delaying a phase of the reference clock.
8. The flip-flop according to claim 2, wherein the clock generation unit is configured to generate the first clock by inverting the reference clock.
9. The flip-flop of claim 8, wherein the clock generation unit is configured to generate the first sub-clock by performing a NAND logic operation on the inverted signal of the first clock and the reference clock.
10. The flip-flop of claim 1, further comprising:
a keeper circuit configured to hold a voltage of the first node based on the first clock and an output of the logical operation.
11. A semiconductor circuit, comprising:
a master circuit and a slave circuit configured to receive a first clock and a second clock, respectively, the first clock and the second clock having different phases,
wherein the main circuit comprises a first transistor, a second transistor, a third transistor, a first inverter and a first gate,
wherein the first transistor, the second transistor and the third transistor are connected in series between a first voltage terminal and a second voltage terminal,
wherein the first inverter is configured to invert input data and gate the first transistor,
wherein the first gate is configured to gate control the third transistor, the first gate is configured to perform a logic operation on the input data and the first clock,
wherein the second transistor is configured to receive a first clock,
wherein the second clock includes a first sub-clock and a second sub-clock, the second sub-clock being an inverse of the first sub-clock,
wherein the first clock is generated by a reference clock, and the first sub-clock is generated by performing a NAND logic operation on the reference clock and the first clock.
12. The semiconductor circuit according to claim 11, wherein a threshold voltage of the master circuit is lower than a threshold voltage of the slave circuit.
13. The semiconductor circuit according to claim 11, wherein the first transistor is connected to a first voltage terminal, the third transistor is connected to a second voltage terminal, and the second transistor is located between the first transistor and the third transistor.
14. The semiconductor circuit according to claim 13, wherein the first transistor and the second transistor are configured to change input data to a first level, and the third transistor is configured to change input data to a second level.
15. The semiconductor circuit of claim 11, further comprising:
a keeper circuit configured to hold a voltage of a node to which the second transistor and the third transistor are connected, based on the first clock and an output of the logical operation.
16. The semiconductor circuit according to claim 11, wherein the logical operation is a NOR logical operation.
17. The semiconductor circuit according to claim 16, wherein the first transistor and the second transistor are PMOS transistors, and wherein the third transistor is an NMOS transistor.
18. The semiconductor circuit according to claim 13, wherein the first voltage of the first voltage terminal is a power supply voltage, and the second voltage of the second voltage terminal is a ground voltage.
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