CN104579298B

CN104579298B - Flip-flop and semiconductor circuit

Info

Publication number: CN104579298B
Application number: CN201410548796.4A
Authority: CN
Inventors: 拉赫·辛哈; 金珉修; 金正熙
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2013-10-16
Filing date: 2014-10-16
Publication date: 2020-03-13
Anticipated expiration: 2034-10-16
Also published as: KR102116722B1; TW201517519A; US20150102847A1; CN104579298A; JP2015080202A; TWI648953B; KR20150044247A; US9503062B2

Abstract

A flip-flop and a semiconductor circuit are provided. An example embodiment discloses a flip-flop including: a first inverter configured to invert the first data; a first transistor and a second transistor connected in series with each other and configured to receive inverted first data and a first clock, respectively; a first gate configured to perform a logical operation on first data and a first clock; a third transistor configured to receive an output of the logical operation. The second transistor and the third transistor are connected to a first node.

Description

Flip-flop and semiconductor circuit

The present application is based on and claims the priority of korean patent application No. 10-2013-0123398, filed 2013, month 10 and 16, to the korean intellectual property office, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

The present inventive concept relates to a semiconductor circuit and a semiconductor system.

Background

As one of the semiconductor devices, a flip-flop operates to store input data in response to a clock signal and sequentially transfer the stored data. Multiple offenders may be used to transmit data.

On the other hand, with the trend of high-speed electronic products, the speed of clock signals supplied to flip-flops has gradually increased. In order to reliably operate a plurality of flip-flops in such an environment, no timing failure needs to occur during the operation of the flip-flops regardless of the high-speed clock signal.

Disclosure of Invention

The inventive concept provides a semiconductor circuit in which a sampling window is symmetrically formed in a small size and thus product reliability is improved.

Further, the inventive concept provides a semiconductor system in which a sampling window is symmetrically formed in a small size and thus product reliability is improved.

Additional advantages, objects, and features of the inventive concept will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the inventive concept.

In one example embodiment of the inventive concepts, there is provided a flip-flop including: a first inverter configured to invert the first data; a first transistor and a second transistor connected in series with each other and configured to receive inverted first data and a first clock, respectively; a third transistor; a first gate configured to perform a logical operation on first data and a first clock; a third transistor configured to receive an output of the logical operation, wherein the second transistor and the third transistor are connected to the first node.

In one example embodiment of the inventive concepts, there is provided a semiconductor circuit including: a master circuit and a slave circuit configured to receive a first clock and a second clock, respectively, the first clock and the second clock having different phases from each other, wherein the master circuit includes: the circuit includes a first transistor, a second transistor, a third transistor, a first inverter, and a first gate, wherein the first transistor, the second transistor, and the third transistor are connected in series between a first voltage terminal and a second voltage terminal, wherein the first inverter is configured to invert input data and gate the first transistor, wherein the first gate is configured to gate the third transistor, wherein the first gate is configured to perform a logical operation on the input data and a first clock, and wherein the second transistor is configured to receive the first clock.

In an embodiment of the inventive concept, there is provided a semiconductor system including: a transmitter configured to transmit first data using a reference clock; a receiver configured to receive first data, wherein the receiver comprises: a clock generation unit configured to generate a first clock and a second clock having different phases using a reference clock; a main circuit configured to receive first data and a first clock and output second data; and a slave circuit configured to receive the second data and the second clock and output third data, wherein the master circuit includes a first circuit between the first voltage terminal and the first node for changing the second data to a first level, a second circuit between the first node and the second voltage terminal for changing the second data to a second level, and the second circuit is configured to operate according to a logic operation signal of the first data and the second clock.

In another example embodiment of the inventive concepts, there is provided a semiconductor circuit including: a clock generation unit configured to generate a first clock and a second clock different from the first clock using a reference clock; a main circuit configured to receive first data and a first clock and output second data; a slave circuit configured to receive second data and a second clock and output third data, wherein the second clock includes a first sub-clock and a second sub-clock, wherein the master circuit includes: a first PMOS transistor connected to a power supply voltage; a second PMSO transistor connected in series to the first PMOS transistor and controlled by the first clock gate; a first NMOS transistor connected to the second PMOS transistor in series and connected to a ground voltage terminal; a first inverter configured to gate control the first PMOS transistor by inverting input data; a NOR gate configured to gate control the first NMOS transistor by performing a NOR logic operation with respect to the first clock and the input data; the clock generation unit includes: a delay unit configured to delay a phase of a reference clock to generate a first clock; and a NAND gate configured to perform a NAND logical operation with respect to the first clock and the reference clock to generate the first sub-clock, and a second inverter configured to invert the first sub-clock to generate the second sub-clock.

At least one example embodiment discloses a clock generation circuit configured to generate a first clock and a second clock, a master circuit configured to receive first data, perform a logical operation on the first clock and the first data, and generate first output data based on the logical operation, and a slave circuit configured to generate second output data based on the first output data and the second clock.

Drawings

The above and other objects, features and advantages of the present inventive concept will become more apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

fig. 1 is a block diagram of a semiconductor circuit according to an example embodiment of the inventive concepts;

fig. 2 is a circuit diagram of a semiconductor circuit according to an example embodiment of the inventive concept;

fig. 3 is a diagram for explaining an operation of a semiconductor circuit according to an example embodiment of the inventive concepts;

fig. 4 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concept;

fig. 5 is a diagram showing operation timings of the semiconductor circuit of fig. 4;

fig. 6 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concepts;

FIG. 7 is a timing diagram of the first clock and the second clock of FIG. 6;

fig. 8 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concepts;

fig. 9 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concepts;

fig. 10 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concepts;

fig. 11 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concepts;

fig. 12 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concepts;

fig. 13 is a block diagram of a semiconductor system including a semiconductor circuit according to some example embodiments of the inventive concepts;

fig. 14 is a block diagram illustrating a configuration of a computing system that may employ semiconductor circuits according to some example embodiments of the inventive concepts;

fig. 15 is a block diagram illustrating a configuration of an electronic system that may employ semiconductor circuits according to some example embodiments of the inventive concepts;

fig. 16 is a diagram illustrating an example of applying the electronic system of fig. 15 to a smartphone.

Detailed Description

The inventive concept will now be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the inventive concept are shown. The inventive concept may, however, be embodied in different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. Like reference numerals refer to like elements throughout the specification. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

The use of the singular or similar referents in the context of describing the concepts of the invention (especially in the context of the following claims) is to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The terms "comprising," "having," "including," and "containing" are to be construed as open-ended terms (i.e., meaning "including, but not limited to,") unless otherwise noted.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs. It is noted that any and all examples, or terms provided, used herein are intended merely to better illustrate the inventive concepts and do not limit the scope of the inventive concepts, unless otherwise defined. Furthermore, unless otherwise defined, all terms defined in general dictionaries should not be interpreted excessively.

The inventive concept will be described with reference to perspective, sectional and/or plan views illustrating example embodiments thereof. Accordingly, the outline of the exemplary diagram may be modified according to manufacturing techniques and/or capabilities. That is, the exemplary embodiments of the inventive concept are not intended to limit the scope of the inventive concept, but to cover all changes and modifications that may be made due to changes in manufacturing techniques. Thus, the regions illustrated in the drawings are illustrated in schematic form, and the shapes of the regions are illustrated by way of illustration and not by way of limitation.

Hereinafter, a semiconductor circuit 1 according to an exemplary embodiment of the inventive concept will be described with reference to fig. 1 and 2.

Fig. 1 is a block diagram of a semiconductor circuit 1 according to an exemplary embodiment of the inventive concept, and fig. 2 is a circuit diagram of the semiconductor circuit 1 according to an exemplary embodiment of the inventive concept.

Referring to fig. 1, a semiconductor circuit 1 includes a master stage 100, a slave stage 200, and a clock generation unit 300.

For example, the semiconductor circuit 1 may receive input data and perform sampling of the received data. However, the inventive concept is not limited thereto. In the following, the semiconductor device 1 is exemplarily shown to be a master-slave flip-flop. However, the inventive concept is not limited thereto, and the technical concept of the inventive concept may be modified and applied to other semiconductor devices without limitation.

The main stage 100 receives the first data ID and the first clock CK 1. The main stage 100 may receive the first data ID based on the first clock CK1 and output the second data OD 1. The first clock CK1 may be provided from the clock generation unit 300.

The slave stage 200 receives a second clock CK2 and second data OD 1. The slave stage 200 may receive the second data OD1 based on the second clock CK2 and output the third data OD 2. In this example embodiment, the second clock CK2 may also be provided from the clock generation unit 300. Here, the first data ID may be input data input to the semiconductor circuit 1, the second data OD1 may be first output data output from the master stage 100, and the third data OD2 may be second output data output from the slave stage 200.

On the other hand, the second clock CK2 provided to the slave stage 200 may include a first sub-clock CK2-1 and a second sub-clock CK2-2. The main stage 100 may use the first clock CK1 and a logical operation signal MCK1, wherein the logical operation signal MCK1 is obtained by performing a logical operation on the first clock CK1 and the first data ID, which will be described later. Hereinafter, a configuration of dividing the second clock CK2 into a plurality of sub-clocks and applying the divided sub-clocks to the slave stage 200 will be described, but the inventive concept is not limited thereto.

Referring to fig. 2, the main stage 100 may include, for example, a first circuit 101, a second circuit 103, a first inverter IN11, a first gate G11, a second inverter IN12, and a first keeper (keeper) 41.

The first circuit 101 and the second circuit 103 are connected in series around the first node N1. The first circuit 101 is connected to a first voltage terminal and the second circuit 103 is connected to a second voltage terminal. For example, the first voltage may be a power supply voltage and the second voltage may be a ground voltage, but is not limited thereto.

The first circuit 101 may be formed by connecting the first transistor MP11 and the second transistor MP12 in series. The second circuit 103 may include a third transistor MN 11. For example, the first transistor MP11 may be a PMOS transistor, the second transistor MP12 may be a PMOS transistor, and the third transistor MN11 may be an NMOS transistor. The first circuit 101 may receive the first data ID and the first clock CK1, and may change the second data OD1 by the received data. The second circuit 103 may receive a logically operated signal through the first gate G11 to operate and change the second data OD 1. In detail, the first circuit 101 may change the second data OD1 to a first level, and the second circuit 103 may change the second data OD1 to a second level. For example, the first level may be a logic low level and the second level may be a logic high level. The details thereof will be described later.

The first inverter IN11 inverts the first data ID and generates inverted data IDB. The first data ID may be, for example, input data received by the main stage 100. The first inverter IN11 may be connected to the first transistor MP11, and the inverted data IDB of the first data ID may be provided to the first transistor MP 11. The inverted data IDB may gate the first transistor MP 11.

The second transistor MP12 may receive the first clock CK1 and may be controlled by the first clock CK 1.

The first gate G11 receives the first data ID and the first clock CK 1. The first gate G11 generates a logical operation signal MCK1 by performing a first logical operation of the received first data ID and the first clock CK1, and provides the generated logical operation signal MCK1 to the third transistor MN 11. The first gate G11 may be, for example, a NOR (NOR) gate. Thus, the first logical operation may be a NOR logical operation. The logic operation signal MCK1 may gate the third transistor MN 11.

The second inverter IN12 may be connected between the first node N1 and the second node N2. The second inverter IN12 may invert the signal of the first node N1 and output the inverted signal to the second node N2, and the output signal may be the second data OD 1.

The first holder 41 may be connected between the first node N1 and the second node N2. The first holder 41 may be connected IN parallel to the second inverter IN 12. The first holder 41 can operate using the first clock CK1 and the logic operation signal MCK 1. The first holder 41 may latch the second data OD 1. Therefore, the second data OD1 can be kept constant without external disturbance.

The slave stage 200 may include a fourth transistor MN21, a fifth transistor MP21, a second keeper 42, and a third inverter IN 21.

The fourth transistor MN21 and the fifth transistor MP21 may be connected in parallel between the second node N2 and the third node N3. For example, the fourth transistor MN21 may be an NMOS transistor, and the fifth transistor MP21 may be a PMOS transistor. The fourth transistor MN21 can be controlled by the second sub-clock CK2-2, and the fifth transistor MP21 can be controlled by the first sub-clock CK 2-1. The fourth transistor MN21 and the fifth transistor MP21 may determine whether the second data OD1 is transferred to the third junction N3.

The third inverter IN21 is connected to the third node N3 and inverts a signal transmitted to the third node N3. The inverted signal inverted by the third inverter IN21 may be the third data OD 2.

The second holder 42 may be connected to a third contact N3. The second keeper 42 may include a fourth inverter IN22 and a fifth inverter IN 23. The fourth inverter IN22 and the fifth inverter IN23 may be connected IN series, and the fourth inverter IN22 may receive the first sub-clock CK2-1 and the second sub-clock CK2-2 to operate. The second keeper 42 may latch the signal provided to the third contact N3.

Referring to fig. 1, the clock generation unit 300 may receive a reference clock CK and generate a first clock CK1 and a second clock CK2 from the reference clock CK. The second clock CK2 may include a first sub-clock CK2-1 and a second sub-clock CK2-2.

In this example embodiment, the first clock CK1 and the second clock CK2 may be different from each other. In other words, the phase of the first clock CK1 is different from the phase of the second clock CK 2. In detail, the first clock CK1 and the second clock CK2 may be generated such that at least one of edges of the first clock CK1 and the second clock CK2 becomes a non-overlapping edge. In more detail, the first clock CK1 and the second clock CK2 may be generated such that a first edge of the first clock CK1 does not overlap with a first edge of the second clock CK2, and at least a portion of a second edge of the first clock CK1 overlaps with a second edge of the second clock CK 2. For example, the first edge may be a rising edge RE and the second edge may be a falling edge FE, but is not limited thereto. The first edge may be a falling edge and the second edge may be a rising edge.

Referring to fig. 2, the clock generation unit 300 may include a sixth inverter IN31 and a seventh inverter IN 32.

In the semiconductor circuit 1 of fig. 2, the first clock CK1 may be the same as the reference clock CK. Accordingly, the clock generation unit 300 may provide the reference clock to the main stage 100 as it is.

The first sub-clock CK2-1 may be generated by inverting the reference clock CK by the sixth inverter IN 31. IN addition, the second sub-clock CK2-2 may be generated by inverting the first sub-clock CK2-1 by the seventh inverter IN 32.

The operation of the semiconductor circuit 1 according to an exemplary embodiment of the inventive concept will be described with reference to fig. 3 and table 1.

Fig. 3 and table 1 are a diagram and a table explaining the operation of the semiconductor circuit 1. Fig. 3 is a diagram showing the operation timing of the semiconductor circuit 1, and table 1 is a table showing the output of the first gate G11 according to its input.

TABLE 1

Before explaining in detail the operation of the semiconductor circuit 1, some terms that may represent the operating characteristics of the flip-flop circuit will be described.

First, the sampling window Tsw represents the time required to hold the input signal in order for the flip-flop circuit to read the data value of the input signal. The sampling window may be represented as equation 1 below.

[ equation 1]

Sampling window (Tsw) ═ data setup time (Tsetup) + data hold time (Thold)

Here, the data setup time Tsetup represents a time provided in advance for the flip-flop circuit to accurately read a data value from an input signal. That is, the data setup time Tsetup is an index representing a time required for the flip-flop circuit to prepare for a read operation before the clock signal is applied in order for the flip-flop circuit to accurately read a data value from an input signal.

In the inventive concept, the data setup time Tsetup represents a time that should be provided in advance in order to accurately read the value of the first data ID when the second data OD1 is changed by the first data ID. The data setup time Tsetup may include a data setup rise time Tsr and a data setup fall time Tsf. The data setup rising time Tsr represents a time that should be provided in order to accurately read the rising edge RE of the first data ID (i.e., in order to accurately read a logic high level), and the data setup falling time Tsf represents a time that should be provided in order to read the falling edge FE of the first data ID (i.e., in order to accurately read a logic low level).

Referring to fig. 3, it can be seen that the second data OD1 changes when the first data ID changes to a logic high level at the data setup rising time Tsr or changes to a logic low level at the data setup falling time Tsf.

For example, for the data setup rising time Tsr, a logic high level of the first data ID should be read when the first clock CK1 is applied. When the first clock CK1 has a constant value C or more, the rising edge RE of the first data ID should also have a constant value D sufficient to read a logic high level. Thus, in fig. 3, the time between C and D may be considered as the data setup rise time Tsr. Since the data setup falling time Tsf can be analogized from the data setup rising time Tsr, a description thereof will be omitted.

On the other hand, the data hold time Thold indicates a time when the input signal should be held in order for the flip-flop circuit to accurately read a data value from the input signal. That is, the data hold time Thold is an index representing a time when the input signal should be held after the clock signal is applied in order for the flip-flop circuit to accurately read a data value from the input signal.

In the inventive concept, the data hold time Thold denotes a time when the first data ID should be held in order to accurately read the value of the first data ID so that the second data OD1 is kept constant. The data hold time Thold may include a data hold rise time Thr and a data hold fall time Thf. The data hold rising time Thr denotes a time when the first data ID should be held in order to accurately read the logic low level just before the rising edge RE of the first data ID is generated, and the data hold falling time Thf denotes a time when the first data ID should be held in order to accurately read the logic high level just before the falling edge FE of the first data ID is generated.

Referring to fig. 3, it can be seen that the second data OD1 remains constant even if the first data ID showing the data hold rising time Thr and the data hold falling time Thf is changed to the first logic high level or logic low level.

For example, for the data holding falling time Thf, the logic high level of the first data ID should be read when the first clock CK1 is applied. When the first clock CK1 has a constant value a or more, the falling edge FE of the first data ID should maintain a constant value B or more sufficient to read a logic high level. Therefore, in fig. 3, the time between a and B is considered as the data retention falling time Thf. Since the data hold rising time Thr can be analogized from the data hold falling time Thf, a description thereof will be omitted. In the semiconductor circuit 1 according to the exemplary embodiment of the inventive concept, the high sampling window Tsw _ high may be obtained from the sum of the data setup rising time Tsr and the data hold falling time Thf, and the low sampling window Tsw _ low may be obtained from the sum of the data setup falling time Tsf and the data hold rising time Thr. In other words, the high sampling window Tsw _ high represents the sum of the time provided for reading the level of the first data ID to a logic high level and the time for which the level of the first data ID should be maintained to a logic high level.

On the other hand, the low sampling window Tsw _ low represents the sum of the time that the level of the first data ID should be provided to be read to a logic low level and the time that the level of the first data ID should be maintained to a logic low level.

In a general flip-flop circuit, as the size of a sampling window becomes smaller, the flip-flop circuit can operate at higher speed.

Referring to fig. 3 and table 1, if the first data ID is applied to the main stage 100, the first data ID is directly output as the second data OD1 through the main stage 100 (operation (1)). In detail, since the level of the first clock CK1 becomes a high level when the level of the first data ID is a logic low level, both the first transistor MP11 and the second transistor MP12 are turned on. However, the third transistor MN11 remains in the off state. Accordingly, the first node N1 is maintained at the high level, and as a result, the second data OD1 is maintained at the first level (logic low level) (operation (2)).

Since the level of the first clock CK1 is a logic high level, the level of the first sub-clock CK2-1 becomes a logic low level, and the level of the second sub-clock CK2-2 becomes a logic high level. Since the first sub-clock CK2-1 is generated by the sixth inverter IN31, the phase of the first sub-clock CK2-1 is delayed by a certain time compared to the phase of the first clock CK 1. Since the second sub-clock CK2-2 is generated by the seventh inverter IN32, the phase of the second sub-clock CK2-2 is delayed by a certain time compared to the phase of the first sub-clock CK 2-1. Since the above-described relationship between the reference clock CK and the first and second sub-clocks CK2-1 and CK2-2 can be derived from the configuration of the clock generation unit 300 described above, a detailed description thereof will be omitted.

On the other hand, if the first sub-clock CK2-1 is a logic high level and the second sub-clock CK2-2 is a logic low level as described above, the fourth transistor MN21 and the fifth transistor MP21 are turned off and the slave stage 200 is in a disabled state. Therefore, the first data ID cannot be latched to the slave stage 200.

Then, if the rising edge RE of the first clock CK1 is formed, the second transistor MP12 is turned off. However, the level of the logical operation signal MCK1 generated by the first gate G11 remains at a logic low level. Accordingly, the third transistor MN11 is still in an off state, and the first node N1 is maintained at a logic high level.

Since the rising edge RE of the first clock CK1 is formed, the first and second sub-clocks CK2-1 and CK2-2 have falling and rising edges FE and RE, respectively. Thus, the slave stage 200 is enabled. Accordingly, the second data OD1 is provided to the slave stage 200, and the third inverter IN21 inverts the second data OD1 to output the third data. The third data OD2 may be at a logic high level.

Then, if the falling edge FE of the first data ID is formed, the rising edge of the inverted data IDB generated by time-delaying the first data ID by the first inverter IN11 is formed (operation (3)). The inverted data IDB is maintained at a logic high level to turn off the first transistor MP 11. However, since the logical operation signal MCK1 is still at a logic low level, the third transistor MN11 is in an off state, and thus the second data OD1 is maintained at a logic low level.

On the other hand, since the rising edge RE of the first clock CK1 and the falling edge FE of the first data ID partially overlap each other, a local change M1 may occur in the logical operation signal MCK 1. However, such a local change does not exert an influence on the third transistor MN 11. Further, local change M1 may not occur.

Then, if the falling edge FE of the first clock CK1 is formed, the rising edge RE of the logical operation signal MCK1 may be formed (operation (4)). By the logical operation signal MCK1, the third transistor MN11 is turned on, and the first node N1 changes to a logic low level (operation (5)). Accordingly, the second data OD1 is delayed by a certain time by the second inverter IN12, and the second data OD1 is changed to a logic high level (operation (6)). As a result, the first data ID may be output as the first data ID at the falling edge FE of the first clock CK 1.

If the falling edge FE of the first clock CK1 is formed, the slave stage 200 is disabled and the second data OD1 cannot be latched. Therefore, the third data OD2 is held at a logic high level.

On the other hand, referring to table 1, it can be seen that the logical operation signal MCK1 is at a logic high level only when both the first clock CK1 and the first data ID are at a logic low level.

Referring again to fig. 3, if the rising edge RE of the first clock CK1 is formed with the first data ID maintained in a logic low state, the first transistor MP11, the second transistor MP12, and the third transistor MN11 are all turned off, and the main stage 100 is disabled. Therefore, the second data OD1 remains at a logic high level. Further, if the rising edge RE of the first clock CK1 is formed, the slave stage 200 is enabled. The second data OD1 of a logic high level is received from the stage 200, and a falling edge of the third data OD2 is formed. As a result, at the rising edge RE of the first clock CK1, the first data ID is read from the stage 200 and the read first data ID will be output as the third data OD2 (operation (7)).

Then, if the rising edge RE of the first data ID is formed, the first transistor MP11 is turned on, but the second transistor MP12 and the third transistor MN11 are still in an off state. Therefore, the main stage 100 is in the disabled state, and the second data OD1 remains constant (operation (8)). Since the first clock CK1 is at a logic high level, the slave stage 200 is enabled, and the third inverter IN21 inverts the second data OD1 and outputs the inverted second data as the third data OD 2.

Then, if the first clock CK1 is at a logic low level and the first data ID is at a logic low level, the first transistor MP11 is turned off. At this time, since the logic operation signal MCK1 is at a logic high level, the third transistor MN11 is turned on and the first node N1 is at a logic low level. Therefore, the second data OD1 is at a logic high level. However, since the first clock CK1 is at a logic low level, the slave stage 200 is disabled, and thus the slave stage 200 cannot latch the second data OD 1.

If the rising edge RE of the first data ID is formed, the first and second transistors MP11 and MP12 are turned on and a rising edge of the first node N1 is formed (operation (9)). At this time, the falling edge FE of the logical operation signal MCK1 is formed, and the third transistor MN11 is turned off (operation (10)). If the rising edge RE of the first node N1 is formed, the second inverter IN12 delays the second data OD1 for a certain time and forms the falling edge FE of the second data OD 1. At this time, the first clock CK1 is at a logic low level, and the slave stage 200 is in a disabled state.

If the rising edge RE of the first clock CK1 is formed, the second transistor MP12 and the third transistor MN11 are turned off, and the main stage 100 is disabled. Therefore, the second data OD1 remains at the logic low level (operation (11)). At the rising edge RE of the first clock CK1, the slave stage 200 is enabled and receives the second data OD1 and inverts the second data OD1 to output the inverted second data OD1 as the third data OD 2. Since the subsequent operation of the semiconductor circuit 1 can be sufficiently expected by the derivation for the above, the description thereof will be omitted.

The operation of the semiconductor circuit 1 according to this embodiment as described above is summarized as follows.

First, after the rising edge RE of the first clock CK1 is formed, the falling edge of the first sub-clock CK2-1 is formed. Accordingly, the master stage 100 is disabled based on the time point T1 of fig. 3, and the slave stage 200 is enabled based on the time point T2 of fig. 3.

That is, since the falling edge FE of the first sub-clock CK2-1 cannot be formed to overlap the rising edge RE of the first clock CK1, the enable/disable operations of the master stage 100 and the slave stage 200 are sequentially performed.

If the enable/disable operations of the master stage 100 and the slave stage 200 are not sequentially performed, the first data ID is not output as the third data OD2 to match the clock signal, but the data already stored in the master stage 100 or the slave stage 200 is output as the third data OD2 regardless of the first data ID. Such a malfunction causes an increase in the sampling window of the semiconductor circuit 1 (e.g., flip-flop), and thus the operational reliability of the device deteriorates.

However, in the semiconductor circuit 1, any possible malfunction is intercepted in advance by the above configuration, so that the operational reliability of the semiconductor circuit 1 can be improved.

In addition, timing skew (timing skew) of the main stage 100 has a large influence on the size and symmetry of the sampling window. However, according to the circuit configuration of the semiconductor circuit 1, timing skew of the main stage 100 can be reduced, so that the sampling window can be symmetrically formed in a small size.

In the semiconductor circuit 1 configured as above, the low sampling window Tsw _ low and the high sampling window Tsw _ high have been measured to be about 2 to 5ps and about 3 to 7ps, respectively. Therefore, it can be confirmed that there is almost no time difference between the low sampling window Tsw _ low and the high sampling window Tsw _ high, and thus the sampling window Tsw is symmetrically formed. Since the sampling windows Tsw are symmetrically formed, the reliability of the semiconductor circuit 1 can be improved.

On the other hand, the master 100 and slave 200 stages may have different threshold voltages Vt. For example, the threshold voltage of the master stage 100 may be lower than the threshold voltage of the slave stage 200. If the threshold voltage of the master stage 100 is constructed to be lower than that of the slave stage 200, the sampling window Tsw may be formed in a small size. Table 2 below shows the ratio of the power loss to the sampling window Tsw in the case where the threshold voltages are different from each other.

TABLE 2

High Vt	Low Vt	Low Vt–High Vt
			Tsw
1	0.76	0.82
			Leakage power	1	5.78	2.3

Referring to table 2, if it is assumed that the sampling window Tsw of the semiconductor circuit 1 is 1 and the power loss of the semiconductor circuit 1 is 1 in the case where both the master stage 100 and the slave stage 200 have high threshold voltages, the sampling window Tsw is increased by 0.76 times and the power loss is increased by 5.789 times in the case where both the master stage 100 and the slave stage 200 have low threshold voltages. Since the circuit can operate at high speed as the threshold voltage is lowered, the sampling window can be reduced. However, since the leakage current increases to the above-described extent, the power loss increases to 5.78 times.

The above problem can be solved by making the threshold voltages of the master stage 100 and the slave stage 200 different from each other. For example, the threshold voltage of the master stage 100 may be configured to be lower than the threshold voltage of the slave stage 200. In this case, the sampling window is increased by a factor of 0.82 and the power loss is increased by a factor of 2.3, compared with the case where the semiconductor circuit 1 has a high threshold voltage

It can be confirmed that the sampling window is reduced in a similar manner and the power loss is reduced to less than half thereof, compared to the case where both the master 100 and the slave 200 have low threshold voltages. Therefore, if the threshold voltage of the master stage 100 is constructed to be lower than that of the slave stage 200, power loss is minimized and the sampling window is reduced.

Here, the threshold voltage of the master stage 100 may represent the threshold voltage of the active device used in the master stage 100 (e.g., the threshold voltage of the first transistor MP11, the second transistor MP12, and the third transistor MN11, and the first holder 41), and the threshold voltage of the slave stage 200 may represent the threshold voltage of the active device used in the slave stage 200 (e.g., the threshold voltage of the fourth transistor MN21 and the fifth transistor MP21, and the threshold voltage of the second holder 42).

Referring to fig. 4 and 5, a semiconductor circuit 2 according to another embodiment will be described. Explanations of contents overlapping with the above description will be omitted, and explanations will be made around different points between the embodiments.

Fig. 4 is a circuit diagram of the semiconductor circuit 2, and fig. 5 is a diagram showing operation timings of the semiconductor circuit 2 of fig. 4.

Referring to fig. 4, according to the semiconductor circuit 2, the clock generating unit 310 additionally includes the first delay unit 51, unlike the semiconductor circuit 1 of fig. 2. In detail, the first delay unit 51 receives the reference clock CK and generates the first clock CK1 by delaying the reference clock CK by a certain time. To delay the reference clock CK, the first delay unit 51 may include two inverters IN33 and IN34 connected IN series. The first delay unit 51 may generate the first clock CK1 by inverting the reference clock CK twice. Similar to the clock generation unit 300 of fig. 2, the second clock CK2 may be generated using the first clock CK 1.

Since the clock generation unit 310 includes the first delay unit 51, as shown in fig. 5, the phase of the first clock CK1 applied to the host 100 may be delayed. If the phase of the first clock CK1 is delayed, the rising edge RE and the falling edge FE of the first data ID and the first clock CK1 can be accurately distinguished, so that an error of the semiconductor circuit 2 can be prevented. Since the phase of the first clock CK1 is delayed as much as the first size W1, the phases of the first sub-clock CK2-1 and the second sub-clock CK2-2 constituting the second clock CK2 are delayed as much as the first size W1.

Referring to fig. 6 and 7, a semiconductor circuit 3 according to another exemplary embodiment of the inventive concept will be described. Explanations of contents overlapping with the above description will be omitted, and explanations will be made around different points between the embodiments.

Fig. 6 is a circuit diagram of the semiconductor circuit 3, and fig. 7 is a timing chart of the first clock and the second clock of fig. 6.

Referring to fig. 6, the semiconductor circuit 3 is different from the semiconductor circuit 2 of fig. 4 in that the clock generating unit 320 has a different configuration. In detail, in a manner similar to the semiconductor circuit 2 of fig. 4, the first clock CK1 is generated by the phase delay of the reference clock CK by the first delay unit 51 being as large as the first magnitude W1. However, IN the case of generating the first sub-clock CK2-1 using the first clock CK1, the second gate G31 is used instead of the sixth inverter IN 31. The second gate G31 may be a NAND gate, for example. The second gate G31 generates the first sub-clock CK2-1 by performing a NAND logic operation on the first clock CK1 and the reference clock CK. As shown in fig. 7, the first sub-clock CK2-1 can shorten the time of a logic low level as compared to the first clock CK 1. When the first sub-clock CK2-1 is at a logic low level and the second sub-clock CK2-2 is at a logic high level, the slave stage 200 may be enabled, and the second gate G31 may be used to shorten the time when the slave stage 200 remains in an enabled state. If the enable time of the slave stage 200 is shortened, the master stage 100 and the slave stage 200 may be prevented from being enabled or disabled simultaneously. The second sub-clock CK2-2 may be generated by an inversion of the first sub-clock CK 2-1.

Referring to fig. 8, a semiconductor circuit 4 according to another exemplary embodiment of the inventive concept will be described. Explanations of contents overlapping with the above description will be omitted, and explanations will be made around different points between the embodiments.

Fig. 8 is a circuit diagram of the semiconductor circuit 4.

Referring to fig. 8, the semiconductor circuit 4 of fig. 8 is different from the semiconductor circuit 1 of fig. 2 in that the clock generation unit 330 includes the second delay unit 53. The second delay unit 53 may be connected IN series to the sixth inverter IN 31. The second delay unit 53 may be provided by connecting two inverters IN35 and IN36 IN series.

The first clock CK1 is the same as the reference clock CK. The first sub-clock CK2-1 is generated by delaying the phase of the first clock CK1 by the second delay unit 53 as much as the first magnitude W1 and inverting the delayed first clock CK by the sixth inverter IN 31.

Referring to fig. 9, a semiconductor circuit 5 according to another exemplary embodiment of the inventive concept will be described. Explanations of the contents overlapping with the above description will be omitted.

Fig. 9 is a circuit diagram of the semiconductor circuit 5.

Referring to fig. 9, the semiconductor circuit 5 of fig. 9 is different from the semiconductor circuit 4 of fig. 8 IN that the second gate G31 IN the clock generating unit 340 may replace the sixth inverter IN 31. The second gate G31 may be a NAND gate, for example. The first clock CK1 may be the same as the reference clock CK. The first sub-clock CK2-1 may be generated by delaying the first clock CK1 through the second delay unit 53 and performing a NAND logic operation on the delayed first clock CK1 and the first clock CK 1. The second sub-clock CK2-2 may be generated by an inversion of the first sub-clock CK 2-1.

Referring to fig. 10, a semiconductor circuit 6 according to another exemplary embodiment of the inventive concept will be described. Explanations of the contents overlapping with the above description will be omitted.

Fig. 10 is a circuit diagram of the semiconductor circuit 6.

Referring to fig. 10, the semiconductor circuit 6 of fig. 10 differs from the semiconductor circuit 1 of fig. 2 in the aspects of the main stage 120 and the clock generation circuit 350.

IN detail, the semiconductor unit 6 of fig. 10 includes a first inverter IN11, a third gate G12, a third circuit 105, a fourth circuit 107, a first holder 41, and a second inverter IN 12. The third circuit 105 may be connected to the third voltage and may include a sixth transistor MP 13. The sixth transistor MP13 may be, for example, a PMOS transistor. The sixth transistor MP13 may be controlled by a logic operation signal MCK2 generated by the third gate G12. The third voltage may be, for example, a supply voltage. The third circuit 105 may change the level of the first node N1 to a logic high level. That is, the third circuit 105 may change the level of the second data OD1 to a logic low level.

The fourth circuit 107 may be connected to a fourth voltage and may include a seventh transistor MN12 and an eighth transistor MN 13. The seventh transistor MN12 and the eighth transistor MN13 may be connected in series, and may be, for example, NMOS transistors. For example, the fourth voltage may be a ground voltage. The fourth circuit 107 may change the level of the first node NI to a logic low level. That is, the fourth circuit 107 may change the level of the second data OD1 to a logic high level.

The seventh transistor MN12 may be controlled by the inverted data IDB gate of the first data ID inverted by the first inverter IN 11. The eighth transistor MN13 is controlled by the first clock CK 1.

The third gate G12 may perform a logical operation of the first data ID and the first clock CK1, and may provide the logical operation signal MCK2 to the third circuit 105. The third gate G12 may be, for example, a NAND gate, and may perform a NAND logic operation of the first data ID and the first clock CK 1.

The third circuit 105 and the fourth circuit 107 may be connected in series and may be connected to the first node N1. The second inverter IN12 is connected to the first node N1 and inverts the signal of the first node N1 to generate the second data OD 1. The first holder 41 is connected to the first node N1, and may be connected IN parallel to the second inverter IN 12.

The clock generation unit 350 may include a seventh inverter IN32 and an eighth inverter IN 37. The eighth inverter IN37 generates the first clock CK1 by inverting the reference clock CK. The first sub-clock CK2-1 may be the same as the first clock CK1, and the second sub-clock CK2-2 may be generated by inverting the first sub-clock CK2-1 by the seventh inverter IN 32.

The slave stage 200 of the semiconductor circuit 6 of fig. 10 is the same as the slave stage of the semiconductor circuit 1 of fig. 2.

The semiconductor circuit 6 of fig. 10 is a circuit formed by inverting the semiconductor circuit 1 of fig. 2. In other words, the semiconductor circuit 1 of fig. 2 operates in a similar manner to the semiconductor circuit 6 of fig. 10, but has a circuit configuration opposite to that of the semiconductor circuit 6 of fig. 10. In detail, the third gate G12 is formed of a NAND gate instead of a NOR gate; the third circuit 105, which is controlled by the third gate G12, is connected to the supply voltage and includes PMOS transistors. The fourth circuit 107 includes two NMOS transistors and is connected to the ground voltage. Further, the first clock CK1 supplied to the main stage 120 is generated by inverting the reference clock CK.

Since it can be deduced from the above: the semiconductor circuit 6 of fig. 10 has a circuit configuration different from that of the semiconductor circuit 1 of fig. 2, but the semiconductor circuit 6 of fig. 10 operates in a similar manner to the semiconductor circuit 1 of fig. 2, and therefore explanation of the operation of the semiconductor circuit 6 of fig. 10 will be omitted.

Referring to fig. 11, a semiconductor circuit 7 according to another exemplary embodiment of the inventive concept will be described. Explanations of the contents overlapping with the above description will be omitted

Fig. 11 is a circuit diagram of the semiconductor circuit 7.

The semiconductor circuit 7 of fig. 11 differs from the semiconductor circuit 6 of fig. 10 in the clock generation unit 360.

Referring to fig. 11, the clock generation unit 360 includes the second delay unit 53. That is, the first clock CK1 is generated by inverting the reference clock CK, and the first sub-clock CK2-1 is generated by delaying the phase of the first clock CK1 by the second delay unit 53. The second sub-clock CK2-2 may be generated by inverting the first sub-clock CK 2-1. The second delay unit 53 may be formed by a series connection of two inverters IN35 and IN 36.

Referring to fig. 12, a semiconductor circuit 8 according to another exemplary embodiment of the inventive concept will be described. Explanations of the contents overlapping with the above description will be omitted

Fig. 12 is a circuit diagram of the semiconductor circuit 8.

The semiconductor circuit 8 of fig. 12 differs from the semiconductor circuit 6 of fig. 10 in the clock generation unit 370. In detail, referring to fig. 12, the clock generation unit 360 may include a third delay unit 55. The third delay unit 55 may include a ninth inverter IN38 and a fourth gate G32.

The first clock CK1 is generated by inverting the reference clock CK by the eighth inverter IN 37. Further, the first sub-clock CK2-1 is generated by performing a logical operation on the reference clock CK and a value obtained by inverting the first clock CK1 through the fourth gate G32. For example, the fourth gate G32 may be a NAND gate, and the first sub-clock CK2-1 may be generated by performing a logical operation on the reference clock CK and a value obtained by inverting the first clock CK 1.

Referring to fig. 13, a semiconductor system 10 including semiconductor circuits according to some example embodiments of the inventive concepts will be described.

Fig. 13 is a block diagram of semiconductor system 10.

Semiconductor system 10 may include a transmitter 20 and a receiver 30. The transmitter 20 may transmit the first data ID to the receiver 30 using the reference clock. The receiver 30 may receive the first data ID and may process or perform sampling of the first data ID using the reference clock CK. One of the semiconductor circuits 1 to 8 described above may be formed at the input of the receiver 30. An input of the receiver 30 may receive the first data ID and the reference clock CK and provide the third data OD2 to the receiver 30.

Here, the semiconductor system 10 may be, for example, a processor, but is not limited thereto. The semiconductor system 10 can be applied to a semiconductor device for transmitting data.

With reference to fig. 14, a computing system that can employ the above-described semiconductor circuits 1 to 8 will be described.

Fig. 14 is a block diagram showing the configuration of the computing system 501.

Referring to fig. 14, a computing system 501 includes a central processing unit 500, an Accelerated Graphics Port (AGP) device 510, a main memory 600, a memory (e.g., SSD or HDD)540, a north bridge 520, a south bridge 530, a keyboard controller 560, and a printer controller 550.

The computing system 501 shown in fig. 14 may be a personal computer or a notebook computer. However, the inventive concept is not so limited and examples of the computing system 501 may be modified without limitation.

In computing system 501, central processing unit 500, AGP device 510, and main memory 600 may be connected to north bridge 520. However, the inventive concept is not limited thereto, and the north bridge 520 may be modified to be included in the central processing unit 500.

The AGP may be a bus standard that enables accelerated implementation of three-dimensional (3D) graphics representations, and the AGP device 510 may include a video card that renders a monitor image.

The central processing unit 500 may perform various types of logical operations required to drive the computing system 101, and may execute an OS and application programs. At least one of the semiconductor circuits 1 to 8 may be employed as a part of the central processing unit 500.

The main memory 600 may load data required to perform the operation of the central processing unit 500 from the memory 540 to store the loaded data.

Memory 540, keyboard controller 560, printer controller 550, and various types of peripheral devices (not shown) may be connected to south bridge 530.

The memory 540 is a mass data storage storing file data and the like, and may be realized by, for example, an HDD or an SSD. However, the inventive concept is not limited to such an example.

Further, the computing system 501 has a structure in which the memory 540 is connected to the south bridge 530, but the inventive concept is not limited thereto. The structure may be modified in such a way that memory 540 is connected to north bridge 520 or memory 540 is directly connected to central processing unit 500.

Next, an electronic system 900 that can employ the semiconductor circuits 1 to 8 will be described with reference to fig. 15.

Fig. 15 is a block diagram showing a configuration of an electronic system 900 that can employ the semiconductor circuits 1 to 8.

Referring to fig. 15, an electronic system 900 may include a memory system 902, a processor 904, RAM 906, and a user interface 908.

The memory system 902, processor 904, RAM 906, and user interface 908 may perform data communications with each other using a bus 910.

The processor 904 may be used to execute programs and control the electronic system 900, and the RAM 906 may be used as operating memory for the processor 904. The processor 904 may include at least one of the semiconductor circuits 1 to 8 as a part of constituent elements. The processor 904 and the RAM 906 may be implemented as one semiconductor device or semiconductor package.

The user interface 908 may be used to input data to the electronic system 900 or to output data from the electronic system 900.

The memory system 902 may store code for the operation of the processor 904, data processed by the processor 904, or data input from the outside. The memory system 902 may include a separate controller for its operation and may be configured to additionally include an error correction block. The error correction block may be configured to detect and correct errors of data stored in the memory system 902 using an Error Correction Code (ECC).

The memory system 902 may be integrated into one semiconductor device. Illustratively, the memory system 902 may be integrated into one semiconductor device to constitute a memory card. For example, the memory system 902 may be integrated into one semiconductor device to construct a memory card, such as a PC card (personal computer memory card international association (PCMCIA)), a Compact Flash (CF) card, a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, or SDHC), a universal flash memory device (UFS), or the like.

The electronic system 900 shown in fig. 15 can be applied to electronic control devices of various electric appliances. Fig. 16 is a diagram illustrating an example in which the electronic apparatus of fig. 15 is applied to a smartphone. In the case where the electronic system 900 (of fig. 15) is applied to the smartphone 1000, at least one of the semiconductor circuits 1 to 8 may be employed as a part of the constituent element of the Application Processor (AP).

Further, the electronic system 900 (of fig. 15) may be provided as one of various constituent elements of an electronic device such as a computer, an ultra mobile pc (umpc), a workstation, a netbook, a Personal Digital Assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smartphone, an electronic book, a Portable Multimedia Player (PMP), a portable game machine, a navigation device, a black box, a digital camera, a 3-dimensional television receiver, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, a device that can transmit and receive information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telecommunication network, an RFID device, or one of various constituent elements constituting a computing system.

Although the exemplary embodiments of the inventive concept have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the inventive concept as disclosed in the accompanying claims.

Claims

1. A flip-flop, comprising:

a first circuit connected between a first voltage terminal and a first node and configured to change a voltage of the first node to a first level of the first voltage terminal according to first data and a first clock;

a first gate configured to perform a logical operation on first data and a first clock;

a second circuit connected between the first node and a second voltage terminal and configured to change a voltage of the first node to a second level of the second voltage terminal according to an output of the logical operation,

wherein the second clock provided to the slave stage of the flip-flop comprises a first sub-clock and a second sub-clock, the second sub-clock being an inverse of the first sub-clock,

wherein the second clock is generated based on the first clock,

wherein the first circuit comprises:

a first inverter configured to invert the first data;

a first transistor and a second transistor connected in series between a first voltage terminal and a first node and configured to receive inverted first data and a first clock, respectively, wherein the second circuit includes:

and a third transistor connected between the first node and the second voltage terminal and configured to receive an output of the logical operation, wherein the first clock is generated by the reference clock, and the first sub-clock is generated by performing a NAND logical operation on the reference clock and the first clock.

2. The flip-flop of claim 1, further comprising:

a clock generation unit configured to receive a reference clock and generate a first clock and a second clock.

3. The flip-flop according to claim 2, wherein the clock generation unit is configured to generate the first sub-clock by inverting the first clock.

4. The flip-flop of claim 2, wherein the clock generation unit comprises:

a first delay unit configured to delay a phase of a first clock and generate a second clock using the delayed first clock.

5. The flip-flop of claim 4, wherein the clock generation unit is configured to generate the first sub-clock by performing a NAND logic operation on the reference clock and the delayed first clock.

6. The flip-flop of claim 4, wherein the first clock and the reference clock are the same.

7. The flip-flop according to claim 2, wherein the clock generation unit is configured to generate the first clock by delaying a phase of the reference clock.

8. The flip-flop according to claim 2, wherein the clock generation unit is configured to generate the first clock by inverting the reference clock.

9. The flip-flop of claim 8, wherein the clock generation unit is configured to generate the first sub-clock by performing a NAND logic operation on the inverted signal of the first clock and the reference clock.

10. The flip-flop of claim 1, further comprising:

a keeper circuit configured to hold a voltage of the first node based on the first clock and an output of the logical operation.

11. A semiconductor circuit, comprising:

a master circuit and a slave circuit configured to receive a first clock and a second clock, respectively, the first clock and the second clock having different phases,

wherein the main circuit comprises a first transistor, a second transistor, a third transistor, a first inverter and a first gate,

wherein the first transistor, the second transistor and the third transistor are connected in series between a first voltage terminal and a second voltage terminal,

wherein the first inverter is configured to invert input data and gate the first transistor,

wherein the first gate is configured to gate control the third transistor, the first gate is configured to perform a logic operation on the input data and the first clock,

wherein the second transistor is configured to receive a first clock,

wherein the second clock includes a first sub-clock and a second sub-clock, the second sub-clock being an inverse of the first sub-clock,

wherein the first clock is generated by a reference clock, and the first sub-clock is generated by performing a NAND logic operation on the reference clock and the first clock.

12. The semiconductor circuit according to claim 11, wherein a threshold voltage of the master circuit is lower than a threshold voltage of the slave circuit.

13. The semiconductor circuit according to claim 11, wherein the first transistor is connected to a first voltage terminal, the third transistor is connected to a second voltage terminal, and the second transistor is located between the first transistor and the third transistor.

14. The semiconductor circuit according to claim 13, wherein the first transistor and the second transistor are configured to change input data to a first level, and the third transistor is configured to change input data to a second level.

15. The semiconductor circuit of claim 11, further comprising:

a keeper circuit configured to hold a voltage of a node to which the second transistor and the third transistor are connected, based on the first clock and an output of the logical operation.

16. The semiconductor circuit according to claim 11, wherein the logical operation is a NOR logical operation.

17. The semiconductor circuit according to claim 16, wherein the first transistor and the second transistor are PMOS transistors, and wherein the third transistor is an NMOS transistor.

18. The semiconductor circuit according to claim 13, wherein the first voltage of the first voltage terminal is a power supply voltage, and the second voltage of the second voltage terminal is a ground voltage.