CN104579298B - Flip-flop and semiconductor circuit - Google Patents

Abstract

A flip-flop and semiconductor circuit are provided. Example embodiments disclose a flip-flop comprising: a first inverter configured to invert first data; a first transistor and a second transistor connected in series with each other and configured to receive the inverters, respectively. a first data and a first clock of a phase; a first gate configured to perform a logic operation on the first data and the first clock; and a third transistor configured to receive an output of the logic operation. The second transistor and the third transistor are connected to the first node.

Description

flip-flops and semiconductor circuits

This application is based on and claims priority to Korean Patent Application No. 10-2013-0123398 filed with the Korean Intellectual Property Office on October 16, 2013, the disclosure of which is incorporated herein by reference in its entirety.

technical field

The inventive concept relates to a semiconductor circuit and a semiconductor system.

Background technique

As one of the semiconductor devices, flip-flops operate to store input data in response to a clock signal, and sequentially transfer the stored data. Multiple triggers can be used to transmit data.

On the other hand, with the trend of high-speed electronics, the speed of clock signals supplied to flip-flops has gradually increased. In order to operate multiple flip-flops reliably in this environment, timing failures need not occur during the operation of the flip-flops regardless of the high-speed clock signal.

SUMMARY OF THE INVENTION

The inventive concept provides a semiconductor circuit that symmetrically forms sampling windows in a small size and thus improves product reliability.

In addition, the inventive concept provides a semiconductor system that symmetrically forms sampling windows in a small size and thus improves product reliability.

Other advantages, objects and features of the inventive concept are set forth in part in the following description and will become apparent to those of ordinary skill in the art or from the inventive concept by the following search. Other advantages, objects and features of the inventive concept are learned from the practice of the present invention.

In an example embodiment of the inventive concept, there is provided a flip-flop including: a first inverter configured to invert first data; a first transistor and a second transistor connected in series with each other connected and configured to receive the inverted first data and the first clock, respectively; a third transistor; a first gate configured to perform a logical operation on the first data and the first clock; and a third transistor configured to receive the output of the logic operation, wherein the second transistor and the third transistor are connected to the first node.

In one example embodiment of the inventive concept, a semiconductor circuit is provided, the semiconductor circuit including a master circuit and a slave circuit configured to receive first and second clocks, respectively, the first and second clocks have different phases from each other, wherein the main circuit includes: a first transistor, a second transistor, a third transistor, a first inverter and a first gate, wherein the first transistor, the second transistor and the third transistor are connected in series at the between a voltage terminal and a second voltage terminal, wherein the first inverter is configured to invert the input data and gate the first transistor, wherein the first gate is configured to gate the third transistor Controlling, the first gate is configured to perform a logical operation on the input data and the first clock, wherein the second transistor is configured to receive the first clock.

In one embodiment of the inventive concept, there is provided a semiconductor system including: a transmitter configured to transmit first data using a reference clock; a receiver configured to receive the first data, wherein the receiving The device includes: a clock generating unit configured to generate a first clock and a second clock having different phases using a reference clock; a master circuit configured to receive the first data and the first clock and output the second data; a slave circuit configured to be configured to receive the second data and the second clock and output the third data, wherein the main circuit includes a first circuit between the first voltage terminal and the first node for changing the second data to a first level, A second circuit for changing the second data to a second level between the first node and the second voltage terminal, and the second circuit is configured to operate according to the first data and the logic operation signal of the second clock .

In another example embodiment of the present inventive concept, there is provided a semiconductor circuit including: a clock generating unit configured to generate a first clock and a second clock different from the first clock using a reference clock; a main clock a circuit configured to receive the first data and the first clock and output the second data; the slave circuit configured to receive the second data and the second clock and output the third data, wherein the second clock includes the first sub-clock and The second sub-clock, wherein the main circuit includes: a first PMOS transistor connected to the power supply voltage; a second PMSO transistor connected in series to the first PMOS transistor and controlled by the first clock gate; a first NMOS transistor connected in series to the first clock gate Two PMOS transistors are connected to the ground voltage terminal; the first inverter is configured to gate the first PMOS transistor by inverting the input data; the NOR gate is configured to perform gate control for the first clock and the input NOR logic operation of data to gate control the first NMOS transistor; the clock generation unit includes: a delay unit, configured to delay the phase of the reference clock to generate the first clock; NAND gate, configured to execute the first clock for the first clock. and a NAND logic operation of the reference clock to generate the first sub-clock, and a second inverter configured to invert the first sub-clock to generate the second sub-clock.

At least one example embodiment discloses a clock generation circuit configured to generate a first clock and a second clock, a circuit configured to receive first data, perform a logical operation on the first clock and the first data, and based on the logical operation And a master circuit that generates first output data and a slave circuit configured to generate second output data based on the first output data and a second clock.

Description of drawings

The above and other objects, features and advantages of the present inventive concept will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

1 is a block diagram of a semiconductor circuit according to an example embodiment of the inventive concept;

FIG. 2 is a circuit diagram of a semiconductor circuit according to an example embodiment of the inventive concept;

FIG. 3 is a diagram explaining an operation of a semiconductor circuit according to example embodiments of the inventive concept;

4 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concept;

FIG. 5 is a diagram illustrating an operation timing of the semiconductor circuit of FIG. 4;

FIG. 6 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concept;

FIG. 7 is a timing diagram of the first clock and the second clock of FIG. 6;

FIG. 8 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concept;

FIG. 9 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concept;

10 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concept;

11 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concept;

12 is a circuit diagram of a semiconductor circuit according to another example embodiment of the inventive concept;

13 is a block diagram of a semiconductor system including a semiconductor circuit according to some example embodiments of the inventive concepts;

14 is a block diagram illustrating a configuration of a computing system that may employ semiconductor circuits according to some example embodiments of the inventive concepts;

15 is a block diagram illustrating a configuration of an electronic system that may employ semiconductor circuits according to some example embodiments of the inventive concepts;

FIG. 16 is a diagram illustrating an example of applying the electronic system of FIG. 15 to a smartphone.

Detailed ways

The inventive concept will now be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the inventive concept are shown. The inventive concepts may, however, be embodied in different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. Throughout the specification, the same reference numerals refer to the same components. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

Unless otherwise indicated herein or clearly contradicted by context, the use of the singular or similar references in the context of describing the inventive concept (especially, in the context of the claims) is to be construed to cover both the singular and the plural. The terms "including," "having," "including," and "containing" are to be construed as open-ended terms (ie, meaning "including, but not limited to,") unless otherwise noted.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It is noted that any and all examples or terminology used herein are merely intended to better illustrate the inventive concept, and do not limit the scope of the inventive concept, unless otherwise defined. Also, unless otherwise defined, all terms defined in the general dictionary should not be overly construed.

The inventive concept will be described with reference to perspective, cross-sectional, and/or plan views illustrating example embodiments of the inventive concept. Accordingly, the outlines of the exemplary diagrams may be modified according to manufacturing technology and/or capacity. That is, the exemplary embodiments of the inventive concept are not intended to limit the scope of the inventive concept, but to cover all changes and modifications that may be caused by changes in manufacturing techniques. Accordingly, the regions illustrated in the figures are shown in schematic form, and their shapes are simplified by way of illustration, and not limitation.

Hereinafter, a semiconductor circuit 1 according to an example embodiment of the inventive concept will be described with reference to FIGS. 1 and 2 .

FIG. 1 is a block diagram of a semiconductor circuit 1 according to an example embodiment of the present inventive concept, and FIG. 2 is a circuit diagram of a semiconductor circuit 1 according to an example embodiment of the present inventive concept.

1 , a semiconductor circuit 1 includes a master stage 100 , a slave stage 200 and a clock generation unit 300 .

For example, the semiconductor circuit 1 may receive input data and perform sampling of the received data. However, the inventive concept is not limited thereto. In the following, the semiconductor device 1 is exemplarily shown as a master-slave flip-flop. However, the inventive concept is not limited thereto, and the technical idea of the inventive concept can be modified without limitation and applied to other semiconductor devices.

The main stage 100 receives the first data ID and the first clock CK1. The main stage 100 may receive the first data ID based on the first clock CK1 and output the second data OD1. The first clock CK1 may be provided from the clock generating unit 300 .

The slave stage 200 receives the second clock CK2 and the second data OD1. The slave stage 200 may receive the second data OD1 based on the second clock CK2 and output the third data OD2. In this example embodiment, the second clock CK2 may also be supplied from the clock generating unit 300 . Here, the first data ID may be input data input to the semiconductor circuit 1 , the second data OD1 may be the first output data output from the master stage 100 , and the third data OD2 may be the second output data output from the slave stage 200 .

On the other hand, the second clock CK2 provided to the slave stage 200 may include a first sub-clock CK2-1 and a second sub-clock CK2-2. The main stage 100 may use a first clock CK1 and a logic operation signal MCK1 obtained by performing a logic operation on the first clock CK1 and the first data ID, which will be described later. Hereinafter, a configuration of dividing the second clock CK2 into a plurality of sub-clocks and applying the divided sub-clocks to the slave stage 200 will be described, but the inventive concept is not limited thereto.

2 , the main stage 100 may include, for example, a first circuit 101 , a second circuit 103 , a first inverter IN11 , a first gate G11 , a second inverter IN12 and a first keeper 41 .

The first circuit 101 and the second circuit 103 are connected in series around the first node N1. The first circuit 101 is connected to the first voltage terminal, and the second circuit 103 is connected to the second voltage terminal. For example, the first voltage may be a power supply voltage, and the second voltage may be a ground voltage, but not limited thereto.

The first circuit 101 may be formed by connecting the first transistor MP11 and the second transistor MP12 in series. The second circuit 103 may include a third transistor MN11. For example, the first transistor MP11 may be a PMOS transistor, the second transistor MP12 may be a PMOS transistor, and the third transistor MN11 may be an NMOS transistor. The first circuit 101 may receive the first data ID and the first clock CK1, and may change the second data OD1 by the received data. The second circuit 103 may receive the logically operated signal through the first gate G11 to perform an operation, and change the second data OD1. In detail, the first circuit 101 may change the second data OD1 to a first level, and the second circuit 103 may change the second data OD1 to a second level. For example, the first level may be a logic low level and the second level may be a logic high level. The details thereof will be described later.

The first inverter IN11 inverts the first data ID and generates inverted data IDB. The first data ID may be, for example, input data received by the main stage 100 . The first inverter IN11 may be connected to the first transistor MP11, and the inverted data IDB of the first data ID may be supplied to the first transistor MP11. The inverted data IDB may gate the first transistor MP11.

The second transistor MP12 may receive the first clock CK1 and may be gate-controlled by the first clock CK1.

The first gate G11 receives the first data ID and the first clock CK1. The first gate G11 generates a logic operation signal MCK1 by performing a first logic operation of the received first data ID and the first clock CK1, and supplies the generated logic operation signal MCK1 to the third transistor MN11. The first gate G11 may be, for example, a NOR gate. Therefore, the first logic operation may be a NOR logic operation. The logic operation signal MCK1 may gate control the third transistor MN11.

The second inverter IN12 may be connected between the first node N1 and the second node N2. The second inverter IN12 may invert the signal of the first node N1 and output the inverted signal to the second node N2, and the output signal may be the second data OD1.

The first holder 41 may be connected between the first node N1 and the second node N2. The first holder 41 may be connected in parallel to the second inverter IN12. The first holder 41 may operate using the first clock CK1 and the logic operation signal MCK1. The first holder 41 may latch the second data OD1. Therefore, the second data OD1 can be kept constant without external disturbance.

The slave stage 200 may include a fourth transistor MN21, a fifth transistor MP21, a second holder 42 and a third inverter IN21.

The fourth transistor MN21 and the fifth transistor MP21 may be connected in parallel between the second node N2 and the third node N3. For example, the fourth transistor MN21 may be an NMOS transistor, and the fifth transistor MP21 may be a PMOS transistor. The fourth transistor MN21 may be gate-controlled by the second sub-clock CK2-2, and the fifth transistor MP21 may be gate-controlled by the first sub-clock CK2-1. The fourth transistor MN21 and the fifth transistor MP21 may determine whether to transfer the second data OD1 to the third node N3.

The third inverter IN21 is connected to the third node N3, and inverts the signal transmitted to the third node N3. The inverted signal inverted by the third inverter IN21 may be the third data OD2.

The second holder 42 may be connected to the third contact N3. The second holder 42 may include a fourth inverter IN22 and a fifth inverter IN23. The fourth inverter IN22 and the fifth inverter IN23 may be connected in series, and the fourth inverter IN22 may receive the first sub-clock CK2-1 and the second sub-clock CK2-2 to operate. The second holder 42 may latch the signal supplied to the third contact N3.

Referring to FIG. 1 , the clock generating unit 300 may receive the reference clock CK, and generate the first clock CK1 and the second clock CK2 from the reference clock CK. The second clock CK2 may include a first sub-clock CK2-1 and a second sub-clock CK2-2.

In this example embodiment, the first clock CK1 and the second clock CK2 may be different from each other. In other words, the phase of the first clock CK1 is different from the phase of the second clock CK2. In detail, the first clock CK1 and the second clock CK2 may be generated such that at least one of the edges of the first clock CK1 and the second clock CK2 becomes a non-overlapping edge. In more detail, the first clock CK1 and the second clock CK2 may be generated such that the first edge of the first clock CK1 does not overlap with the first edge of the second clock CK2, and at least a portion of the first clock CK1 is second. The edge overlaps with the second edge of the second clock CK2. For example, the first edge may be the rising edge RE, and the second edge may be the falling edge FE, but is not limited thereto. The first edge may be a falling edge and the second edge may be a rising edge.

Referring to FIG. 2 , the clock generating unit 300 may include a sixth inverter IN31 and a seventh inverter IN32.

In the semiconductor circuit 1 of FIG. 2 , the first clock CK1 may be the same as the reference clock CK. Therefore, the clock generation unit 300 may provide the reference clock to the main stage 100 as it is.

The first sub-clock CK2-1 may be generated by inverting the reference clock CK by the sixth inverter IN31. Also, the second sub-clock CK2-2 may be generated by inverting the first sub-clock CK2-1 by the seventh inverter IN32.

The operation of the semiconductor circuit 1 according to example embodiments of the inventive concepts will be described with reference to FIG. 3 and Table 1 .

FIG. 3 and Table 1 are diagrams and tables for explaining the operation of the semiconductor circuit 1 . FIG. 3 is a diagram showing the operation timing of the semiconductor circuit 1 , and Table 1 is a table showing the output of the first gate G11 according to its input.

Table 1

Before explaining the operation of the semiconductor circuit 1 in detail, some terms that can represent the operation characteristics of the flip-flop circuit will be described.

First, the sampling window Tsw represents the time required to hold the input signal in order for the flip-flop circuit to read the data value of the input signal. The sampling window can be expressed as Equation 1 below.

[Equation 1]

Sampling window (Tsw) = data setup time (Tsetup) + data hold time (Thold)

Here, the data setup time Tsetup represents a time provided in advance in order for the flip-flop circuit to accurately read the data value from the input signal. That is, the data setup time Tsetup is an index indicating the time required for the flip-flop circuit to prepare for a read operation before the clock signal is applied so that the flip-flop circuit can accurately read the data value from the input signal.

In the inventive concept, the data setup time Tsetup represents a time that should be provided in advance in order to accurately read the value of the first data ID when the second data OD1 is changed by the first data ID. The data setup time Tsetup may include a data setup rise time Tsr and a data setup fall time Tsf. The data setup rise time Tsr represents the time that should be provided in order to accurately read the rising edge RE of the first data ID (ie, in order to accurately read the logic high level), and the data setup fall time Tsf represents the time required to read the first data ID. The time that the falling edge FE of the data ID (ie, to accurately read the logic low level) should be provided.

3 , it can be seen that when the first data ID changes to a logic high level at the data setup rise time Tsr or to a logic low level at the data setup fall time Tsf, the second data OD1 changes.

For example, for the data setup rise time Tsr, the logic high level of the first data ID should be read when the first clock CK1 is applied. When the first clock CK1 has a constant value C or greater, the rising edge RE of the first data ID should also have a constant value D sufficient to read a logic high level. Therefore, in FIG. 3, the time between C and D can be considered as the data setup rise time Tsr. Since the data settling fall time Tsf can be derived from the data settling rise time Tsr class, the description thereof will be omitted.

On the other hand, the data hold time Thold represents the time for which the input signal should be held in order for the flip-flop circuit to accurately read the data value from the input signal. That is, the data hold time Thold is an index indicating the time for which the input signal should be held after the clock signal is applied so that the flip-flop circuit can accurately read the data value from the input signal.

In the inventive concept, the data holding time Thold represents the time during which the first data ID should be held in order to accurately read the value of the first data ID to keep the second data OD1 constant. The data hold time Thold may include a data hold rise time Thr and a data hold fall time Thf. The data hold rise time Thr represents the time during which the first data ID should be held in order to accurately read the logic low level just before the rising edge RE of the first data ID is generated, and the data hold fall time Thf represents the time for which the first data ID should be held just before the first data ID's rising edge RE is generated. The time that the first data ID should be held by reading the logic high level exactly before the falling edge FE of the data ID is generated.

Referring to FIG. 3, it can be seen that even if the first data ID showing the data holding rising time Thr and the data holding falling time Thf is changed to the first logic high level or the logic low level, the second data OD1 remains constant .

For example, for the data hold fall time Thf, the logic high level of the first data ID should be read when the first clock CK1 is applied. When the first clock CK1 has a constant value A or more, the falling edge FE of the first data ID should maintain a constant value B or more sufficient to read a logic high level. Therefore, in FIG. 3, the time between A and B is considered as the data hold fall time Thf. Since the data hold rise time Thr can be derived from the data hold fall time Thf class, the description thereof will be omitted. In the semiconductor circuit 1 according to example embodiments of the inventive concept, the high sampling window Tsw_high may be obtained from the sum of the data setup rise time Tsr and the data hold fall time Thf, and the high sampling window Tsw_high may be obtained from the sum of the data setup fall time Tsf and the data hold rise time Thr and get the low sampling window Tsw_low. In other words, the high sampling window Tsw_high represents the sum of the time provided for reading the level of the first data ID as a logic high level and the time during which the level of the first data ID should be kept at a logic high level.

On the other hand, the low sampling window Tsw_low represents the sum of the time that should be provided to read the level of the first data ID as a logic low level and the time that the level of the first data ID should be kept at the logic low level.

In a general flip-flop circuit, as the size of the sampling window becomes smaller, the flip-flop circuit can operate at a higher speed.

3 and Table 1, if the first data ID is applied to the main stage 100, the first data ID is directly output as the second data OD1 through the main stage 100 (operation (1)). In detail, since the level of the first clock CK1 becomes a high level when the level of the first data ID is a logic low level, both the first transistor MP11 and the second transistor MP12 are turned on. However, the third transistor MN11 remains in an off state. Therefore, the first node N1 is maintained at the high level, and as a result, the second data OD1 is maintained at the first level (logic low level) (operation (2)).

Since the level of the first clock CK1 is a logic high level, the level of the first sub clock CK2-1 becomes a logic low level, and the level of the second sub clock CK2-2 becomes a logic high level. Since the first sub-clock CK2-1 is generated by the sixth inverter IN31, the phase of the first sub-clock CK2-1 is delayed by a certain time compared to the phase of the first clock CK1. Since the second sub-clock CK2-2 is generated by the seventh inverter IN32, the phase of the second sub-clock CK2-2 is delayed by a certain time compared to the phase of the first sub-clock CK2-1. Since the above-described relationship between the reference clock CK and the first and second sub-clocks CK2-1 and CK2-2 can be derived from the above-described configuration of the clock generating unit 300, a detailed description thereof will be omitted.

On the other hand, if the first sub clock CK2-1 is a logic high level and the second sub clock CK2-2 is a logic low level as described above, the fourth transistor MN21 and the fifth transistor MP21 are turned off, and the slave stage 200 is disabled. Therefore, the first data ID cannot be latched to the slave stage 200 .

Then, if the rising edge RE of the first clock CK1 is formed, the second transistor MP12 is turned off. However, the level of the logic operation signal MCK1 generated by the first gate G11 remains at a logic low level. Therefore, the third transistor MN11 is still in an off state, and the first node N1 is kept at a logic high level.

Since the rising edge RE of the first clock CK1 is formed, the first sub-clock CK2-1 and the second sub-clock CK2-2 have a falling edge FE and a rising edge RE, respectively. Therefore, the slave stage 200 is enabled. Therefore, the second data OD1 is supplied to the slave stage 200, and the third inverter IN21 inverts the second data OD1 to output the third data. The third data OD2 may be at a logic high level.

Then, if the falling edge FE of the first data ID is formed, the rising edge of the inverted data IDB is formed (operation (3)), wherein the first data ID is time-delayed by the first inverter IN11 to generate the Describe the inverted data IDB. The inverted data IDB remains at a logic high level to turn off the first transistor MP11. However, since the logic operation signal MCK1 is still at a logic low level, the third transistor MN11 is in an off state, and thus the second data OD1 remains at a logic low level.

On the other hand, since the rising edge RE of the first clock CK1 and the falling edge FE of the first data ID partially overlap each other, a local change M1 may occur in the logic operation signal MCK1. However, such a local change does not exert an influence on the third transistor MN11. Furthermore, local changes M1 may not occur.

Then, if the falling edge FE of the first clock CK1 is formed, the rising edge RE of the logic operation signal MCK1 may be formed (operation (4)). By the logic operation signal MCK1, the third transistor MN11 is turned on, and the first node N1 is changed to a logic low level (operation (5)). Therefore, the second data OD1 is delayed for a certain time by the second inverter IN12, and is changed to a logic high level (operation (6)). As a result, the first data ID may be output as the first data ID at the falling edge FE of the first clock CK1.

If the falling edge FE of the first clock CK1 is formed, the slave stage 200 is disabled and the second data OD1 cannot be latched. Therefore, the third data OD2 is maintained at a logic high level.

On the other hand, referring to Table 1, it can be seen that the logic operation signal MCK1 is at a logic high level only when the first clock CK1 and the first data ID are both at a logic low level.

Referring again to FIG. 3 , if the rising edge RE of the first clock CK1 is formed with the first data ID kept in the logic low state, the first transistor MP11 , the second transistor MP12 and the third transistor MN11 are all turned off, and Main stage 100 is disabled. Therefore, the second data OD1 remains at a logic high level. Furthermore, if the rising edge RE of the first clock CK1 is formed, the slave stage 200 is enabled. The second data OD1 of a logic high level is received from the stage 200 and forms a falling edge of the third data OD2. As a result, at the rising edge RE of the first clock CK1, the first data ID is read from the stage 200 and the read first data ID is output as the third data OD2 (operation (7)).

Then, if the rising edge RE of the first data ID is formed, the first transistor MP11 is turned on, but the second transistor MP12 and the third transistor MN11 are still in the off state. Therefore, the main stage 100 is in a disabled state, and the second data OD1 is kept constant (operation (8)). Since the first clock CK1 is at a logic high level, the slave stage 200 is enabled, and the third inverter IN21 inverts the second data OD1 and outputs the inverted second data as the third data OD2.

Then, if the first clock CK1 is at a logic low level and the first data ID is at a logic low level, the first transistor MP11 is turned off. At this time, since the logic operation signal MCK1 is at a logic high level, the third transistor MN11 is turned on, and the first node N1 is at a logic low level. Therefore, the second data OD1 is at a logic high level. However, since the first clock CK1 is at a logic low level, the slave stage 200 is disabled, and thus the slave stage 200 cannot latch the second data OD1.

If the rising edge RE of the first data ID is formed, the first transistor MP11 and the second transistor MP12 are turned on, and the rising edge of the first node N1 is formed (operation (9)). At this time, the falling edge FE of the logic operation signal MCK1 is formed, and the third transistor MN11 is turned off (operation (10)). If the rising edge RE of the first node N1 is formed, the second inverter IN12 delays the second data OD1 for a certain time, and forms the falling edge FE of the second data OD1. At this time, the first clock CK1 is at a logic low level, and the slave stage 200 is in a disabled state.

If the rising edge RE of the first clock CK1 is formed, the second transistor MP12 and the third transistor MN11 are turned off, and the main stage 100 is disabled. Therefore, the second data OD1 is maintained at a logic low level (operation (11)). At the rising edge RE of the first clock CK1, the slave stage 200 is enabled, and receives the second data OD1 and inverts the second data OD1 to output the inverted second data OD1 as the third data OD2. Since the subsequent operations of the semiconductor circuit 1 can be sufficiently anticipated by derivation from the above, the description thereof will be omitted.

The operation of the semiconductor circuit 1 according to this embodiment as described above is summarized as follows.

First, after the rising edge RE of the first clock CK1 is formed, the falling edge of the first sub clock CK2-1 is formed. Therefore, the master stage 100 is disabled based on the time point T1 of FIG. 3 , and the slave stage 200 is enabled based on the time point T2 of FIG. 3 .

That is, since the falling edge FE of the first sub clock CK2-1 cannot be formed to overlap with the rising edge RE of the first clock CK1, the enable/disable operations of the master stage 100 and the slave stage 200 are sequentially performed.

If the enable/disable operations of the master stage 100 and the slave stage 200 are not sequentially performed, the first data ID is not output as the third data OD2 to match the clock signal, but has been stored in the master stage 100 or the slave stage 200 The data of are output as third data OD2 regardless of the first data ID. Such failure causes the sampling window of the semiconductor circuit 1 (eg, flip-flop) to increase, and thus the operational reliability of the device deteriorates.

However, in the semiconductor circuit 1, any possible failure is blocked in advance by the above-described configuration, so that the operational reliability of the semiconductor circuit 1 can be improved.

In addition, the timing skew of the main stage 100 has a great influence on the size and symmetry of the sampling window. However, according to the circuit configuration of the semiconductor circuit 1, the timing skew of the main stage 100 can be reduced, so that the sampling window can be symmetrically formed in a small size.

In the semiconductor circuit 1 constructed as above, the low sampling window Tsw_low and the high sampling window Tsw_high have been measured to be about 2 to 5 ps and about 3 to 7 ps, respectively. Therefore, it can be confirmed that there is almost no time difference between the low sampling window Tsw_low and the high sampling window Tsw_high, so that the sampling window Tsw is formed symmetrically. Since the sampling windows Tsw are formed symmetrically, the reliability of the semiconductor circuit 1 can be improved.

On the other hand, the master stage 100 and the slave stage 200 may have different threshold voltages Vt. For example, the threshold voltage of the master stage 100 may be lower than the threshold voltage of the slave stage 200 . If the threshold voltage of the master stage 100 is configured to be lower than the threshold voltage of the slave stage 200, the sampling window Tsw may be formed in a small size. Table 2 below shows the ratio of power consumption to sampling window Tsw in the case where the threshold voltages are different from each other.

Table 2

High Vt Low Vt Low Vt–High Vt Tsw 1 0.76 0.82 leakage power 1 5.78 2.3

Referring to Table 2, if it is assumed that the sampling window Tsw of the semiconductor circuit 1 is 1 and the power loss of the semiconductor circuit 1 is 1 in the case where both the master stage 100 and the slave stage 200 have high threshold voltages, then in the master stage 100 and the slave stage 200 with low threshold voltages, the sampling window Tsw is increased by a factor of 0.76, and the power loss is increased by a factor of 5.789. Since the circuit can operate at high speed as the threshold voltage decreases, the sampling window can be reduced. However, since the leakage current increases to the above-mentioned level, the power loss increases by a factor of 5.78.

The above problem can be solved by making the threshold voltages of the master stage 100 and the slave stage 200 different from each other. For example, the threshold voltage of the master stage 100 may be configured to be lower than the threshold voltage of the slave stage 200 . In this case, compared to the case where the semiconductor circuit 1 has a high threshold voltage, the sampling window is increased by a factor of 0.82, and the power loss is increased by a factor of 2.3

Compared to the case where both the master 100 and the slave 200 have low threshold voltages, it can be confirmed that the sampling window is reduced in a similar manner and the power consumption is reduced to less than half. Therefore, if the threshold voltage of the master stage 100 is configured to be lower than the threshold voltage of the slave stage 200, the power loss is minimized and the sampling window is reduced.

Here, the threshold voltage of the main stage 100 may represent threshold voltages of active devices used in the main stage 100 (eg, threshold voltages of the first transistor MP11 , the second transistor MP12 and the third transistor MN11 and the first keeper 41 ) , the threshold voltage of the slave stage 200 may represent the threshold voltage of the active devices used in the slave stage 200 (eg, the threshold voltages of the fourth transistor MN21 and the fifth transistor MP21 and the threshold voltage of the second keeper 42 ).

4 and 5, a semiconductor circuit 2 according to another embodiment will be described. Explanation of the contents overlapping with the above description will be omitted, and explanation will be made focusing on the differences between the embodiments.

FIG. 4 is a circuit diagram of the semiconductor circuit 2 , and FIG. 5 is a diagram illustrating an operation timing of the semiconductor circuit 2 of FIG. 4 .

4 , according to the semiconductor circuit 2 , unlike the semiconductor circuit 1 of FIG. 2 , the clock generation unit 310 additionally includes a first delay unit 51 . In detail, the first delay unit 51 receives the reference clock CK and generates the first clock CK1 by delaying the reference clock CK by a certain time. In order to delay the reference clock CK, the first delay unit 51 may include two inverters IN33 and IN34 connected in series. The first delay unit 51 may generate the first clock CK1 by inverting the reference clock CK twice. Similar to the clock generating unit 300 of FIG. 2 , the second clock CK2 may be generated using the first clock CK1 .

Since the clock generating unit 310 includes the first delay unit 51, as shown in FIG. 5, the phase of the first clock CK1 applied to the host 100 may be delayed. If the phase of the first clock CK1 is delayed, the first data ID and the rising edge RE and the falling edge FE of the first clock CK1 can be accurately distinguished, so that errors of the semiconductor circuit 2 can be prevented. Since the phase of the first clock CK1 is delayed as much as the first size W1, the phases of the first sub-clock CK2-1 and the second sub-clock CK2-2 constituting the second clock CK2 are delayed as much as the first size W1 .

6 and 7 , a semiconductor circuit 3 according to another example embodiment of the inventive concept will be described. Explanation of the contents overlapping with the above description will be omitted, and explanation will be made focusing on the differences between the embodiments.

FIG. 6 is a circuit diagram of the semiconductor circuit 3 , and FIG. 7 is a timing chart of the first clock and the second clock of FIG. 6 .

Referring to FIG. 6 , the semiconductor circuit 3 is different from the semiconductor circuit 2 of FIG. 4 in that the clock generating unit 320 has a different configuration. In detail, in a similar manner to the semiconductor circuit 2 of FIG. 4 , the first clock CK1 is generated by delaying the phase of the reference clock CK by the first delay unit 51 as large as the first magnitude W1. However, in the case where the first sub-clock CK2-1 is generated using the first clock CK1, the second gate G31 is used in place of the sixth inverter IN31. The second gate G31 may be, for example, a NAND gate. The second gate G31 generates the first sub-clock CK2-1 by performing a NAND logic operation on the first clock CK1 and the reference clock CK. As shown in FIG. 7 , the first sub clock CK2-1 may shorten the time of the logic low level compared with the first clock CK1. When the first sub-clock CK2-1 is at a logic low level and the second sub-clock CK2-2 is at a logic high level, the slave stage 200 may be enabled, and the second gate G31 may be used to shorten when the slave stage 200 is held at time in the enabled state. If the enable time of the slave stage 200 is shortened, the master stage 100 and the slave stage 200 can be prevented from being enabled or disabled at the same time. The second sub-clock CK2-2 may be generated by inversion of the first sub-clock CK2-1.

8 , a semiconductor circuit 4 according to another example embodiment of the inventive concept will be described. Explanation of the contents overlapping with the above description will be omitted, and explanation will be made focusing on the differences between the embodiments.

FIG. 8 is a circuit diagram of the semiconductor circuit 4 .

8 , the semiconductor circuit 4 of FIG. 8 is different from the semiconductor circuit 1 of FIG. 2 in that the clock generation unit 330 includes the second delay unit 53 . The second delay unit 53 may be connected to the sixth inverter IN31 in series. The second delay unit 53 may be provided by connecting two inverters IN35 and IN36 in series.

The first clock CK1 is the same as the reference clock CK. The first sub clock CK2- 1.

9 , a semiconductor circuit 5 according to another example embodiment of the inventive concept will be described. Explanation of content overlapping with the above description will be omitted.

FIG. 9 is a circuit diagram of the semiconductor circuit 5 .

9 , the semiconductor circuit 5 of FIG. 9 is different from the semiconductor circuit 4 of FIG. 8 in that the second gate G31 in the clock generating unit 340 can replace the sixth inverter IN31. The second gate G31 may be, for example, a NAND gate. The first clock CK1 may be the same as the reference clock CK. The first sub clock CK2-1 may be generated by delaying the first clock CK1 through the second delay unit 53 and performing a NAND logic operation on the delayed first clock CK1 and the first clock CK1. The second sub-clock CK2-2 may be generated by inverting the first sub-clock CK2-1.

10 , a semiconductor circuit 6 according to another example embodiment of the inventive concept will be described. Explanation of content overlapping with the above description will be omitted.

FIG. 10 is a circuit diagram of the semiconductor circuit 6 .

Referring to FIG. 10 , the semiconductor circuit 6 of FIG. 10 is different from the semiconductor circuit 1 of FIG. 2 in the main stage 120 and the clock generation circuit 350 .

In detail, the semiconductor single circuit 6 of FIG. 10 includes a first inverter IN11 , a third gate G12 , a third circuit 105 , a fourth circuit 107 , a first holder 41 and a second inverter IN12 . The third circuit 105 may be connected to the third voltage and may include a sixth transistor MP13. The sixth transistor MP13 may be, for example, a PMOS transistor. The sixth transistor MP13 may be gate-controlled by the logic operation signal MCK2 generated by the third gate G12. The third voltage may be, for example, the power supply voltage. The third circuit 105 may change the level of the first node N1 to a logic high level. That is, the third circuit 105 may change the level of the second data OD1 to a logic low level.

The fourth circuit 107 may be connected to a fourth voltage, and may include a seventh transistor MN12 and an eighth transistor MN13. The seventh transistor MN12 and the eighth transistor MN13 may be connected in series, and may be, for example, NMOS transistors. For example, the fourth voltage may be a ground voltage. The fourth circuit 107 may change the level of the first node NI to a logic low level. That is, the fourth circuit 107 may change the level of the second data OD1 to a logic high level.

The seventh transistor MN12 may be gate-controlled by the inverted data IDB of the first data ID inverted by the first inverter IN11. The eighth transistor MN13 is gate-controlled by the first clock CK1.

The third gate G12 may perform a logic operation of the first data ID and the first clock CK1 and may provide the logic operation signal MCK2 to the third circuit 105 . The third gate G12 may be, for example, a NAND gate, and may perform a NAND logic operation of the first data ID and the first clock CK1.

The third circuit 105 and the fourth circuit 107 may be connected in series, and may be connected to the first node N1. The second inverter IN12 is connected to the first node N1, and inverts the signal of the first node N1 to generate the second data OD1. The first holder 41 is connected to the first node N1, and may be connected in parallel to the second inverter IN12.

The clock generating unit 350 may include a seventh inverter IN32 and an eighth inverter IN37. The eighth inverter IN37 generates the first clock CK1 by inverting the reference clock CK. The first sub-clock CK2-1 may be the same as the first sub-clock CK1, and the second sub-clock CK2-2 may be generated by inverting the first sub-clock CK2-1 by the seventh inverter IN32.

The slave stage 200 of the semiconductor circuit 6 of FIG. 10 is the same as the slave stage of the semiconductor circuit 1 of FIG. 2 .

The semiconductor circuit 6 of FIG. 10 is a circuit formed by inversion of the semiconductor circuit 1 of FIG. 2 . In other words, the semiconductor circuit 1 of FIG. 2 operates in a similar manner to the semiconductor circuit 6 of FIG. 10 , but its circuit configuration is opposite to that of the semiconductor circuit 6 of FIG. 10 . In detail, the third gate G12 is formed of a NAND gate instead of a NOR gate; the third circuit 105 gate-controlled by the third gate G12 is connected to the supply voltage and includes a PMOS transistor. The fourth circuit 107 includes two NMOS transistors and is connected to ground voltage. Also, the first clock CK1 supplied to the main stage 120 is generated by inverting the reference clock CK.

Since it can be deduced from the above that the semiconductor circuit 6 of FIG. 10 has a circuit configuration different from that of the semiconductor circuit 1 of FIG. 2 , but the semiconductor circuit 6 of FIG. 10 operates in a similar manner to the semiconductor circuit 1 of FIG. 2 , Therefore, the explanation of the operation of the semiconductor circuit 6 of FIG. 10 will be omitted.

11 , a semiconductor circuit 7 according to another example embodiment of the inventive concept will be described. Explanation of content overlapping with the above description will be omitted

FIG. 11 is a circuit diagram of the semiconductor circuit 7 .

The semiconductor circuit 7 of FIG. 11 is different from the semiconductor circuit 6 of FIG. 10 in the clock generation unit 360 .

Referring to FIG. 11 , the clock generation unit 360 includes the second delay unit 53 . That is, the first clock CK1 is generated by inverting the reference clock CK, and the first sub-clock CK2 - 1 is generated by delaying the phase of the first clock CK1 by the second delay unit 53 . The second sub-clock CK2-2 may be generated by inverting the first sub-clock CK2-1. The second delay unit 53 may be formed by a series connection of two inverters IN35 and IN36.

12 , a semiconductor circuit 8 according to another example embodiment of the inventive concept will be described. Explanation of content overlapping with the above description will be omitted

FIG. 12 is a circuit diagram of the semiconductor circuit 8 .

The semiconductor circuit 8 of FIG. 12 is different from the semiconductor circuit 6 of FIG. 10 in the clock generation unit 370 . In detail, referring to FIG. 12 , the clock generation unit 360 may include the third delay unit 55 . The third delay unit 55 may include a ninth inverter IN38 and a fourth gate G32.

The first clock CK1 is generated by inverting the reference clock CK by the eighth inverter IN37. Also, the first sub clock CK2-1 is generated by performing a logical operation on the reference clock CK and a value obtained by inverting the first clock CK1 via the fourth gate G32. For example, the fourth gate G32 may be a NAND gate, and may generate the first sub clock CK2-1 by performing a logical operation on the reference clock CK and a value obtained by inverting the first clock CK1.

13, a semiconductor system 10 including a semiconductor circuit according to some example embodiments of the inventive concepts will be described.

FIG. 13 is a block diagram of the semiconductor system 10 .

The semiconductor system 10 may include a transmitter 20 and a receiver 30 . The transmitter 20 may transmit the first data ID to the receiver 30 using the reference clock. The receiver 30 may receive the first data ID, and may process or perform sampling of the first data ID using the reference clock CK. One of the semiconductor circuits 1 to 8 as described above may be formed at the input terminal of the receiver 30 . The input terminal of the receiver 30 may receive the first data ID and the reference clock CK, and provide the third data OD2 to the receiver 30 .

Here, the semiconductor system 10 may be, for example, a processor, but is not limited thereto. The semiconductor system 10 can be applied to a semiconductor device for transmitting data.

14, a computing system that can employ the above-described semiconductor circuits 1 to 8 will be described.

FIG. 14 is a block diagram showing the configuration of the computing system 501 .

14, a computing system 501 includes a central processing unit 500, an accelerated graphics port (AGP) device 510, a main memory 600, a memory (eg, SSD or HDD) 540, a north bridge 520, a south bridge 530, a keyboard controller 560, and a printer control device 550.

The computing system 501 shown in FIG. 14 may be a personal computer or a notebook computer. However, the inventive concept is not limited thereto, and the example of the computing system 501 may be modified without limitation.

In computing system 501 , central processing unit 500 , AGP device 510 and main memory 600 may be connected to north bridge 520 . However, the inventive concept is not limited thereto, and the north bridge 520 may be modified to be included in the central processing unit 500 .

AGP may be a bus standard that enables accelerated implementation of three-dimensional (3D) graphics, and AGP device 510 may include a video card that reproduces monitor images.

The central processing unit 500 may perform various types of logical operations required to drive the computing system 101, and may execute OS and application programs. At least one of the semiconductor circuits 1 to 8 may be employed as part of the central processing unit 500 .

The main memory 600 may load data required to perform operations of the central processing unit 500 from the memory 540 to store the loaded data.

A memory 540 , a keyboard controller 560 , a printer controller 550 and various types of peripheral devices (not shown) may be connected to the south bridge 530 .

The storage 540 is a large-capacity data storage that stores file data and the like, and can be implemented by, for example, an HDD or an SSD. However, the inventive concept is not limited to such an example.

Also, the computing system 501 has a structure in which the memory 540 is connected to the south bridge 530, but the inventive concept is not limited thereto. The structure can be modified in such a way that the memory 540 is connected to the north bridge 520 or the memory 540 is connected directly to the central processing unit 500 .

Then, an electronic system 900 that can employ the semiconductor circuits 1 to 8 will be described with reference to FIG. 15 .

FIG. 15 is a block diagram showing the configuration of an electronic system 900 in which the semiconductor circuits 1 to 8 can be employed.

Referring to FIG. 15 , electronic system 900 may include memory system 902 , processor 904 , RAM 906 and user interface 908 .

Memory system 902 , processor 904 , RAM 906 and user interface 908 may use bus 910 to perform data communication with each other.

The processor 904 may be used to execute programs and control the electronic system 900 , and the RAM 906 may be used as the operating memory of the processor 904 . The processor 904 may include at least one of the semiconductor circuits 1 to 8 as a part of the constituent elements. The processor 904 and RAM 906 may be implemented as packaged as one semiconductor device or semiconductor package.

User interface 908 may be used to input data to and output data from electronic system 900 .

The memory system 902 may store codes for operations of the processor 904, data processed by the processor 904, or data input from the outside. Memory system 902 may include a separate controller for its operation, and may be configured to additionally include an error correction block. Error correction blocks may be configured to detect and correct errors in data stored in memory system 902 using error correction codes (ECC).

The memory system 902 may be integrated into one semiconductor device. Illustratively, the memory system 902 may be integrated into one semiconductor device to constitute a memory card. For example, the memory system 902 may be integrated into a semiconductor device to construct a memory card, such as a PC Card (Personal Computer Memory Card International Association (PCMCIA)), Compact Flash (CF) card, Smart Media Card (SM or SMC), Memory Stick , Multimedia Card (MMC, RS-MMC, MMCmicro), SD Card (SD, miniSD, microSD or SDHC), Universal Flash Storage (UFS), etc.

The electronic system 900 shown in FIG. 15 can be applied to electronic control devices of various electric appliances. FIG. 16 is a diagram illustrating an example in which the electronic device of FIG. 15 is applied to a smartphone. In the case where the electronic system 900 (of FIG. 15 ) is applied to the smartphone 1000 , at least one of the semiconductor circuits 1 to 8 may be employed as a partial constituent element of an application processor (AP).

Additionally, the electronic system 900 (of FIG. 15) may be provided as an electronic device such as a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a nettable, a wireless phone, a mobile phone , smartphones, e-books, portable multimedia players (PMP), portable game consoles, navigation devices, black boxes, digital cameras, 3D TV receivers, digital audio recorders, digital audio players, digital image recorders, digital Image player, digital video recorder, digital video player, device that can send and receive information in a wireless environment, one of various electronic devices that constitute a home network, one of various electronic devices that constitute a computer network, one of various electronic devices that constitute a telecommunication One of various electronic devices of a network, one of various constituent elements of an RFID device) or one of various constituent elements of a computing system.

While example embodiments of the inventive concept have been described for illustrative purposes, it will be apparent to those skilled in the art that various modifications are possible without departing from the scope and spirit of the inventive concept as disclosed in the accompanying claims. Modifications, additions and substitutions.

Claims (18)

1. A flip-flop, comprising:

a first circuit connected between a first voltage terminal and a first node and configured to change a voltage of the first node to a first level of the first voltage terminal according to first data and a first clock;

a first gate configured to perform a logical operation on first data and a first clock;

a second circuit connected between the first node and a second voltage terminal and configured to change a voltage of the first node to a second level of the second voltage terminal according to an output of the logical operation,

wherein the second clock provided to the slave stage of the flip-flop comprises a first sub-clock and a second sub-clock, the second sub-clock being an inverse of the first sub-clock,

wherein the second clock is generated based on the first clock,

wherein the first circuit comprises:

a first inverter configured to invert the first data;

a first transistor and a second transistor connected in series between a first voltage terminal and a first node and configured to receive inverted first data and a first clock, respectively, wherein the second circuit includes:

and a third transistor connected between the first node and the second voltage terminal and configured to receive an output of the logical operation, wherein the first clock is generated by the reference clock, and the first sub-clock is generated by performing a NAND logical operation on the reference clock and the first clock.

2. The flip-flop of claim 1, further comprising:

a clock generation unit configured to receive a reference clock and generate a first clock and a second clock.

3. The flip-flop according to claim 2, wherein the clock generation unit is configured to generate the first sub-clock by inverting the first clock.

4. The flip-flop of claim 2, wherein the clock generation unit comprises:

a first delay unit configured to delay a phase of a first clock and generate a second clock using the delayed first clock.

5. The flip-flop of claim 4, wherein the clock generation unit is configured to generate the first sub-clock by performing a NAND logic operation on the reference clock and the delayed first clock.

6. The flip-flop of claim 4, wherein the first clock and the reference clock are the same.

7. The flip-flop according to claim 2, wherein the clock generation unit is configured to generate the first clock by delaying a phase of the reference clock.

8. The flip-flop according to claim 2, wherein the clock generation unit is configured to generate the first clock by inverting the reference clock.

9. The flip-flop of claim 8, wherein the clock generation unit is configured to generate the first sub-clock by performing a NAND logic operation on the inverted signal of the first clock and the reference clock.

10. The flip-flop of claim 1, further comprising:

a keeper circuit configured to hold a voltage of the first node based on the first clock and an output of the logical operation.

11. A semiconductor circuit, comprising:

a master circuit and a slave circuit configured to receive a first clock and a second clock, respectively, the first clock and the second clock having different phases,

wherein the main circuit comprises a first transistor, a second transistor, a third transistor, a first inverter and a first gate,

wherein the first transistor, the second transistor and the third transistor are connected in series between a first voltage terminal and a second voltage terminal,

wherein the first inverter is configured to invert input data and gate the first transistor,

wherein the first gate is configured to gate control the third transistor, the first gate is configured to perform a logic operation on the input data and the first clock,

wherein the second transistor is configured to receive a first clock,

wherein the second clock includes a first sub-clock and a second sub-clock, the second sub-clock being an inverse of the first sub-clock,

wherein the first clock is generated by a reference clock, and the first sub-clock is generated by performing a NAND logic operation on the reference clock and the first clock.

12. The semiconductor circuit according to claim 11, wherein a threshold voltage of the master circuit is lower than a threshold voltage of the slave circuit.

13. The semiconductor circuit according to claim 11, wherein the first transistor is connected to a first voltage terminal, the third transistor is connected to a second voltage terminal, and the second transistor is located between the first transistor and the third transistor.

14. The semiconductor circuit according to claim 13, wherein the first transistor and the second transistor are configured to change input data to a first level, and the third transistor is configured to change input data to a second level.

15. The semiconductor circuit of claim 11, further comprising:

a keeper circuit configured to hold a voltage of a node to which the second transistor and the third transistor are connected, based on the first clock and an output of the logical operation.

16. The semiconductor circuit according to claim 11, wherein the logical operation is a NOR logical operation.

17. The semiconductor circuit according to claim 16, wherein the first transistor and the second transistor are PMOS transistors, and wherein the third transistor is an NMOS transistor.

18. The semiconductor circuit according to claim 13, wherein the first voltage of the first voltage terminal is a power supply voltage, and the second voltage of the second voltage terminal is a ground voltage.

Images